[PATCH 04/10] dt-bindings: pinctrl: add Ambarella CV75 pinctrl

[Long Zhao <longzhao@ambarella.com>]

Add the CV75 pin controller binding and pinmux ID header.

Signed-off-by: Long Zhao <longzhao@ambarella.com>
---
 .../pinctrl/ambarella,cv75-pinctrl.yaml       | 167 ++++++++++++++++++
 .../dt-bindings/pinctrl/ambarella,pinctrl.h   |  11 ++
 2 files changed, 178 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml
 create mode 100644 include/dt-bindings/pinctrl/ambarella,pinctrl.h

diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml
new file mode 100644
index 000000000000..8a331c642fad
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/ambarella,cv75-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ambarella CV75 Pin Controller
+
+maintainers:
+  - Long Zhao <longzhao@ambarella.com>
+
+description:
+  The Ambarella CV75 pin controller configures pin multiplexing, bias and
+  drive strength for the main GPIO banks. Pin multiplexing entries encode
+  the pin number and alternate function with the AMBA_PINMUX() macro from
+  dt-bindings/pinctrl/ambarella,pinctrl.h.
+
+allOf:
+  - $ref: pinctrl.yaml#
+
+properties:
+  compatible:
+    const: ambarella,cv75-pinctrl
+
+  reg:
+    items:
+      - description: GPIO bank 0 registers
+      - description: GPIO bank 1 registers
+      - description: GPIO bank 2 registers
+      - description: IOMUX registers
+
+  reg-names:
+    items:
+      - const: gpio0
+      - const: gpio1
+      - const: gpio2
+      - const: iomux
+
+  interrupts:
+    items:
+      - description: GPIO bank 0 interrupt
+      - description: GPIO bank 1 interrupt
+      - description: GPIO bank 2 interrupt
+
+  ambarella,drive-strength-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: RCT syscon containing the drive-strength registers.
+
+  ambarella,pull-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: Secure scratchpad syscon containing the pull registers.
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^gpio@[0-9a-f]+$":
+    type: object
+    additionalProperties: false
+
+    properties:
+      reg:
+        maxItems: 1
+
+      gpio-controller: true
+
+      "#gpio-cells":
+        const: 2
+
+      gpio-ranges:
+        maxItems: 1
+
+      interrupt-controller: true
+
+      "#interrupt-cells":
+        const: 2
+
+    required:
+      - reg
+      - gpio-controller
+      - "#gpio-cells"
+      - gpio-ranges
+      - interrupt-controller
+      - "#interrupt-cells"
+
+  "^[a-z0-9-]+-pins$":
+    type: object
+    allOf:
+      - $ref: pinmux-node.yaml#
+      - $ref: pincfg-node.yaml#
+    additionalProperties: false
+
+    properties:
+      function: true
+
+      pinmux:
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        minItems: 1
+        maxItems: 96
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+
+      drive-strength:
+        enum: [3, 4, 5, 6, 7, 8, 9, 12]
+
+    required:
+      - function
+      - pinmux
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - ambarella,drive-strength-syscon
+  - ambarella,pull-syscon
+  - "#address-cells"
+  - "#size-cells"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/pinctrl/ambarella,pinctrl.h>
+
+    rct: rct {
+    };
+
+    scratchpad: scratchpad {
+    };
+
+    pinctrl: pinctrl@e4013000 {
+        compatible = "ambarella,cv75-pinctrl";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0xe4013000 0x1000>, <0xe4014000 0x1000>,
+              <0xe4015000 0x1000>, <0xe4010000 0x1000>;
+        reg-names = "gpio0", "gpio1", "gpio2", "iomux";
+        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+        ambarella,drive-strength-syscon = <&rct>;
+        ambarella,pull-syscon = <&scratchpad>;
+
+        gpio: gpio@0 {
+            reg = <0>;
+            gpio-controller;
+            #gpio-cells = <2>;
+            gpio-ranges = <&pinctrl 0 0 95>;
+            interrupt-controller;
+            #interrupt-cells = <2>;
+        };
+
+        uart0-pins {
+            function = "uart0";
+            pinmux = <AMBA_PINMUX(44, 1)>,
+                     <AMBA_PINMUX(45, 1)>;
+            bias-disable;
+            drive-strength = <8>;
+        };
+    };
diff --git a/include/dt-bindings/pinctrl/ambarella,pinctrl.h b/include/dt-bindings/pinctrl/ambarella,pinctrl.h
new file mode 100644
index 000000000000..20463d5acc66
--- /dev/null
+++ b/include/dt-bindings/pinctrl/ambarella,pinctrl.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2026 Ambarella, Inc.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_AMBARELLA_PINCTRL_H
+#define _DT_BINDINGS_PINCTRL_AMBARELLA_PINCTRL_H
+
+#define AMBA_PINMUX(pin, mux)  (((mux) << 12) | (pin))
+
+#endif
--
2.34.1

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