* [PATCH v1 03/11] dt-bindings: pinctrl: add Allwinner B288 pin controller [not found] <20260923201701.43391-1-pmazzini@gmail.com> @ 2026-09-23 20:16 ` Pablo Mazzini 2026-09-24 9:07 ` Andre Przywara 2026-09-23 20:16 ` [PATCH v1 04/11] pinctrl: sunxi: add Allwinner B288 pin controller driver Pablo Mazzini 1 sibling, 1 reply; 7+ messages in thread From: Pablo Mazzini @ 2026-09-23 20:16 UTC (permalink / raw) To: Chen-Yu Tsai, Conor Dooley, Jernej Skrabec, Krzysztof Kozlowski, Linus Walleij, Rob Herring, Samuel Holland Cc: Pablo Mazzini, devicetree, linux-arm-kernel, linux-gpio, linux-kernel, linux-sunxi One controller at 0x01c20800 with four external interrupt banks. Signed-off-by: Pablo Mazzini <pmazzini@gmail.com> --- .../pinctrl/allwinner,sun8i-b288-pinctrl.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml new file mode 100644 index 000000000000..806da97ab708 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/allwinner,sun8i-b288-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner B288 Pin Controller + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Jernej Skrabec <jernej.skrabec@gmail.com> + +properties: + compatible: + const: allwinner,sun8i-b288-pinctrl + + reg: + maxItems: 1 + + interrupts: + description: + One interrupt per bank of external interrupt capable pins. + maxItems: 4 + + clocks: + items: + - description: Bus Clock + - description: High Frequency Oscillator + - description: Low Frequency Oscillator + + clock-names: + items: + - const: apb + - const: hosc + - const: losc + + gpio-controller: true + interrupt-controller: true + gpio-line-names: true + + "#gpio-cells": + const: 3 + + "#interrupt-cells": + const: 3 + +patternProperties: + "-pins$": + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml# + additionalProperties: false + + properties: + pins: true + function: true + bias-pull-up: true + bias-pull-down: true + bias-disable: true + drive-strength: + enum: [10, 20, 30, 40] + + required: + - pins + - function + + "^vcc-p[bcdfg]-supply$": + description: + Power supplies for pin banks. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/sun8i-b288-ccu.h> + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-b288-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "sdc0"; + drive-strength = <30>; + bias-pull-up; + }; + }; -- 2.53.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v1 03/11] dt-bindings: pinctrl: add Allwinner B288 pin controller 2026-09-23 20:16 ` [PATCH v1 03/11] dt-bindings: pinctrl: add Allwinner B288 pin controller Pablo Mazzini @ 2026-09-24 9:07 ` Andre Przywara 2026-09-24 20:16 ` Pablo Mazzini 0 siblings, 1 reply; 7+ messages in thread From: Andre Przywara @ 2026-09-24 9:07 UTC (permalink / raw) To: Pablo Mazzini, Chen-Yu Tsai, Conor Dooley, Jernej Skrabec, Krzysztof Kozlowski, Linus Walleij, Rob Herring, Samuel Holland Cc: devicetree, linux-arm-kernel, linux-gpio, linux-kernel, linux-sunxi Hi Pablo, On 9/23/26 22:16, Pablo Mazzini wrote: > One controller at 0x01c20800 with four external interrupt banks. > > Signed-off-by: Pablo Mazzini <pmazzini@gmail.com> > --- > .../pinctrl/allwinner,sun8i-b288-pinctrl.yaml | 108 ++++++++++++++++++ Why is this a new file? Can't you just add the new compatible string to the existing allwinner,sun4i-a10-pinctrl.yaml binding? Cheers, Andre P.S. Since we have seen this a lot lately: please wait with a new version of your series for a few days, to allow other people to comment, and to allow discussions to settle down. Not everyone can respond quickly. > 1 file changed, 108 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml > new file mode 100644 > index 000000000000..806da97ab708 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml > @@ -0,0 +1,108 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/allwinner,sun8i-b288-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner B288 Pin Controller > + > +maintainers: > + - Chen-Yu Tsai <wens@csie.org> > + - Jernej Skrabec <jernej.skrabec@gmail.com> > + > +properties: > + compatible: > + const: allwinner,sun8i-b288-pinctrl > + > + reg: > + maxItems: 1 > + > + interrupts: > + description: > + One interrupt per bank of external interrupt capable pins. > + maxItems: 4 > + > + clocks: > + items: > + - description: Bus Clock > + - description: High Frequency Oscillator > + - description: Low Frequency Oscillator > + > + clock-names: > + items: > + - const: apb > + - const: hosc > + - const: losc > + > + gpio-controller: true > + interrupt-controller: true > + gpio-line-names: true > + > + "#gpio-cells": > + const: 3 > + > + "#interrupt-cells": > + const: 3 > + > +patternProperties: > + "-pins$": > + type: object > + $ref: /schemas/pinctrl/pincfg-node.yaml# > + additionalProperties: false > + > + properties: > + pins: true > + function: true > + bias-pull-up: true > + bias-pull-down: true > + bias-disable: true > + drive-strength: > + enum: [10, 20, 30, 40] > + > + required: > + - pins > + - function > + > + "^vcc-p[bcdfg]-supply$": > + description: > + Power supplies for pin banks. > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - gpio-controller > + - "#gpio-cells" > + - interrupt-controller > + - "#interrupt-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/sun8i-b288-ccu.h> > + > + pio: pinctrl@1c20800 { > + compatible = "allwinner,sun8i-b288-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; > + clock-names = "apb", "hosc", "losc"; > + gpio-controller; > + #gpio-cells = <3>; > + interrupt-controller; > + #interrupt-cells = <3>; > + > + mmc0_pins: mmc0-pins { > + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; > + function = "sdc0"; > + drive-strength = <30>; > + bias-pull-up; > + }; > + }; ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 03/11] dt-bindings: pinctrl: add Allwinner B288 pin controller 2026-09-24 9:07 ` Andre Przywara @ 2026-09-24 20:16 ` Pablo Mazzini 0 siblings, 0 replies; 7+ messages in thread From: Pablo Mazzini @ 2026-09-24 20:16 UTC (permalink / raw) To: Andre Przywara Cc: Chen-Yu Tsai, Conor Dooley, Jernej Skrabec, Krzysztof Kozlowski, Linus Walleij, Rob Herring, Samuel Holland, devicetree, linux-arm-kernel, linux-gpio, linux-kernel, linux-sunxi Hi Andre, > Can't you just add the new compatible string to the existing > allwinner,sun4i-a10-pinctrl.yaml binding? Done for v2. Thanks, Pablo On Thu, Sep 24, 2026 at 10:07 AM Andre Przywara <andre.przywara@arm.com> wrote: > > Hi Pablo, > > On 9/23/26 22:16, Pablo Mazzini wrote: > > One controller at 0x01c20800 with four external interrupt banks. > > > > Signed-off-by: Pablo Mazzini <pmazzini@gmail.com> > > --- > > .../pinctrl/allwinner,sun8i-b288-pinctrl.yaml | 108 ++++++++++++++++++ > > Why is this a new file? Can't you just add the new compatible string to > the existing allwinner,sun4i-a10-pinctrl.yaml binding? > > Cheers, > Andre > > P.S. Since we have seen this a lot lately: please wait with a new > version of your series for a few days, to allow other people to comment, > and to allow discussions to settle down. Not everyone can respond quickly. > > > 1 file changed, 108 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml > > new file mode 100644 > > index 000000000000..806da97ab708 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml > > @@ -0,0 +1,108 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pinctrl/allwinner,sun8i-b288-pinctrl.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Allwinner B288 Pin Controller > > + > > +maintainers: > > + - Chen-Yu Tsai <wens@csie.org> > > + - Jernej Skrabec <jernej.skrabec@gmail.com> > > + > > +properties: > > + compatible: > > + const: allwinner,sun8i-b288-pinctrl > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + description: > > + One interrupt per bank of external interrupt capable pins. > > + maxItems: 4 > > + > > + clocks: > > + items: > > + - description: Bus Clock > > + - description: High Frequency Oscillator > > + - description: Low Frequency Oscillator > > + > > + clock-names: > > + items: > > + - const: apb > > + - const: hosc > > + - const: losc > > + > > + gpio-controller: true > > + interrupt-controller: true > > + gpio-line-names: true > > + > > + "#gpio-cells": > > + const: 3 > > + > > + "#interrupt-cells": > > + const: 3 > > + > > +patternProperties: > > + "-pins$": > > + type: object > > + $ref: /schemas/pinctrl/pincfg-node.yaml# > > + additionalProperties: false > > + > > + properties: > > + pins: true > > + function: true > > + bias-pull-up: true > > + bias-pull-down: true > > + bias-disable: true > > + drive-strength: > > + enum: [10, 20, 30, 40] > > + > > + required: > > + - pins > > + - function > > + > > + "^vcc-p[bcdfg]-supply$": > > + description: > > + Power supplies for pin banks. > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + - clock-names > > + - gpio-controller > > + - "#gpio-cells" > > + - interrupt-controller > > + - "#interrupt-cells" > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/clock/sun8i-b288-ccu.h> > > + > > + pio: pinctrl@1c20800 { > > + compatible = "allwinner,sun8i-b288-pinctrl"; > > + reg = <0x01c20800 0x400>; > > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; > > + clock-names = "apb", "hosc", "losc"; > > + gpio-controller; > > + #gpio-cells = <3>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + > > + mmc0_pins: mmc0-pins { > > + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; > > + function = "sdc0"; > > + drive-strength = <30>; > > + bias-pull-up; > > + }; > > + }; > ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v1 04/11] pinctrl: sunxi: add Allwinner B288 pin controller driver [not found] <20260923201701.43391-1-pmazzini@gmail.com> 2026-09-23 20:16 ` [PATCH v1 03/11] dt-bindings: pinctrl: add Allwinner B288 pin controller Pablo Mazzini @ 2026-09-23 20:16 ` Pablo Mazzini 2026-09-24 9:17 ` Andre Przywara 1 sibling, 1 reply; 7+ messages in thread From: Pablo Mazzini @ 2026-09-23 20:16 UTC (permalink / raw) To: Chen-Yu Tsai, Jernej Skrabec, Linus Walleij, Samuel Holland Cc: Pablo Mazzini, linux-arm-kernel, linux-gpio, linux-kernel, linux-sunxi 78 pins across ports B, C, D, F and G. PH0 is BSP FPGA-only and omitted. Signed-off-by: Pablo Mazzini <pmazzini@gmail.com> --- drivers/pinctrl/sunxi/Kconfig | 10 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c | 623 +++++++++++++++++++++ 3 files changed, 634 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index dc62eba96348..a08186133090 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -56,6 +56,16 @@ config PINCTRL_SUN8I_A23_R default MACH_SUN8I select PINCTRL_SUNXI +config PINCTRL_SUN8I_B288 + bool "Support for the Allwinner B288 PIO" + default MACH_SUN8I + select PINCTRL_SUNXI + help + Say Y here to enable pin controller and GPIO support for the + Allwinner B288 (sun8iw10p1) SoC, as used in e-book readers such + as the PocketBook Verse. This covers ports B, C, D, F and G, + including the four banks of external interrupt capable pins. + config PINCTRL_SUN8I_H3 bool "Support for the Allwinner H3 PIO" default MACH_SUN8I diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 951b3f1e4b4f..5129c0f19f3e 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_SUN50I_A100) += pinctrl-sun50i-a100.o obj-$(CONFIG_PINCTRL_SUN50I_A100_R) += pinctrl-sun50i-a100-r.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o +obj-$(CONFIG_PINCTRL_SUN8I_B288) += pinctrl-sun8i-b288.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c new file mode 100644 index 000000000000..ffd7eef68d19 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c @@ -0,0 +1,623 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Allwinner B288 (sun8iw10p1) SoC pinctrl driver. + * + * Derived from Allwinner's BSP driver pinctrl-sun8iw10p1.c, which is: + * Copyright (C) 2014 Jackie Hwang <huangshr@allwinnertech.com> + * + * Based on pinctrl-sun8i-a23.c, which is: + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_b288_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), + SUNXI_FUNCTION(0x3, "jtag0"), + SUNXI_FUNCTION(0x5, "vdevice"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), + SUNXI_FUNCTION(0x3, "jtag0"), + SUNXI_FUNCTION(0x4, "spdif0"), + SUNXI_FUNCTION(0x5, "vdevice"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), + SUNXI_FUNCTION(0x3, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), + SUNXI_FUNCTION(0x3, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), + SUNXI_FUNCTION(0x3, "pwm0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), + SUNXI_FUNCTION(0x3, "pwm1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), + SUNXI_FUNCTION(0x3, "uart4"), + SUNXI_FUNCTION(0x4, "pwm2"), + SUNXI_FUNCTION(0x5, "wifi_uart0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), + SUNXI_FUNCTION(0x3, "uart4"), + SUNXI_FUNCTION(0x4, "pwm3"), + SUNXI_FUNCTION(0x5, "wifi_uart0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), + SUNXI_FUNCTION(0x4, "pwm4"), + SUNXI_FUNCTION(0x5, "uart3"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), + SUNXI_FUNCTION(0x4, "pwm5"), + SUNXI_FUNCTION(0x5, "uart3"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), + SUNXI_FUNCTION(0x3, "ac0"), + SUNXI_FUNCTION(0x4, "twi1"), + SUNXI_FUNCTION(0x5, "uart3"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), + SUNXI_FUNCTION(0x3, "ac0"), + SUNXI_FUNCTION(0x4, "twi1"), + SUNXI_FUNCTION(0x5, "uart3"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), + /*Hole*/ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x4, "spi0"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "spi0"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x4, "spi0"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x4, "spi0"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart1"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart1"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart5"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart5"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart5"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart5"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart1"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 17)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 18)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 19)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 20)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 21)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 22)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 23)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "spi2"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 24)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "spi2"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 25)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "spi2"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 26)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "spi2"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 27)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 28)), + + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "uart0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "uart0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), + + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm6"), + SUNXI_FUNCTION(0x3, "dmic0"), + SUNXI_FUNCTION(0x4, "spi1"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm7"), + SUNXI_FUNCTION(0x3, "dmic0"), + SUNXI_FUNCTION(0x4, "spi1"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi1"), + SUNXI_FUNCTION(0x3, "dmic0"), + SUNXI_FUNCTION(0x4, "spi1"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi1"), + SUNXI_FUNCTION(0x3, "dmic0"), + SUNXI_FUNCTION(0x4, "spi1"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi2"), + SUNXI_FUNCTION(0x3, "dmic0"), + SUNXI_FUNCTION(0x4, "spi1"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi2"), + SUNXI_FUNCTION(0x4, "ac0"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), + SUNXI_FUNCTION(0x3, "dsd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), + SUNXI_FUNCTION(0x3, "dsd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), + SUNXI_FUNCTION(0x3, "dsd0"), + SUNXI_FUNCTION(0x4, "bist_result0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), + SUNXI_FUNCTION(0x3, "dsd0"), + SUNXI_FUNCTION(0x4, "bist_result1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spdif0"), + SUNXI_FUNCTION(0x4, "pll_lock_dbg"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), + +}; + +static const struct sunxi_pinctrl_desc sun8i_b288_pinctrl_data = { + .pins = sun8i_b288_pins, + .npins = ARRAY_SIZE(sun8i_b288_pins), + .irq_banks = 4, +}; + +static int sun8i_b288_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun8i_b288_pinctrl_data); +} + +static const struct of_device_id sun8i_b288_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-b288-pinctrl", }, + {} +}; + +static struct platform_driver sun8i_b288_pinctrl_driver = { + .probe = sun8i_b288_pinctrl_probe, + .driver = { + .name = "sun8i-b288-pinctrl", + .of_match_table = sun8i_b288_pinctrl_match, + }, +}; +builtin_platform_driver(sun8i_b288_pinctrl_driver); -- 2.53.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v1 04/11] pinctrl: sunxi: add Allwinner B288 pin controller driver 2026-09-23 20:16 ` [PATCH v1 04/11] pinctrl: sunxi: add Allwinner B288 pin controller driver Pablo Mazzini @ 2026-09-24 9:17 ` Andre Przywara 2026-09-24 20:28 ` Pablo Mazzini 0 siblings, 1 reply; 7+ messages in thread From: Andre Przywara @ 2026-09-24 9:17 UTC (permalink / raw) To: Pablo Mazzini, Chen-Yu Tsai, Jernej Skrabec, Linus Walleij, Samuel Holland Cc: linux-arm-kernel, linux-gpio, linux-kernel, linux-sunxi Hi, many thanks for going through the task of creating this table - though I think you wouldn't need to do this anymore, since we now have another way of describing pins, which avoids this lenghty table in the driver: look at pinctrl-sun55i-a523.c for an example. This would allow the "driver" to be a mere high level description, and leave the mux values to the DT. That being said: it's good to have that info, for the lack of a manual. Can you by any chance try to make a table out of it and put it into our wiki (https://linux-sunxi.org/B288)? That would then be the replacement for the manual. Maybe write a small tool to convert this data struct into Wiki table format. Some general things inline ... On 9/23/26 22:16, Pablo Mazzini wrote: > 78 pins across ports B, C, D, F and G. PH0 is BSP FPGA-only and omitted. > > Signed-off-by: Pablo Mazzini <pmazzini@gmail.com> > --- > drivers/pinctrl/sunxi/Kconfig | 10 + > drivers/pinctrl/sunxi/Makefile | 1 + > drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c | 623 +++++++++++++++++++++ > 3 files changed, 634 insertions(+) > create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c > > diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig > index dc62eba96348..a08186133090 100644 > --- a/drivers/pinctrl/sunxi/Kconfig > +++ b/drivers/pinctrl/sunxi/Kconfig > @@ -56,6 +56,16 @@ config PINCTRL_SUN8I_A23_R > default MACH_SUN8I > select PINCTRL_SUNXI > > +config PINCTRL_SUN8I_B288 > + bool "Support for the Allwinner B288 PIO" > + default MACH_SUN8I > + select PINCTRL_SUNXI > + help > + Say Y here to enable pin controller and GPIO support for the > + Allwinner B288 (sun8iw10p1) SoC, as used in e-book readers such > + as the PocketBook Verse. This covers ports B, C, D, F and G, > + including the four banks of external interrupt capable pins. > + > config PINCTRL_SUN8I_H3 > bool "Support for the Allwinner H3 PIO" > default MACH_SUN8I > diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile > index 951b3f1e4b4f..5129c0f19f3e 100644 > --- a/drivers/pinctrl/sunxi/Makefile > +++ b/drivers/pinctrl/sunxi/Makefile > @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_SUN50I_A100) += pinctrl-sun50i-a100.o > obj-$(CONFIG_PINCTRL_SUN50I_A100_R) += pinctrl-sun50i-a100-r.o > obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o > obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o > +obj-$(CONFIG_PINCTRL_SUN8I_B288) += pinctrl-sun8i-b288.o > obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o > obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o > obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c > new file mode 100644 > index 000000000000..ffd7eef68d19 > --- /dev/null > +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c > @@ -0,0 +1,623 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Allwinner B288 (sun8iw10p1) SoC pinctrl driver. > + * > + * Derived from Allwinner's BSP driver pinctrl-sun8iw10p1.c, which is: > + * Copyright (C) 2014 Jackie Hwang <huangshr@allwinnertech.com> > + * > + * Based on pinctrl-sun8i-a23.c, which is: > + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> > + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> > + */ > + > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/of.h> > +#include <linux/pinctrl/pinctrl.h> > + > +#include "pinctrl-sunxi.h" > + > +static const struct sunxi_desc_pin sun8i_b288_pins[] = { > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), > + SUNXI_FUNCTION(0x3, "jtag0"), > + SUNXI_FUNCTION(0x5, "vdevice"), What's vdevice? I don't think we used to describe those weird functions. > + SUNXI_FUNCTION(0x7, "io_disabled"), I know Allwinner does this, but we do not describe the HighZ mux, it's all 1's anyway, and the same for all pins. Those comments are probably irrelevant if you go with the new pinctrl driver style. Most of the settings there should be straightforward to figure out, just remember to add an IRQ map, to account for the missing interrupts on PortC. Cheers, Andre > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), > + SUNXI_FUNCTION(0x3, "jtag0"), > + SUNXI_FUNCTION(0x4, "spdif0"), > + SUNXI_FUNCTION(0x5, "vdevice"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), > + SUNXI_FUNCTION(0x3, "jtag0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), > + SUNXI_FUNCTION(0x3, "jtag0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart0"), > + SUNXI_FUNCTION(0x3, "pwm0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart0"), > + SUNXI_FUNCTION(0x3, "pwm1"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "twi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "twi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "spi1"), > + SUNXI_FUNCTION(0x3, "uart4"), > + SUNXI_FUNCTION(0x4, "pwm2"), > + SUNXI_FUNCTION(0x5, "wifi_uart0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "spi1"), > + SUNXI_FUNCTION(0x3, "uart4"), > + SUNXI_FUNCTION(0x4, "pwm3"), > + SUNXI_FUNCTION(0x5, "wifi_uart0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s1"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s1"), > + SUNXI_FUNCTION(0x4, "pwm4"), > + SUNXI_FUNCTION(0x5, "uart3"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s1"), > + SUNXI_FUNCTION(0x4, "pwm5"), > + SUNXI_FUNCTION(0x5, "uart3"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s1"), > + SUNXI_FUNCTION(0x3, "ac0"), > + SUNXI_FUNCTION(0x4, "twi1"), > + SUNXI_FUNCTION(0x5, "uart3"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s1"), > + SUNXI_FUNCTION(0x3, "ac0"), > + SUNXI_FUNCTION(0x4, "twi1"), > + SUNXI_FUNCTION(0x5, "uart3"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), > + /*Hole*/ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x4, "spi0"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x4, "spi0"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x4, "spi0"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x4, "spi0"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x4, "uart1"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x4, "uart1"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x4, "uart1"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x4, "uart1"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x4, "uart1"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x4, "uart1"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x4, "uart1"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x4, "uart1"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), > + SUNXI_FUNCTION(0x3, "sdc2"), > + SUNXI_FUNCTION(0x5, "sdc3"), > + SUNXI_FUNCTION(0x7, "io_disabled")), > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "uart1"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "uart1"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "uart5"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "uart5"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "uart5"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "uart5"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "uart1"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "uart1"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 17)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 18)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 19)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 20)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 21)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 22)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x4, "csi0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 23)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "spi2"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 24)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "spi2"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 25)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "spi2"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 26)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd0"), > + SUNXI_FUNCTION(0x3, "spi2"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 27)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "pwm0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 28)), > + > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "sdc0"), > + SUNXI_FUNCTION(0x4, "jtag0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "sdc0"), > + SUNXI_FUNCTION(0x4, "jtag0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "sdc0"), > + SUNXI_FUNCTION(0x4, "uart0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "sdc0"), > + SUNXI_FUNCTION(0x4, "jtag0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "sdc0"), > + SUNXI_FUNCTION(0x4, "uart0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "sdc0"), > + SUNXI_FUNCTION(0x4, "jtag0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), > + > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "pwm6"), > + SUNXI_FUNCTION(0x3, "dmic0"), > + SUNXI_FUNCTION(0x4, "spi1"), > + SUNXI_FUNCTION(0x5, "sdc1"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "pwm7"), > + SUNXI_FUNCTION(0x3, "dmic0"), > + SUNXI_FUNCTION(0x4, "spi1"), > + SUNXI_FUNCTION(0x5, "sdc1"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "twi1"), > + SUNXI_FUNCTION(0x3, "dmic0"), > + SUNXI_FUNCTION(0x4, "spi1"), > + SUNXI_FUNCTION(0x5, "sdc1"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "twi1"), > + SUNXI_FUNCTION(0x3, "dmic0"), > + SUNXI_FUNCTION(0x4, "spi1"), > + SUNXI_FUNCTION(0x5, "sdc1"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "twi2"), > + SUNXI_FUNCTION(0x3, "dmic0"), > + SUNXI_FUNCTION(0x4, "spi1"), > + SUNXI_FUNCTION(0x5, "sdc1"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "twi2"), > + SUNXI_FUNCTION(0x4, "ac0"), > + SUNXI_FUNCTION(0x5, "sdc1"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s0"), > + SUNXI_FUNCTION(0x3, "dsd0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s0"), > + SUNXI_FUNCTION(0x3, "dsd0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s0"), > + SUNXI_FUNCTION(0x3, "dsd0"), > + SUNXI_FUNCTION(0x4, "bist_result0"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s0"), > + SUNXI_FUNCTION(0x3, "dsd0"), > + SUNXI_FUNCTION(0x4, "bist_result1"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "spdif0"), > + SUNXI_FUNCTION(0x4, "pll_lock_dbg"), > + SUNXI_FUNCTION(0x7, "io_disabled"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), > + > +}; > + > +static const struct sunxi_pinctrl_desc sun8i_b288_pinctrl_data = { > + .pins = sun8i_b288_pins, > + .npins = ARRAY_SIZE(sun8i_b288_pins), > + .irq_banks = 4, > +}; > + > +static int sun8i_b288_pinctrl_probe(struct platform_device *pdev) > +{ > + return sunxi_pinctrl_init(pdev, > + &sun8i_b288_pinctrl_data); > +} > + > +static const struct of_device_id sun8i_b288_pinctrl_match[] = { > + { .compatible = "allwinner,sun8i-b288-pinctrl", }, > + {} > +}; > + > +static struct platform_driver sun8i_b288_pinctrl_driver = { > + .probe = sun8i_b288_pinctrl_probe, > + .driver = { > + .name = "sun8i-b288-pinctrl", > + .of_match_table = sun8i_b288_pinctrl_match, > + }, > +}; > +builtin_platform_driver(sun8i_b288_pinctrl_driver); ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 04/11] pinctrl: sunxi: add Allwinner B288 pin controller driver 2026-09-24 9:17 ` Andre Przywara @ 2026-09-24 20:28 ` Pablo Mazzini 2026-09-25 8:21 ` Andre Przywara 0 siblings, 1 reply; 7+ messages in thread From: Pablo Mazzini @ 2026-09-24 20:28 UTC (permalink / raw) To: Andre Przywara Cc: Chen-Yu Tsai, Jernej Skrabec, Linus Walleij, Samuel Holland, linux-arm-kernel, linux-gpio, linux-kernel, linux-sunxi Hi Andre, > look at pinctrl-sun55i-a523.c for an example Thanks for the pointer - much nicer. Converted for v2. > Can you put it into our wiki The page already has the table and it matches the BSP exactly. Thanks, Pablo On Thu, Sep 24, 2026 at 10:17 AM Andre Przywara <andre.przywara@arm.com> wrote: > > Hi, > > many thanks for going through the task of creating this table - though I > think you wouldn't need to do this anymore, since we now have another > way of describing pins, which avoids this lenghty table in the driver: > look at pinctrl-sun55i-a523.c for an example. > > This would allow the "driver" to be a mere high level description, and > leave the mux values to the DT. > > That being said: it's good to have that info, for the lack of a manual. > Can you by any chance try to make a table out of it and put it into our > wiki (https://linux-sunxi.org/B288)? That would then be the replacement > for the manual. Maybe write a small tool to convert this data struct > into Wiki table format. > > Some general things inline ... > > On 9/23/26 22:16, Pablo Mazzini wrote: > > 78 pins across ports B, C, D, F and G. PH0 is BSP FPGA-only and omitted. > > > > Signed-off-by: Pablo Mazzini <pmazzini@gmail.com> > > --- > > drivers/pinctrl/sunxi/Kconfig | 10 + > > drivers/pinctrl/sunxi/Makefile | 1 + > > drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c | 623 +++++++++++++++++++++ > > 3 files changed, 634 insertions(+) > > create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c > > > > diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig > > index dc62eba96348..a08186133090 100644 > > --- a/drivers/pinctrl/sunxi/Kconfig > > +++ b/drivers/pinctrl/sunxi/Kconfig > > @@ -56,6 +56,16 @@ config PINCTRL_SUN8I_A23_R > > default MACH_SUN8I > > select PINCTRL_SUNXI > > > > +config PINCTRL_SUN8I_B288 > > + bool "Support for the Allwinner B288 PIO" > > + default MACH_SUN8I > > + select PINCTRL_SUNXI > > + help > > + Say Y here to enable pin controller and GPIO support for the > > + Allwinner B288 (sun8iw10p1) SoC, as used in e-book readers such > > + as the PocketBook Verse. This covers ports B, C, D, F and G, > > + including the four banks of external interrupt capable pins. > > + > > config PINCTRL_SUN8I_H3 > > bool "Support for the Allwinner H3 PIO" > > default MACH_SUN8I > > diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile > > index 951b3f1e4b4f..5129c0f19f3e 100644 > > --- a/drivers/pinctrl/sunxi/Makefile > > +++ b/drivers/pinctrl/sunxi/Makefile > > @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_SUN50I_A100) += pinctrl-sun50i-a100.o > > obj-$(CONFIG_PINCTRL_SUN50I_A100_R) += pinctrl-sun50i-a100-r.o > > obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o > > obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o > > +obj-$(CONFIG_PINCTRL_SUN8I_B288) += pinctrl-sun8i-b288.o > > obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o > > obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o > > obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c > > new file mode 100644 > > index 000000000000..ffd7eef68d19 > > --- /dev/null > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c > > @@ -0,0 +1,623 @@ > > +// SPDX-License-Identifier: GPL-2.0-or-later > > +/* > > + * Allwinner B288 (sun8iw10p1) SoC pinctrl driver. > > + * > > + * Derived from Allwinner's BSP driver pinctrl-sun8iw10p1.c, which is: > > + * Copyright (C) 2014 Jackie Hwang <huangshr@allwinnertech.com> > > + * > > + * Based on pinctrl-sun8i-a23.c, which is: > > + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> > > + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> > > + */ > > + > > +#include <linux/module.h> > > +#include <linux/platform_device.h> > > +#include <linux/of.h> > > +#include <linux/pinctrl/pinctrl.h> > > + > > +#include "pinctrl-sunxi.h" > > + > > +static const struct sunxi_desc_pin sun8i_b288_pins[] = { > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "uart2"), > > + SUNXI_FUNCTION(0x3, "jtag0"), > > + SUNXI_FUNCTION(0x5, "vdevice"), > > What's vdevice? I don't think we used to describe those weird functions. > > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > I know Allwinner does this, but we do not describe the HighZ mux, it's > all 1's anyway, and the same for all pins. > > Those comments are probably irrelevant if you go with the new pinctrl > driver style. Most of the settings there should be straightforward to > figure out, just remember to add an IRQ map, to account for the missing > interrupts on PortC. > > Cheers, > Andre > > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "uart2"), > > + SUNXI_FUNCTION(0x3, "jtag0"), > > + SUNXI_FUNCTION(0x4, "spdif0"), > > + SUNXI_FUNCTION(0x5, "vdevice"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "uart2"), > > + SUNXI_FUNCTION(0x3, "jtag0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "uart2"), > > + SUNXI_FUNCTION(0x3, "jtag0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "uart0"), > > + SUNXI_FUNCTION(0x3, "pwm0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "uart0"), > > + SUNXI_FUNCTION(0x3, "pwm1"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "twi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "twi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "spi1"), > > + SUNXI_FUNCTION(0x3, "uart4"), > > + SUNXI_FUNCTION(0x4, "pwm2"), > > + SUNXI_FUNCTION(0x5, "wifi_uart0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "spi1"), > > + SUNXI_FUNCTION(0x3, "uart4"), > > + SUNXI_FUNCTION(0x4, "pwm3"), > > + SUNXI_FUNCTION(0x5, "wifi_uart0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "i2s1"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "i2s1"), > > + SUNXI_FUNCTION(0x4, "pwm4"), > > + SUNXI_FUNCTION(0x5, "uart3"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "i2s1"), > > + SUNXI_FUNCTION(0x4, "pwm5"), > > + SUNXI_FUNCTION(0x5, "uart3"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "i2s1"), > > + SUNXI_FUNCTION(0x3, "ac0"), > > + SUNXI_FUNCTION(0x4, "twi1"), > > + SUNXI_FUNCTION(0x5, "uart3"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "i2s1"), > > + SUNXI_FUNCTION(0x3, "ac0"), > > + SUNXI_FUNCTION(0x4, "twi1"), > > + SUNXI_FUNCTION(0x5, "uart3"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), > > + /*Hole*/ > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x4, "spi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x4, "spi0"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x4, "spi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x4, "spi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x4, "uart1"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x4, "uart1"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x4, "uart1"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x4, "uart1"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x4, "uart1"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x4, "uart1"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x4, "uart1"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x4, "uart1"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "nand0"), > > + SUNXI_FUNCTION(0x3, "sdc2"), > > + SUNXI_FUNCTION(0x5, "sdc3"), > > + SUNXI_FUNCTION(0x7, "io_disabled")), > > + /* Hole */ > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "uart1"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "uart1"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "uart5"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "uart5"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "uart5"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "uart5"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "uart1"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "uart1"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 17)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 18)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 19)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 20)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 21)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 22)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x4, "csi0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 23)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "spi2"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 24)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "spi2"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 25)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "spi2"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 26)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "lcd0"), > > + SUNXI_FUNCTION(0x3, "spi2"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 27)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "pwm0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 28)), > > + > > + /* Hole */ > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "sdc0"), > > + SUNXI_FUNCTION(0x4, "jtag0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "sdc0"), > > + SUNXI_FUNCTION(0x4, "jtag0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "sdc0"), > > + SUNXI_FUNCTION(0x4, "uart0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "sdc0"), > > + SUNXI_FUNCTION(0x4, "jtag0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "sdc0"), > > + SUNXI_FUNCTION(0x4, "uart0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "sdc0"), > > + SUNXI_FUNCTION(0x4, "jtag0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), > > + > > + /* Hole */ > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "pwm6"), > > + SUNXI_FUNCTION(0x3, "dmic0"), > > + SUNXI_FUNCTION(0x4, "spi1"), > > + SUNXI_FUNCTION(0x5, "sdc1"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "pwm7"), > > + SUNXI_FUNCTION(0x3, "dmic0"), > > + SUNXI_FUNCTION(0x4, "spi1"), > > + SUNXI_FUNCTION(0x5, "sdc1"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "twi1"), > > + SUNXI_FUNCTION(0x3, "dmic0"), > > + SUNXI_FUNCTION(0x4, "spi1"), > > + SUNXI_FUNCTION(0x5, "sdc1"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "twi1"), > > + SUNXI_FUNCTION(0x3, "dmic0"), > > + SUNXI_FUNCTION(0x4, "spi1"), > > + SUNXI_FUNCTION(0x5, "sdc1"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "twi2"), > > + SUNXI_FUNCTION(0x3, "dmic0"), > > + SUNXI_FUNCTION(0x4, "spi1"), > > + SUNXI_FUNCTION(0x5, "sdc1"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "twi2"), > > + SUNXI_FUNCTION(0x4, "ac0"), > > + SUNXI_FUNCTION(0x5, "sdc1"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "i2s0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "i2s0"), > > + SUNXI_FUNCTION(0x3, "dsd0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "i2s0"), > > + SUNXI_FUNCTION(0x3, "dsd0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "i2s0"), > > + SUNXI_FUNCTION(0x3, "dsd0"), > > + SUNXI_FUNCTION(0x4, "bist_result0"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "i2s0"), > > + SUNXI_FUNCTION(0x3, "dsd0"), > > + SUNXI_FUNCTION(0x4, "bist_result1"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), > > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), > > + SUNXI_FUNCTION(0x0, "gpio_in"), > > + SUNXI_FUNCTION(0x1, "gpio_out"), > > + SUNXI_FUNCTION(0x2, "spdif0"), > > + SUNXI_FUNCTION(0x4, "pll_lock_dbg"), > > + SUNXI_FUNCTION(0x7, "io_disabled"), > > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), > > + > > +}; > > + > > +static const struct sunxi_pinctrl_desc sun8i_b288_pinctrl_data = { > > + .pins = sun8i_b288_pins, > > + .npins = ARRAY_SIZE(sun8i_b288_pins), > > + .irq_banks = 4, > > +}; > > + > > +static int sun8i_b288_pinctrl_probe(struct platform_device *pdev) > > +{ > > + return sunxi_pinctrl_init(pdev, > > + &sun8i_b288_pinctrl_data); > > +} > > + > > +static const struct of_device_id sun8i_b288_pinctrl_match[] = { > > + { .compatible = "allwinner,sun8i-b288-pinctrl", }, > > + {} > > +}; > > + > > +static struct platform_driver sun8i_b288_pinctrl_driver = { > > + .probe = sun8i_b288_pinctrl_probe, > > + .driver = { > > + .name = "sun8i-b288-pinctrl", > > + .of_match_table = sun8i_b288_pinctrl_match, > > + }, > > +}; > > +builtin_platform_driver(sun8i_b288_pinctrl_driver); > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 04/11] pinctrl: sunxi: add Allwinner B288 pin controller driver 2026-09-24 20:28 ` Pablo Mazzini @ 2026-09-25 8:21 ` Andre Przywara 0 siblings, 0 replies; 7+ messages in thread From: Andre Przywara @ 2026-09-25 8:21 UTC (permalink / raw) To: Pablo Mazzini Cc: Chen-Yu Tsai, Jernej Skrabec, Linus Walleij, Samuel Holland, linux-arm-kernel, linux-gpio, linux-kernel, linux-sunxi Hi Pablo, On 9/24/26 22:28, Pablo Mazzini wrote: > Hi Andre, > >> look at pinctrl-sun55i-a523.c for an example > > Thanks for the pointer - much nicer. Converted for v2. > >> Can you put it into our wiki > > The page already has the table and it matches the BSP exactly. Lol, it was even me putting it there, but I hid it under that Collapse feature, so I didn't spot it yesterday. All good then, and thanks for the confirmation about them matching! Cheers, Andre > > Thanks, > Pablo > > On Thu, Sep 24, 2026 at 10:17 AM Andre Przywara <andre.przywara@arm.com> wrote: >> >> Hi, >> >> many thanks for going through the task of creating this table - though I >> think you wouldn't need to do this anymore, since we now have another >> way of describing pins, which avoids this lenghty table in the driver: >> look at pinctrl-sun55i-a523.c for an example. >> >> This would allow the "driver" to be a mere high level description, and >> leave the mux values to the DT. >> >> That being said: it's good to have that info, for the lack of a manual. >> Can you by any chance try to make a table out of it and put it into our >> wiki (https://linux-sunxi.org/B288)? That would then be the replacement >> for the manual. Maybe write a small tool to convert this data struct >> into Wiki table format. >> >> Some general things inline ... >> >> On 9/23/26 22:16, Pablo Mazzini wrote: >>> 78 pins across ports B, C, D, F and G. PH0 is BSP FPGA-only and omitted. >>> >>> Signed-off-by: Pablo Mazzini <pmazzini@gmail.com> >>> --- >>> drivers/pinctrl/sunxi/Kconfig | 10 + >>> drivers/pinctrl/sunxi/Makefile | 1 + >>> drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c | 623 +++++++++++++++++++++ >>> 3 files changed, 634 insertions(+) >>> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c >>> >>> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig >>> index dc62eba96348..a08186133090 100644 >>> --- a/drivers/pinctrl/sunxi/Kconfig >>> +++ b/drivers/pinctrl/sunxi/Kconfig >>> @@ -56,6 +56,16 @@ config PINCTRL_SUN8I_A23_R >>> default MACH_SUN8I >>> select PINCTRL_SUNXI >>> >>> +config PINCTRL_SUN8I_B288 >>> + bool "Support for the Allwinner B288 PIO" >>> + default MACH_SUN8I >>> + select PINCTRL_SUNXI >>> + help >>> + Say Y here to enable pin controller and GPIO support for the >>> + Allwinner B288 (sun8iw10p1) SoC, as used in e-book readers such >>> + as the PocketBook Verse. This covers ports B, C, D, F and G, >>> + including the four banks of external interrupt capable pins. >>> + >>> config PINCTRL_SUN8I_H3 >>> bool "Support for the Allwinner H3 PIO" >>> default MACH_SUN8I >>> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile >>> index 951b3f1e4b4f..5129c0f19f3e 100644 >>> --- a/drivers/pinctrl/sunxi/Makefile >>> +++ b/drivers/pinctrl/sunxi/Makefile >>> @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_SUN50I_A100) += pinctrl-sun50i-a100.o >>> obj-$(CONFIG_PINCTRL_SUN50I_A100_R) += pinctrl-sun50i-a100-r.o >>> obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o >>> obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o >>> +obj-$(CONFIG_PINCTRL_SUN8I_B288) += pinctrl-sun8i-b288.o >>> obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o >>> obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o >>> obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o >>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c >>> new file mode 100644 >>> index 000000000000..ffd7eef68d19 >>> --- /dev/null >>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c >>> @@ -0,0 +1,623 @@ >>> +// SPDX-License-Identifier: GPL-2.0-or-later >>> +/* >>> + * Allwinner B288 (sun8iw10p1) SoC pinctrl driver. >>> + * >>> + * Derived from Allwinner's BSP driver pinctrl-sun8iw10p1.c, which is: >>> + * Copyright (C) 2014 Jackie Hwang <huangshr@allwinnertech.com> >>> + * >>> + * Based on pinctrl-sun8i-a23.c, which is: >>> + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> >>> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> >>> + */ >>> + >>> +#include <linux/module.h> >>> +#include <linux/platform_device.h> >>> +#include <linux/of.h> >>> +#include <linux/pinctrl/pinctrl.h> >>> + >>> +#include "pinctrl-sunxi.h" >>> + >>> +static const struct sunxi_desc_pin sun8i_b288_pins[] = { >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "uart2"), >>> + SUNXI_FUNCTION(0x3, "jtag0"), >>> + SUNXI_FUNCTION(0x5, "vdevice"), >> >> What's vdevice? I don't think we used to describe those weird functions. >> >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >> >> I know Allwinner does this, but we do not describe the HighZ mux, it's >> all 1's anyway, and the same for all pins. >> >> Those comments are probably irrelevant if you go with the new pinctrl >> driver style. Most of the settings there should be straightforward to >> figure out, just remember to add an IRQ map, to account for the missing >> interrupts on PortC. >> >> Cheers, >> Andre >> >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "uart2"), >>> + SUNXI_FUNCTION(0x3, "jtag0"), >>> + SUNXI_FUNCTION(0x4, "spdif0"), >>> + SUNXI_FUNCTION(0x5, "vdevice"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "uart2"), >>> + SUNXI_FUNCTION(0x3, "jtag0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "uart2"), >>> + SUNXI_FUNCTION(0x3, "jtag0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "uart0"), >>> + SUNXI_FUNCTION(0x3, "pwm0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "uart0"), >>> + SUNXI_FUNCTION(0x3, "pwm1"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "twi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "twi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "spi1"), >>> + SUNXI_FUNCTION(0x3, "uart4"), >>> + SUNXI_FUNCTION(0x4, "pwm2"), >>> + SUNXI_FUNCTION(0x5, "wifi_uart0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "spi1"), >>> + SUNXI_FUNCTION(0x3, "uart4"), >>> + SUNXI_FUNCTION(0x4, "pwm3"), >>> + SUNXI_FUNCTION(0x5, "wifi_uart0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "i2s1"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "i2s1"), >>> + SUNXI_FUNCTION(0x4, "pwm4"), >>> + SUNXI_FUNCTION(0x5, "uart3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "i2s1"), >>> + SUNXI_FUNCTION(0x4, "pwm5"), >>> + SUNXI_FUNCTION(0x5, "uart3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "i2s1"), >>> + SUNXI_FUNCTION(0x3, "ac0"), >>> + SUNXI_FUNCTION(0x4, "twi1"), >>> + SUNXI_FUNCTION(0x5, "uart3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "i2s1"), >>> + SUNXI_FUNCTION(0x3, "ac0"), >>> + SUNXI_FUNCTION(0x4, "twi1"), >>> + SUNXI_FUNCTION(0x5, "uart3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), >>> + /*Hole*/ >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x4, "spi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x4, "spi0"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x4, "spi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x4, "spi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x4, "uart1"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x4, "uart1"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x4, "uart1"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x4, "uart1"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x4, "uart1"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x4, "uart1"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x4, "uart1"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x4, "uart1"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "nand0"), >>> + SUNXI_FUNCTION(0x3, "sdc2"), >>> + SUNXI_FUNCTION(0x5, "sdc3"), >>> + SUNXI_FUNCTION(0x7, "io_disabled")), >>> + /* Hole */ >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "uart1"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "uart1"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "uart5"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "uart5"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "uart5"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "uart5"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "uart1"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "uart1"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 17)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 18)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 19)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 20)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 21)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 22)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x4, "csi0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 23)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "spi2"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 24)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "spi2"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 25)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "spi2"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 26)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "lcd0"), >>> + SUNXI_FUNCTION(0x3, "spi2"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 27)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "pwm0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 28)), >>> + >>> + /* Hole */ >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "sdc0"), >>> + SUNXI_FUNCTION(0x4, "jtag0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "sdc0"), >>> + SUNXI_FUNCTION(0x4, "jtag0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "sdc0"), >>> + SUNXI_FUNCTION(0x4, "uart0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "sdc0"), >>> + SUNXI_FUNCTION(0x4, "jtag0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "sdc0"), >>> + SUNXI_FUNCTION(0x4, "uart0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "sdc0"), >>> + SUNXI_FUNCTION(0x4, "jtag0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), >>> + >>> + /* Hole */ >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "pwm6"), >>> + SUNXI_FUNCTION(0x3, "dmic0"), >>> + SUNXI_FUNCTION(0x4, "spi1"), >>> + SUNXI_FUNCTION(0x5, "sdc1"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "pwm7"), >>> + SUNXI_FUNCTION(0x3, "dmic0"), >>> + SUNXI_FUNCTION(0x4, "spi1"), >>> + SUNXI_FUNCTION(0x5, "sdc1"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "twi1"), >>> + SUNXI_FUNCTION(0x3, "dmic0"), >>> + SUNXI_FUNCTION(0x4, "spi1"), >>> + SUNXI_FUNCTION(0x5, "sdc1"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "twi1"), >>> + SUNXI_FUNCTION(0x3, "dmic0"), >>> + SUNXI_FUNCTION(0x4, "spi1"), >>> + SUNXI_FUNCTION(0x5, "sdc1"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "twi2"), >>> + SUNXI_FUNCTION(0x3, "dmic0"), >>> + SUNXI_FUNCTION(0x4, "spi1"), >>> + SUNXI_FUNCTION(0x5, "sdc1"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "twi2"), >>> + SUNXI_FUNCTION(0x4, "ac0"), >>> + SUNXI_FUNCTION(0x5, "sdc1"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "i2s0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "i2s0"), >>> + SUNXI_FUNCTION(0x3, "dsd0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "i2s0"), >>> + SUNXI_FUNCTION(0x3, "dsd0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "i2s0"), >>> + SUNXI_FUNCTION(0x3, "dsd0"), >>> + SUNXI_FUNCTION(0x4, "bist_result0"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "i2s0"), >>> + SUNXI_FUNCTION(0x3, "dsd0"), >>> + SUNXI_FUNCTION(0x4, "bist_result1"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), >>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), >>> + SUNXI_FUNCTION(0x0, "gpio_in"), >>> + SUNXI_FUNCTION(0x1, "gpio_out"), >>> + SUNXI_FUNCTION(0x2, "spdif0"), >>> + SUNXI_FUNCTION(0x4, "pll_lock_dbg"), >>> + SUNXI_FUNCTION(0x7, "io_disabled"), >>> + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), >>> + >>> +}; >>> + >>> +static const struct sunxi_pinctrl_desc sun8i_b288_pinctrl_data = { >>> + .pins = sun8i_b288_pins, >>> + .npins = ARRAY_SIZE(sun8i_b288_pins), >>> + .irq_banks = 4, >>> +}; >>> + >>> +static int sun8i_b288_pinctrl_probe(struct platform_device *pdev) >>> +{ >>> + return sunxi_pinctrl_init(pdev, >>> + &sun8i_b288_pinctrl_data); >>> +} >>> + >>> +static const struct of_device_id sun8i_b288_pinctrl_match[] = { >>> + { .compatible = "allwinner,sun8i-b288-pinctrl", }, >>> + {} >>> +}; >>> + >>> +static struct platform_driver sun8i_b288_pinctrl_driver = { >>> + .probe = sun8i_b288_pinctrl_probe, >>> + .driver = { >>> + .name = "sun8i-b288-pinctrl", >>> + .of_match_table = sun8i_b288_pinctrl_match, >>> + }, >>> +}; >>> +builtin_platform_driver(sun8i_b288_pinctrl_driver); >> ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-09-25 8:22 UTC | newest]
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[not found] <20260923201701.43391-1-pmazzini@gmail.com>
2026-09-23 20:16 ` [PATCH v1 03/11] dt-bindings: pinctrl: add Allwinner B288 pin controller Pablo Mazzini
2026-09-24 9:07 ` Andre Przywara
2026-09-24 20:16 ` Pablo Mazzini
2026-09-23 20:16 ` [PATCH v1 04/11] pinctrl: sunxi: add Allwinner B288 pin controller driver Pablo Mazzini
2026-09-24 9:17 ` Andre Przywara
2026-09-24 20:28 ` Pablo Mazzini
2026-09-25 8:21 ` Andre Przywara
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