Re: [PATCH v4 2/2] pinctrl: upboard: add device id INTC1055 based UP boards support

[Thomas Richard <thomas.richard@bootlin.com>]

On 7/8/26 11:21 AM, Andy Shevchenko wrote:
> On Wed, Jul 8, 2026 at 10:49 AM Thomas Richard
> <thomas.richard@bootlin.com> wrote:
>> On 7/7/26 5:55 PM, GaryWang wrote:
>>> On Tue, Jul 7, 2026 at 7:50 PM Thomas Richard
>>> <thomas.richard@bootlin.com> wrote:
>>>> On 7/6/26 12:36 PM, Gary Wang wrote:
> 
> ...
> 
>>>> I tested the IOs:
>>>> - pwm0 does not work.
>>> you have to use our pwm kernel module for pwm test, I'll provide later.
>>
>> Ack
> 
> Can you, folks, elaborate why this is a requirement and what exactly
> is not working?
> 
>>>> - uart1 partially works: TX is okay, but loopback doesn't work. Signal
>>>> is bad when I add a loopback. Looks like pinctrl misconfig on SoC side.
>>> uart1 tested ok on our side, if you loop TX/RX do not forget to turn off
>>> hardware flow control. and we have executed cmd as below to make sure
>>> direction is set all right.
>>> echo "uart1_grp uart1" >
>>> /sys/kernel/debug/pinctrl/upboard-pinctrl/pinmux-select
>>
>> I did some tests with/without flow control using linux-serial-test tool.
> 
> I'm sorry it's not so clear to me, does it mean the serial interface
> is (still) not properly working or you have done that pinmux
> configuration and everything becomes fine (as Tested-by tag suggests)?
> 
> ...
> 
>>>> - for SPI, MOSI and CLK are okay, but not CS.
>>> Do you have enabled spi in BIOS HAT configuration?
>>> CS0 should be ok, it's SOC defined, CS1 is optional, users can activate low by
>>> himself before read/write, actually all gpio can be manually used as CS pin.
>>
>> I applied an ACPI overlay. I'll test it again.
> 
> I suppose this part is not as critical and I just wonder what the test
> results are.
> 
> ...
> 
>> Anyway these are not related to this patch series.
>> Thanks for the clarification.
>>
>> Tested-by: Thomas Richard <thomas.richard@bootlin.com>
> 
> So, after all, are they all good to go?

Yes,

I tested all functions and it is okay.

It was my fault, my test script did not select pingroup and function
correctly, so FPGA pins were misconfigured.

You can pick my TB tag.

Best Regards,
Thomas