[PATCH v4] gpio: mvebu: fix Armada XP per-CPU mask register save/restore

[PATCH v4] gpio: mvebu: fix Armada XP per-CPU mask register save/restore

[Rosen Penev]

The Armada XP variant keeps the per-CPU edge/level mask registers in a
second I/O window (percpu_regs) rather than in the main GPIO window.
The suspend and resume paths however read and wrote them through
mvchip->regs with the per-CPU offsets, which hits the global
GPIO_EDGE_MASK / GPIO_LEVEL_MASK registers instead. Per-CPU mask state
was therefore lost across suspend/resume, so a level line could end up
unmasked behind genirq's back and trigger an interrupt storm once
interrupts are re-enabled.

Use mvchip->percpu_regs for the Armada XP per-CPU mask registers in
both the suspend save and the resume restore paths, matching the
mask/unmask handlers and the probe-time masking.

Fixes: b5b7b487431b ("gpio: mvebu: add suspend/resume support")
Cc: stable@vger.kernel.org
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
 v4: rebase again
 v3: rebase again
 v2: rebase
 drivers/gpio/gpio-mvebu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index c57758019e92..03e977c2a629 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -1028,10 +1028,10 @@ static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
 		break;
 	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 		for (i = 0; i < 4; i++) {
-			regmap_read(mvchip->regs,
+			regmap_read(mvchip->percpu_regs,
 				    GPIO_EDGE_MASK_ARMADAXP_OFF(i),
 				    &mvchip->edge_mask_regs[i]);
-			regmap_read(mvchip->regs,
+			regmap_read(mvchip->percpu_regs,
 				    GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
 				    &mvchip->level_mask_regs[i]);
 		}
@@ -1080,10 +1080,10 @@ static int mvebu_gpio_resume(struct platform_device *pdev)
 		break;
 	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 		for (i = 0; i < 4; i++) {
-			regmap_write(mvchip->regs,
+			regmap_write(mvchip->percpu_regs,
 				     GPIO_EDGE_MASK_ARMADAXP_OFF(i),
 				     mvchip->edge_mask_regs[i]);
-			regmap_write(mvchip->regs,
+			regmap_write(mvchip->percpu_regs,
 				     GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
 				     mvchip->level_mask_regs[i]);
 		}
-- 
2.56.0

Re: [PATCH v4] gpio: mvebu: fix Armada XP per-CPU mask register save/restore

[Bartosz Golaszewski]

On Mon, 19 Oct 2026 01:01:17 +0200, Rosen Penev <rosenp@gmail.com> said:
> The Armada XP variant keeps the per-CPU edge/level mask registers in a
> second I/O window (percpu_regs) rather than in the main GPIO window.
> The suspend and resume paths however read and wrote them through
> mvchip->regs with the per-CPU offsets, which hits the global
> GPIO_EDGE_MASK / GPIO_LEVEL_MASK registers instead. Per-CPU mask state
> was therefore lost across suspend/resume, so a level line could end up
> unmasked behind genirq's back and trigger an interrupt storm once
> interrupts are re-enabled.
>
> Use mvchip->percpu_regs for the Armada XP per-CPU mask registers in
> both the suspend save and the resume restore paths, matching the
> mask/unmask handlers and the probe-time masking.
>
> Fixes: b5b7b487431b ("gpio: mvebu: add suspend/resume support")
> Cc: stable@vger.kernel.org
> Signed-off-by: Rosen Penev <rosenp@gmail.com>
> ---
>  v4: rebase again
>  v3: rebase again
>  v2: rebase

Are you rebasing it on top of the gpio/for-next branch of the GPIO git tree
as indicated in MAINTAINERS? Because this still fails to apply. :(

Bart

Re: [PATCH v4] gpio: mvebu: fix Armada XP per-CPU mask register save/restore

[Rosen Penev]

On Mon Oct 19, 2026 at 12:59 AM PDT, Bartosz Golaszewski wrote:
> On Mon, 19 Oct 2026 01:01:17 +0200, Rosen Penev <rosenp@gmail.com> said:
>> The Armada XP variant keeps the per-CPU edge/level mask registers in a
>> second I/O window (percpu_regs) rather than in the main GPIO window.
>> The suspend and resume paths however read and wrote them through
>> mvchip->regs with the per-CPU offsets, which hits the global
>> GPIO_EDGE_MASK / GPIO_LEVEL_MASK registers instead. Per-CPU mask state
>> was therefore lost across suspend/resume, so a level line could end up
>> unmasked behind genirq's back and trigger an interrupt storm once
>> interrupts are re-enabled.
>>
>> Use mvchip->percpu_regs for the Armada XP per-CPU mask registers in
>> both the suspend save and the resume restore paths, matching the
>> mask/unmask handlers and the probe-time masking.
>>
>> Fixes: b5b7b487431b ("gpio: mvebu: add suspend/resume support")
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Rosen Penev <rosenp@gmail.com>
>> ---
>>  v4: rebase again
>>  v3: rebase again
>>  v2: rebase
>
> Are you rebasing it on top of the gpio/for-next branch of the GPIO git tree
> as indicated in MAINTAINERS? Because this still fails to apply. :(
I cloned it, yes.
>
> Bart