* [PATCH AUTOSEL 5.1 33/39] pinctrl: mediatek: Ignore interrupts that are wake only during resume
From: Sasha Levin @ 2019-07-03 2:15 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Nicolas Boichat, Sean Wang, Linus Walleij, Sasha Levin,
linux-gpio
In-Reply-To: <20190703021514.17727-1-sashal@kernel.org>
From: Nicolas Boichat <drinkcat@chromium.org>
[ Upstream commit 35594bc7cecf3a78504b590e350570e8f4d7779e ]
Before suspending, mtk-eint would set the interrupt mask to the
one in wake_mask. However, some of these interrupts may not have a
corresponding interrupt handler, or the interrupt may be disabled.
On resume, the eint irq handler would trigger nevertheless,
and irq/pm.c:irq_pm_check_wakeup would be called, which would
try to call irq_disable. However, if the interrupt is not enabled
(irqd_irq_disabled(&desc->irq_data) is true), the call does nothing,
and the interrupt is left enabled in the eint driver.
Especially for level-sensitive interrupts, this will lead to an
interrupt storm on resume.
If we detect that an interrupt is only in wake_mask, but not in
cur_mask, we can just mask it out immediately (as mtk_eint_resume
would do anyway at a later stage in the resume sequence, when
restoring cur_mask).
Fixes: bf22ff45bed6 ("genirq: Avoid unnecessary low level irq function calls")
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Acked-by: Sean Wang <sean.wang@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/pinctrl/mediatek/mtk-eint.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c
index f464f8cd274b..737385e86beb 100644
--- a/drivers/pinctrl/mediatek/mtk-eint.c
+++ b/drivers/pinctrl/mediatek/mtk-eint.c
@@ -318,7 +318,7 @@ static void mtk_eint_irq_handler(struct irq_desc *desc)
struct irq_chip *chip = irq_desc_get_chip(desc);
struct mtk_eint *eint = irq_desc_get_handler_data(desc);
unsigned int status, eint_num;
- int offset, index, virq;
+ int offset, mask_offset, index, virq;
void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat);
int dual_edge, start_level, curr_level;
@@ -328,10 +328,24 @@ static void mtk_eint_irq_handler(struct irq_desc *desc)
status = readl(reg);
while (status) {
offset = __ffs(status);
+ mask_offset = eint_num >> 5;
index = eint_num + offset;
virq = irq_find_mapping(eint->domain, index);
status &= ~BIT(offset);
+ /*
+ * If we get an interrupt on pin that was only required
+ * for wake (but no real interrupt requested), mask the
+ * interrupt (as would mtk_eint_resume do anyway later
+ * in the resume sequence).
+ */
+ if (eint->wake_mask[mask_offset] & BIT(offset) &&
+ !(eint->cur_mask[mask_offset] & BIT(offset))) {
+ writel_relaxed(BIT(offset), reg -
+ eint->regs->stat +
+ eint->regs->mask_set);
+ }
+
dual_edge = eint->dual_edge[index];
if (dual_edge) {
/*
--
2.20.1
^ permalink raw reply related
* [PATCH AUTOSEL 5.1 25/39] pinctrl: ocelot: fix pinmuxing for pins after 31
From: Sasha Levin @ 2019-07-03 2:15 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Alexandre Belloni, Linus Walleij, Sasha Levin, linux-gpio
In-Reply-To: <20190703021514.17727-1-sashal@kernel.org>
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
[ Upstream commit 4b36082e2e09c2769710756390d54cfca563ed96 ]
The actual layout for OCELOT_GPIO_ALT[01] when there are more than 32 pins
is interleaved, i.e. OCELOT_GPIO_ALT0[0], OCELOT_GPIO_ALT1[0],
OCELOT_GPIO_ALT0[1], OCELOT_GPIO_ALT1[1]. Introduce a new REG_ALT macro to
facilitate the register offset calculation and use it where necessary.
Fixes: da801ab56ad8 pinctrl: ocelot: add MSCC Jaguar2 support
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/pinctrl/pinctrl-ocelot.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c
index d2478db975bd..fb76fb2e9ea5 100644
--- a/drivers/pinctrl/pinctrl-ocelot.c
+++ b/drivers/pinctrl/pinctrl-ocelot.c
@@ -396,7 +396,7 @@ static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
return -1;
}
-#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
+#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
@@ -412,19 +412,21 @@ static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
/*
* f is encoded on two bits.
- * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
- * ALT1
+ * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
+ * ALT[1]
* This is racy because both registers can't be updated at the same time
* but it doesn't matter much for now.
*/
- regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT0, info, pin->pin),
+ regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
BIT(p), f << p);
- regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT1, info, pin->pin),
+ regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
BIT(p), f << (p - 1));
return 0;
}
+#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
+
static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
@@ -445,9 +447,9 @@ static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
unsigned int p = offset % 32;
- regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT0, info, offset),
+ regmap_update_bits(info->map, REG_ALT(0, info, offset),
BIT(p), 0);
- regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT1, info, offset),
+ regmap_update_bits(info->map, REG_ALT(1, info, offset),
BIT(p), 0);
return 0;
--
2.20.1
^ permalink raw reply related
* [PATCH AUTOSEL 5.1 24/39] pinctrl: ocelot: fix gpio direction for pins after 31
From: Sasha Levin @ 2019-07-03 2:14 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Alexandre Belloni, Linus Walleij, Sasha Levin, linux-gpio
In-Reply-To: <20190703021514.17727-1-sashal@kernel.org>
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
[ Upstream commit f2818ba3a0125670cb9999bb5a65ebb631a8da2f ]
The third argument passed to REG is not the correct one and
ocelot_gpio_set_direction is not working for pins after 31. Fix that by
passing the pin number instead of the modulo 32 value.
Fixes: da801ab56ad8 pinctrl: ocelot: add MSCC Jaguar2 support
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/pinctrl/pinctrl-ocelot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c
index 3b4ca52d2456..d2478db975bd 100644
--- a/drivers/pinctrl/pinctrl-ocelot.c
+++ b/drivers/pinctrl/pinctrl-ocelot.c
@@ -432,7 +432,7 @@ static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
unsigned int p = pin % 32;
- regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, p), BIT(p),
+ regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
input ? 0 : BIT(p));
return 0;
--
2.20.1
^ permalink raw reply related
* [PATCH AUTOSEL 5.1 23/39] pinctrl: mcp23s08: Fix add_data and irqchip_add_nested call order
From: Sasha Levin @ 2019-07-03 2:14 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Phil Reid, Marco Felsch, Linus Walleij, Sasha Levin, linux-gpio
In-Reply-To: <20190703021514.17727-1-sashal@kernel.org>
From: Phil Reid <preid@electromag.com.au>
[ Upstream commit 6dbc6e6f58556369bf999cd7d9793586f1b0e4b4 ]
Currently probing of the mcp23s08 results in an error message
"detected irqchip that is shared with multiple gpiochips:
please fix the driver"
This is due to the following:
Call to mcp23s08_irqchip_setup() with call hierarchy:
mcp23s08_irqchip_setup()
gpiochip_irqchip_add_nested()
gpiochip_irqchip_add_key()
gpiochip_set_irq_hooks()
Call to devm_gpiochip_add_data() with call hierarchy:
devm_gpiochip_add_data()
gpiochip_add_data_with_key()
gpiochip_add_irqchip()
gpiochip_set_irq_hooks()
The gpiochip_add_irqchip() returns immediately if there isn't a irqchip
but we added a irqchip due to the previous mcp23s08_irqchip_setup()
call. So it calls gpiochip_set_irq_hooks() a second time.
Fix this by moving the call to devm_gpiochip_add_data before
the call to mcp23s08_irqchip_setup
Fixes: 02e389e63e35 ("pinctrl: mcp23s08: fix irq setup order")
Suggested-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Phil Reid <preid@electromag.com.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/pinctrl/pinctrl-mcp23s08.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c
index 5d7a8514def9..b727de5654cd 100644
--- a/drivers/pinctrl/pinctrl-mcp23s08.c
+++ b/drivers/pinctrl/pinctrl-mcp23s08.c
@@ -881,6 +881,10 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
if (ret < 0)
goto fail;
+ ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
+ if (ret < 0)
+ goto fail;
+
mcp->irq_controller =
device_property_read_bool(dev, "interrupt-controller");
if (mcp->irq && mcp->irq_controller) {
@@ -922,10 +926,6 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
goto fail;
}
- ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
- if (ret < 0)
- goto fail;
-
if (one_regmap_config) {
mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL,
"mcp23xxx-pinctrl.%d", raw_chip_address);
--
2.20.1
^ permalink raw reply related
* gpio desc flags being lost
From: Chris Packham @ 2019-07-03 5:35 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski
Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org
Hi LinusW, Bartosz,
I was debugging something else and I noticed a problem with the gpio
framework or the gpio-mmio driver (or both) in 5.2.0-rc6.
I have some gpio hogs in my device tree which seem to get requested at
startup as expected
...
GPIO line 456 (sw-reset) hogged as output/low
GPIO line 459 (phy-1g-reset) hogged as output/low
GPIO line 460 (i2c-reset) hogged as output/low
GPIO line 461 (lm81-reset) hogged as output/low
GPIO line 462 (phy-led-reset) hogged as output/low
GPIO line 448 (pcie-reset) hogged as output/low
..
I wanted to see what state these lines were in
# cat /sys/kernel/debug/gpio
gpiochip4: GPIOs 448-455, parent: platform/fffa00029.dev-reset-ctl-2,
fffa00029.dev-reset-ctl-2:
gpiochip3: GPIOs 456-463, parent: platform/fffa00020.dev-reset-ctl,
fffa00020.dev-reset-ctl:
I expected the hogs to show up here.
# echo 448 >/sys/class/gpio/export
Now I'm pretty sure I shouldn't be allowed to do that.
# cat /sys/kernel/debug/gpio
gpiochip4: GPIOs 448-455, parent: platform/fffa00029.dev-reset-ctl-2,
fffa00029.dev-reset-ctl-2:gpio-448 ( |sysfs
) in lo
Doing a bit of debugging so far I see that after startup the desc->flags
for those gpios is 0. But for the hogged ones it should be 0x800 (or 0x801).
I happen to have a 4.8.17 kernel for the board I'm using. Testing with
that seems to be OK.
[root@linuxbox ~]# uname -a
Linux linuxbox 4.8.17-at1+ #3 SMP Wed Jul 3 05:30:55 UTC 2019 ppc GNU/Linux
[root@linuxbox ~]# cat /sys/kernel/debug/gpio
gpiochip4: GPIOs 448-455, parent: platform/fffa00029.dev-reset-ctl-2,
fffa00029.dev-reset-ctl-2:
gpio-448 ( |pcie-reset ) out lo
gpiochip3: GPIOs 456-463, parent: platform/fffa00020.dev-reset-ctl,
fffa00020.dev-reset-ctl:
gpio-456 ( |sw-reset ) out lo
gpio-459 ( |phy-1g-reset ) out lo
gpio-460 ( |i2c-reset ) out lo
gpio-461 ( |lm81-reset ) out lo
gpio-462 ( |phy-led-reset ) out lo
[root@linuxbox ~]# echo 448 >/sys/class/gpio/export
sh: write error: Device or resource busy
I'll do some proper bisecting tomorrow, but figured you might want to
know sooner rather than later.
^ permalink raw reply
* Re: gpio desc flags being lost
From: Linus Walleij @ 2019-07-03 6:28 UTC (permalink / raw)
To: Chris Packham
Cc: Bartosz Golaszewski, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <d4724d7ec8ab4f95884ea947d9467e26@svr-chch-ex1.atlnz.lc>
On Wed, Jul 3, 2019 at 7:35 AM Chris Packham
<Chris.Packham@alliedtelesis.co.nz> wrote:
> Doing a bit of debugging so far I see that after startup the desc->flags
> for those gpios is 0. But for the hogged ones it should be 0x800 (or 0x801).
Yeah that is wrong.
> I'll do some proper bisecting tomorrow, but figured you might want to
> know sooner rather than later.
Thanks, I have another critical GPIO fix queued so would be great if we
can fix this too before v5.2 is released.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/4 v1] gpio: Add support for hierarchical IRQ domains
From: Linus Walleij @ 2019-07-03 6:33 UTC (permalink / raw)
To: Lina Iyer
Cc: open list:GPIO SUBSYSTEM, Bartosz Golaszewski, Thomas Gleixner,
Marc Zyngier, Jon Hunter, Sowjanya Komatineni, Bitan Biswas,
linux-tegra, David Daney, Masahiro Yamada, Brian Masney,
Thierry Reding
In-Reply-To: <20190628155817.GB24030@codeaurora.org>
On Fri, Jun 28, 2019 at 5:58 PM Lina Iyer <ilina@codeaurora.org> wrote:
> >I might be wrong, but then I need to see some example
> >of hierarchies that need something more than what the
> >gpiolib core is providing and idiomatic enough that it can't
> >be rewritten and absolutely must have its own ops.
>
> Here is an example of what I am working on [1]. The series is based on
> this patch. What I want to point out is the .alloc function. The TLMM
> irqchip's parent could be a PDC or a MPM depending on the QCOM SoC
> architecture. They behave differently. The PDC takes over for the GPIO
> and handles the monitoring etc, while the MPM comes into play only after
> the SoC is in low power therefore TLMM needs to do its job. The way to
> cleanly support both of themis to have our own .alloc functions to help
> understand the the wakeup-parent irqchip's behavior.
>
> Since I need my own .ops, it makes the function below irrelevant to
> gpiolib. While I would still need a function to translate to parent
> hwirq, I don't see it any beneficial to gpiolib.
OK I see, I am holding the patch set back for v5.4 so we can make
sure that yours and also Brian Masney's drivers will be able to
work with this. Let's try to get this in shape for the next kernel.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: pinctrl: qcom: Document missing gpio nodes
From: Bjorn Andersson @ 2019-07-03 7:17 UTC (permalink / raw)
To: Vinod Koul
Cc: Linus Walleij, linux-arm-msm, Andy Gross, Rob Herring,
Mark Rutland, linux-gpio, devicetree, linux-kernel
In-Reply-To: <20190702105045.27646-2-vkoul@kernel.org>
On Tue 02 Jul 03:50 PDT 2019, Vinod Koul wrote:
> The bindings for msm8998-pinctrl was missing gpio-ranges and
> gpio-reserved-ranges, so document them as well
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> .../bindings/pinctrl/qcom,msm8998-pinctrl.txt | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
> index e70c79bbbc5b..280af41eb86e 100644
> --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
> @@ -40,6 +40,14 @@ MSM8998 platform.
> Definition: must be 2. Specifying the pin number and flags, as defined
> in <dt-bindings/gpio/gpio.h>
>
> +- gpio-ranges:
> + Usage: required
> + Definition: see ../gpio/gpio.txt
> +
> +- gpio-reserved-ranges:
> + Usage: optional
> + Definition: see ../gpio/gpio.txt
> +
> Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
> a general description of GPIO and interrupt bindings.
>
> @@ -175,6 +183,8 @@ Example:
> interrupts = <0 208 0>;
> gpio-controller;
> #gpio-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 175>;
> + gpio-reserved-ranges = <0 4>, <81 4>;
> interrupt-controller;
> #interrupt-cells = <2>;
>
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH v2 2/3] dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
From: Bjorn Andersson @ 2019-07-03 7:18 UTC (permalink / raw)
To: Vinod Koul
Cc: Linus Walleij, linux-arm-msm, Prasad Sodagudi, Andy Gross,
Rob Herring, Mark Rutland, linux-gpio, devicetree, linux-kernel,
Isaac J . Manjarres
In-Reply-To: <20190702105045.27646-3-vkoul@kernel.org>
On Tue 02 Jul 03:50 PDT 2019, Vinod Koul wrote:
> From: Prasad Sodagudi <psodagud@codeaurora.org>
>
> Add the binding for the TLMM pinctrl block found in the SM8150 platform.
>
> Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
> Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
> [vkoul: add missing nodes of gpio range and reserved
> rewrote function names and order them]
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> .../bindings/pinctrl/qcom,sm8150-pinctrl.txt | 190 ++++++++++++++++++
> 1 file changed, 190 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
> new file mode 100644
> index 000000000000..fa37733e5102
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
> @@ -0,0 +1,190 @@
> +Qualcomm SM8150 TLMM block
> +
> +This binding describes the Top Level Mode Multiplexer block found in the
> +QCS404 platform.
> +
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be "qcom,sm8150-pinctrl"
> +
> +- reg:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: the base address and size of the north, south, west
> + and east TLMM tiles.
> +
> +- reg-names:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Defintiion: names for the cells of reg, must contain "north", "south"
> + "west" and "east".
> +
> +- interrupts:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: should specify the TLMM summary IRQ.
> +
> +- interrupt-controller:
> + Usage: required
> + Value type: <none>
> + Definition: identifies this node as an interrupt controller
> +
> +- #interrupt-cells:
> + Usage: required
> + Value type: <u32>
> + Definition: must be 2. Specifying the pin number and flags, as defined
> + in <dt-bindings/interrupt-controller/irq.h>
> +
> +- gpio-controller:
> + Usage: required
> + Value type: <none>
> + Definition: identifies this node as a gpio controller
> +
> +- #gpio-cells:
> + Usage: required
> + Value type: <u32>
> + Definition: must be 2. Specifying the pin number and flags, as defined
> + in <dt-bindings/gpio/gpio.h>
> +
> +- gpio-ranges:
> + Usage: required
> + Value type: <prop-encoded-array>
> + Definition: see ../gpio/gpio.txt
> +
> +- gpio-reserved-ranges:
> + Usage: optional
> + Value type: <prop-encoded-array>
> + Definition: see ../gpio/gpio.txt
> +
> +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
> +a general description of GPIO and interrupt bindings.
> +
> +Please refer to pinctrl-bindings.txt in this directory for details of the
> +common pinctrl bindings used by client devices, including the meaning of the
> +phrase "pin configuration node".
> +
> +The pin configuration nodes act as a container for an arbitrary number of
> +subnodes. Each of these subnodes represents some desired configuration for a
> +pin, a group, or a list of pins or groups. This configuration can include the
> +mux function to select on those pin(s)/group(s), and various pin configuration
> +parameters, such as pull-up, drive strength, etc.
> +
> +
> +PIN CONFIGURATION NODES:
> +
> +The name of each subnode is not important; all subnodes should be enumerated
> +and processed purely based on their content.
> +
> +Each subnode only affects those parameters that are explicitly listed. In
> +other words, a subnode that lists a mux function but no pin configuration
> +parameters implies no information about any pin configuration parameters.
> +Similarly, a pin subnode that describes a pullup parameter implies no
> +information about e.g. the mux function.
> +
> +
> +The following generic properties as defined in pinctrl-bindings.txt are valid
> +to specify in a pin configuration subnode:
> +
> +- pins:
> + Usage: required
> + Value type: <string-array>
> + Definition: List of gpio pins affected by the properties specified in
> + this subnode.
> +
> + Valid pins are:
> + gpio0-gpio149
> + Supports mux, bias and drive-strength
> +
> + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
> + sdc2_data sdc1_rclk
> + Supports bias and drive-strength
> +
> + ufs_reset
> + Supports bias and drive-strength
> +
> +- function:
> + Usage: required
> + Value type: <string>
> + Definition: Specify the alternative function to be configured for the
> + specified pins. Functions are only valid for gpio pins.
> + Valid values are:
> +
> + adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
> + atest_char0, atest_char1, atest_char2, atest_char3,
> + audio_ref, atest_usb1, atest_usb2, atest_usb10,
> + atest_usb11, atest_usb12, atest_usb13, atest_usb20,
> + atest_usb21, atest_usb22, atest_usb2, atest_usb23,
> + btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
> + cci_timer1, cci_timer2, cci_timer3, cci_timer4,
> + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
> + ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd,
> + emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
> + hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist,
> + lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
> + mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps,
> + pa_indicator, pci_e0, phase_flag, pll_bypassnl,
> + pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws,
> + prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable,
> + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s,
> + qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
> + qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16,
> + qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii,
> + sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s,
> + tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
> + tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
> + usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
> + wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset
> +
> +- bias-disable:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins should be configued as no pull.
> +
> +- bias-pull-down:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins should be configued as pull down.
> +
> +- bias-pull-up:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins should be configued as pull up.
> +
> +- output-high:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins are configured in output mode, driven
> + high.
> + Not valid for sdc pins.
> +
> +- output-low:
> + Usage: optional
> + Value type: <none>
> + Definition: The specified pins are configured in output mode, driven
> + low.
> + Not valid for sdc pins.
> +
> +- drive-strength:
> + Usage: optional
> + Value type: <u32>
> + Definition: Selects the drive strength for the specified pins, in mA.
> + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
> +
> +Example:
> +
> + tlmm: pinctrl@3000000 {
> + compatible = "qcom,sm8150-pinctrl";
> + reg = <0x03100000 0x300000>,
> + <0x03500000 0x300000>,
> + <0x03900000 0x300000>,
> + <0x03D00000 0x300000>;
> + reg-names = "west", "east", "north", "south";
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 175>;
> + gpio-reserved-ranges = <0 4>, <126 4>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH v2 3/3] pinctrl: qcom: Add SM8150 pinctrl driver
From: Bjorn Andersson @ 2019-07-03 7:19 UTC (permalink / raw)
To: Vinod Koul
Cc: Linus Walleij, linux-arm-msm, Prasad Sodagudi, Andy Gross,
Rob Herring, Mark Rutland, linux-gpio, devicetree, linux-kernel,
Isaac J . Manjarres
In-Reply-To: <20190702105045.27646-4-vkoul@kernel.org>
On Tue 02 Jul 03:50 PDT 2019, Vinod Koul wrote:
> From: Prasad Sodagudi <psodagud@codeaurora.org>
>
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for SM8150
>
> Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
> Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
> [vkoul: modify to use upstream tile support
> use upstream code style
> order the functions and squash functions]
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> drivers/pinctrl/qcom/Kconfig | 9 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-sm8150.c | 1548 +++++++++++++++++++++++++
> 3 files changed, 1558 insertions(+)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 2e66ab72c10b..47be1622dcf6 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -175,4 +175,13 @@ config PINCTRL_SDM845
> Qualcomm Technologies Inc TLMM block found on the Qualcomm
> Technologies Inc SDM845 platform.
>
> +config PINCTRL_SM8150
> + tristate "Qualcomm Technologies Inc SM8150 pin controller driver"
> + depends on GPIOLIB && OF
> + select PINCTRL_MSM
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc TLMM block found on the Qualcomm
> + Technologies Inc SM8150 platform.
> +
> endif
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 344b4c6a6c6e..ebe906872272 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -22,3 +22,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
> obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
> obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
> obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
> +obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c
> new file mode 100644
> index 000000000000..7359bae68c69
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c
> @@ -0,0 +1,1548 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-msm.h"
> +
> +static const char * const sm8150_tiles[] = {
> + "north",
> + "south",
> + "east",
> + "west"
> +};
> +
> +enum {
> + NORTH,
> + SOUTH,
> + EAST,
> + WEST
> +};
> +
> +#define FUNCTION(fname) \
> + [msm_mux_##fname] = { \
> + .name = #fname, \
> + .groups = fname##_groups, \
> + .ngroups = ARRAY_SIZE(fname##_groups), \
> + }
> +
> +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
> + { \
> + .name = "gpio" #id, \
> + .pins = gpio##id##_pins, \
> + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
> + .funcs = (int[]){ \
> + msm_mux_gpio, /* gpio mode */ \
> + msm_mux_##f1, \
> + msm_mux_##f2, \
> + msm_mux_##f3, \
> + msm_mux_##f4, \
> + msm_mux_##f5, \
> + msm_mux_##f6, \
> + msm_mux_##f7, \
> + msm_mux_##f8, \
> + msm_mux_##f9 \
> + }, \
> + .nfuncs = 10, \
> + .ctl_reg = 0x1000 * id, \
> + .io_reg = 0x1000 * id + 0x4, \
> + .intr_cfg_reg = 0x1000 * id + 0x8, \
> + .intr_status_reg = 0x1000 * id + 0xc, \
> + .intr_target_reg = 0x1000 * id + 0x8, \
> + .tile = _tile, \
> + .mux_bit = 2, \
> + .pull_bit = 0, \
> + .drv_bit = 6, \
> + .oe_bit = 9, \
> + .in_bit = 0, \
> + .out_bit = 1, \
> + .intr_enable_bit = 0, \
> + .intr_status_bit = 0, \
> + .intr_target_bit = 5, \
> + .intr_target_kpss_val = 3, \
> + .intr_raw_status_bit = 4, \
> + .intr_polarity_bit = 1, \
> + .intr_detection_bit = 2, \
> + .intr_detection_width = 2, \
> + }
> +
> +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
> + { \
> + .name = #pg_name, \
> + .pins = pg_name##_pins, \
> + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
> + .ctl_reg = ctl, \
> + .io_reg = 0, \
> + .intr_cfg_reg = 0, \
> + .intr_status_reg = 0, \
> + .intr_target_reg = 0, \
> + .tile = NORTH, \
> + .mux_bit = -1, \
> + .pull_bit = pull, \
> + .drv_bit = drv, \
> + .oe_bit = -1, \
> + .in_bit = -1, \
> + .out_bit = -1, \
> + .intr_enable_bit = -1, \
> + .intr_status_bit = -1, \
> + .intr_target_bit = -1, \
> + .intr_raw_status_bit = -1, \
> + .intr_polarity_bit = -1, \
> + .intr_detection_bit = -1, \
> + .intr_detection_width = -1, \
> + }
> +
> +#define UFS_RESET(pg_name, offset) \
> + { \
> + .name = #pg_name, \
> + .pins = pg_name##_pins, \
> + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
> + .ctl_reg = offset, \
> + .io_reg = offset + 0x4, \
> + .intr_cfg_reg = 0, \
> + .intr_status_reg = 0, \
> + .intr_target_reg = 0, \
> + .tile = SOUTH, \
> + .mux_bit = -1, \
> + .pull_bit = 3, \
> + .drv_bit = 0, \
> + .oe_bit = -1, \
> + .in_bit = -1, \
> + .out_bit = 0, \
> + .intr_enable_bit = -1, \
> + .intr_status_bit = -1, \
> + .intr_target_bit = -1, \
> + .intr_raw_status_bit = -1, \
> + .intr_polarity_bit = -1, \
> + .intr_detection_bit = -1, \
> + .intr_detection_width = -1, \
> + }
> +
> +static const struct pinctrl_pin_desc sm8150_pins[] = {
> + PINCTRL_PIN(0, "GPIO_0"),
> + PINCTRL_PIN(1, "GPIO_1"),
> + PINCTRL_PIN(2, "GPIO_2"),
> + PINCTRL_PIN(3, "GPIO_3"),
> + PINCTRL_PIN(4, "GPIO_4"),
> + PINCTRL_PIN(5, "GPIO_5"),
> + PINCTRL_PIN(6, "GPIO_6"),
> + PINCTRL_PIN(7, "GPIO_7"),
> + PINCTRL_PIN(8, "GPIO_8"),
> + PINCTRL_PIN(9, "GPIO_9"),
> + PINCTRL_PIN(10, "GPIO_10"),
> + PINCTRL_PIN(11, "GPIO_11"),
> + PINCTRL_PIN(12, "GPIO_12"),
> + PINCTRL_PIN(13, "GPIO_13"),
> + PINCTRL_PIN(14, "GPIO_14"),
> + PINCTRL_PIN(15, "GPIO_15"),
> + PINCTRL_PIN(16, "GPIO_16"),
> + PINCTRL_PIN(17, "GPIO_17"),
> + PINCTRL_PIN(18, "GPIO_18"),
> + PINCTRL_PIN(19, "GPIO_19"),
> + PINCTRL_PIN(20, "GPIO_20"),
> + PINCTRL_PIN(21, "GPIO_21"),
> + PINCTRL_PIN(22, "GPIO_22"),
> + PINCTRL_PIN(23, "GPIO_23"),
> + PINCTRL_PIN(24, "GPIO_24"),
> + PINCTRL_PIN(25, "GPIO_25"),
> + PINCTRL_PIN(26, "GPIO_26"),
> + PINCTRL_PIN(27, "GPIO_27"),
> + PINCTRL_PIN(28, "GPIO_28"),
> + PINCTRL_PIN(29, "GPIO_29"),
> + PINCTRL_PIN(30, "GPIO_30"),
> + PINCTRL_PIN(31, "GPIO_31"),
> + PINCTRL_PIN(32, "GPIO_32"),
> + PINCTRL_PIN(33, "GPIO_33"),
> + PINCTRL_PIN(34, "GPIO_34"),
> + PINCTRL_PIN(35, "GPIO_35"),
> + PINCTRL_PIN(36, "GPIO_36"),
> + PINCTRL_PIN(37, "GPIO_37"),
> + PINCTRL_PIN(38, "GPIO_38"),
> + PINCTRL_PIN(39, "GPIO_39"),
> + PINCTRL_PIN(40, "GPIO_40"),
> + PINCTRL_PIN(41, "GPIO_41"),
> + PINCTRL_PIN(42, "GPIO_42"),
> + PINCTRL_PIN(43, "GPIO_43"),
> + PINCTRL_PIN(44, "GPIO_44"),
> + PINCTRL_PIN(45, "GPIO_45"),
> + PINCTRL_PIN(46, "GPIO_46"),
> + PINCTRL_PIN(47, "GPIO_47"),
> + PINCTRL_PIN(48, "GPIO_48"),
> + PINCTRL_PIN(49, "GPIO_49"),
> + PINCTRL_PIN(50, "GPIO_50"),
> + PINCTRL_PIN(51, "GPIO_51"),
> + PINCTRL_PIN(52, "GPIO_52"),
> + PINCTRL_PIN(53, "GPIO_53"),
> + PINCTRL_PIN(54, "GPIO_54"),
> + PINCTRL_PIN(55, "GPIO_55"),
> + PINCTRL_PIN(56, "GPIO_56"),
> + PINCTRL_PIN(57, "GPIO_57"),
> + PINCTRL_PIN(58, "GPIO_58"),
> + PINCTRL_PIN(59, "GPIO_59"),
> + PINCTRL_PIN(60, "GPIO_60"),
> + PINCTRL_PIN(61, "GPIO_61"),
> + PINCTRL_PIN(62, "GPIO_62"),
> + PINCTRL_PIN(63, "GPIO_63"),
> + PINCTRL_PIN(64, "GPIO_64"),
> + PINCTRL_PIN(65, "GPIO_65"),
> + PINCTRL_PIN(66, "GPIO_66"),
> + PINCTRL_PIN(67, "GPIO_67"),
> + PINCTRL_PIN(68, "GPIO_68"),
> + PINCTRL_PIN(69, "GPIO_69"),
> + PINCTRL_PIN(70, "GPIO_70"),
> + PINCTRL_PIN(71, "GPIO_71"),
> + PINCTRL_PIN(72, "GPIO_72"),
> + PINCTRL_PIN(73, "GPIO_73"),
> + PINCTRL_PIN(74, "GPIO_74"),
> + PINCTRL_PIN(75, "GPIO_75"),
> + PINCTRL_PIN(76, "GPIO_76"),
> + PINCTRL_PIN(77, "GPIO_77"),
> + PINCTRL_PIN(78, "GPIO_78"),
> + PINCTRL_PIN(79, "GPIO_79"),
> + PINCTRL_PIN(80, "GPIO_80"),
> + PINCTRL_PIN(81, "GPIO_81"),
> + PINCTRL_PIN(82, "GPIO_82"),
> + PINCTRL_PIN(83, "GPIO_83"),
> + PINCTRL_PIN(84, "GPIO_84"),
> + PINCTRL_PIN(85, "GPIO_85"),
> + PINCTRL_PIN(86, "GPIO_86"),
> + PINCTRL_PIN(87, "GPIO_87"),
> + PINCTRL_PIN(88, "GPIO_88"),
> + PINCTRL_PIN(89, "GPIO_89"),
> + PINCTRL_PIN(90, "GPIO_90"),
> + PINCTRL_PIN(91, "GPIO_91"),
> + PINCTRL_PIN(92, "GPIO_92"),
> + PINCTRL_PIN(93, "GPIO_93"),
> + PINCTRL_PIN(94, "GPIO_94"),
> + PINCTRL_PIN(95, "GPIO_95"),
> + PINCTRL_PIN(96, "GPIO_96"),
> + PINCTRL_PIN(97, "GPIO_97"),
> + PINCTRL_PIN(98, "GPIO_98"),
> + PINCTRL_PIN(99, "GPIO_99"),
> + PINCTRL_PIN(100, "GPIO_100"),
> + PINCTRL_PIN(101, "GPIO_101"),
> + PINCTRL_PIN(102, "GPIO_102"),
> + PINCTRL_PIN(103, "GPIO_103"),
> + PINCTRL_PIN(104, "GPIO_104"),
> + PINCTRL_PIN(105, "GPIO_105"),
> + PINCTRL_PIN(106, "GPIO_106"),
> + PINCTRL_PIN(107, "GPIO_107"),
> + PINCTRL_PIN(108, "GPIO_108"),
> + PINCTRL_PIN(109, "GPIO_109"),
> + PINCTRL_PIN(110, "GPIO_110"),
> + PINCTRL_PIN(111, "GPIO_111"),
> + PINCTRL_PIN(112, "GPIO_112"),
> + PINCTRL_PIN(113, "GPIO_113"),
> + PINCTRL_PIN(114, "GPIO_114"),
> + PINCTRL_PIN(115, "GPIO_115"),
> + PINCTRL_PIN(116, "GPIO_116"),
> + PINCTRL_PIN(117, "GPIO_117"),
> + PINCTRL_PIN(118, "GPIO_118"),
> + PINCTRL_PIN(119, "GPIO_119"),
> + PINCTRL_PIN(120, "GPIO_120"),
> + PINCTRL_PIN(121, "GPIO_121"),
> + PINCTRL_PIN(122, "GPIO_122"),
> + PINCTRL_PIN(123, "GPIO_123"),
> + PINCTRL_PIN(124, "GPIO_124"),
> + PINCTRL_PIN(125, "GPIO_125"),
> + PINCTRL_PIN(126, "GPIO_126"),
> + PINCTRL_PIN(127, "GPIO_127"),
> + PINCTRL_PIN(128, "GPIO_128"),
> + PINCTRL_PIN(129, "GPIO_129"),
> + PINCTRL_PIN(130, "GPIO_130"),
> + PINCTRL_PIN(131, "GPIO_131"),
> + PINCTRL_PIN(132, "GPIO_132"),
> + PINCTRL_PIN(133, "GPIO_133"),
> + PINCTRL_PIN(134, "GPIO_134"),
> + PINCTRL_PIN(135, "GPIO_135"),
> + PINCTRL_PIN(136, "GPIO_136"),
> + PINCTRL_PIN(137, "GPIO_137"),
> + PINCTRL_PIN(138, "GPIO_138"),
> + PINCTRL_PIN(139, "GPIO_139"),
> + PINCTRL_PIN(140, "GPIO_140"),
> + PINCTRL_PIN(141, "GPIO_141"),
> + PINCTRL_PIN(142, "GPIO_142"),
> + PINCTRL_PIN(143, "GPIO_143"),
> + PINCTRL_PIN(144, "GPIO_144"),
> + PINCTRL_PIN(145, "GPIO_145"),
> + PINCTRL_PIN(146, "GPIO_146"),
> + PINCTRL_PIN(147, "GPIO_147"),
> + PINCTRL_PIN(148, "GPIO_148"),
> + PINCTRL_PIN(149, "GPIO_149"),
> + PINCTRL_PIN(150, "GPIO_150"),
> + PINCTRL_PIN(151, "GPIO_151"),
> + PINCTRL_PIN(152, "GPIO_152"),
> + PINCTRL_PIN(153, "GPIO_153"),
> + PINCTRL_PIN(154, "GPIO_154"),
> + PINCTRL_PIN(155, "GPIO_155"),
> + PINCTRL_PIN(156, "GPIO_156"),
> + PINCTRL_PIN(157, "GPIO_157"),
> + PINCTRL_PIN(158, "GPIO_158"),
> + PINCTRL_PIN(159, "GPIO_159"),
> + PINCTRL_PIN(160, "GPIO_160"),
> + PINCTRL_PIN(161, "GPIO_161"),
> + PINCTRL_PIN(162, "GPIO_162"),
> + PINCTRL_PIN(163, "GPIO_163"),
> + PINCTRL_PIN(164, "GPIO_164"),
> + PINCTRL_PIN(165, "GPIO_165"),
> + PINCTRL_PIN(166, "GPIO_166"),
> + PINCTRL_PIN(167, "GPIO_167"),
> + PINCTRL_PIN(168, "GPIO_168"),
> + PINCTRL_PIN(169, "GPIO_169"),
> + PINCTRL_PIN(170, "GPIO_170"),
> + PINCTRL_PIN(171, "GPIO_171"),
> + PINCTRL_PIN(172, "GPIO_172"),
> + PINCTRL_PIN(173, "GPIO_173"),
> + PINCTRL_PIN(174, "GPIO_174"),
> + PINCTRL_PIN(175, "UFS_RESET"),
> + PINCTRL_PIN(176, "SDC2_CLK"),
> + PINCTRL_PIN(177, "SDC2_CMD"),
> + PINCTRL_PIN(178, "SDC2_DATA"),
> +};
> +
> +#define DECLARE_MSM_GPIO_PINS(pin) \
> + static const unsigned int gpio##pin##_pins[] = { pin }
> +DECLARE_MSM_GPIO_PINS(0);
> +DECLARE_MSM_GPIO_PINS(1);
> +DECLARE_MSM_GPIO_PINS(2);
> +DECLARE_MSM_GPIO_PINS(3);
> +DECLARE_MSM_GPIO_PINS(4);
> +DECLARE_MSM_GPIO_PINS(5);
> +DECLARE_MSM_GPIO_PINS(6);
> +DECLARE_MSM_GPIO_PINS(7);
> +DECLARE_MSM_GPIO_PINS(8);
> +DECLARE_MSM_GPIO_PINS(9);
> +DECLARE_MSM_GPIO_PINS(10);
> +DECLARE_MSM_GPIO_PINS(11);
> +DECLARE_MSM_GPIO_PINS(12);
> +DECLARE_MSM_GPIO_PINS(13);
> +DECLARE_MSM_GPIO_PINS(14);
> +DECLARE_MSM_GPIO_PINS(15);
> +DECLARE_MSM_GPIO_PINS(16);
> +DECLARE_MSM_GPIO_PINS(17);
> +DECLARE_MSM_GPIO_PINS(18);
> +DECLARE_MSM_GPIO_PINS(19);
> +DECLARE_MSM_GPIO_PINS(20);
> +DECLARE_MSM_GPIO_PINS(21);
> +DECLARE_MSM_GPIO_PINS(22);
> +DECLARE_MSM_GPIO_PINS(23);
> +DECLARE_MSM_GPIO_PINS(24);
> +DECLARE_MSM_GPIO_PINS(25);
> +DECLARE_MSM_GPIO_PINS(26);
> +DECLARE_MSM_GPIO_PINS(27);
> +DECLARE_MSM_GPIO_PINS(28);
> +DECLARE_MSM_GPIO_PINS(29);
> +DECLARE_MSM_GPIO_PINS(30);
> +DECLARE_MSM_GPIO_PINS(31);
> +DECLARE_MSM_GPIO_PINS(32);
> +DECLARE_MSM_GPIO_PINS(33);
> +DECLARE_MSM_GPIO_PINS(34);
> +DECLARE_MSM_GPIO_PINS(35);
> +DECLARE_MSM_GPIO_PINS(36);
> +DECLARE_MSM_GPIO_PINS(37);
> +DECLARE_MSM_GPIO_PINS(38);
> +DECLARE_MSM_GPIO_PINS(39);
> +DECLARE_MSM_GPIO_PINS(40);
> +DECLARE_MSM_GPIO_PINS(41);
> +DECLARE_MSM_GPIO_PINS(42);
> +DECLARE_MSM_GPIO_PINS(43);
> +DECLARE_MSM_GPIO_PINS(44);
> +DECLARE_MSM_GPIO_PINS(45);
> +DECLARE_MSM_GPIO_PINS(46);
> +DECLARE_MSM_GPIO_PINS(47);
> +DECLARE_MSM_GPIO_PINS(48);
> +DECLARE_MSM_GPIO_PINS(49);
> +DECLARE_MSM_GPIO_PINS(50);
> +DECLARE_MSM_GPIO_PINS(51);
> +DECLARE_MSM_GPIO_PINS(52);
> +DECLARE_MSM_GPIO_PINS(53);
> +DECLARE_MSM_GPIO_PINS(54);
> +DECLARE_MSM_GPIO_PINS(55);
> +DECLARE_MSM_GPIO_PINS(56);
> +DECLARE_MSM_GPIO_PINS(57);
> +DECLARE_MSM_GPIO_PINS(58);
> +DECLARE_MSM_GPIO_PINS(59);
> +DECLARE_MSM_GPIO_PINS(60);
> +DECLARE_MSM_GPIO_PINS(61);
> +DECLARE_MSM_GPIO_PINS(62);
> +DECLARE_MSM_GPIO_PINS(63);
> +DECLARE_MSM_GPIO_PINS(64);
> +DECLARE_MSM_GPIO_PINS(65);
> +DECLARE_MSM_GPIO_PINS(66);
> +DECLARE_MSM_GPIO_PINS(67);
> +DECLARE_MSM_GPIO_PINS(68);
> +DECLARE_MSM_GPIO_PINS(69);
> +DECLARE_MSM_GPIO_PINS(70);
> +DECLARE_MSM_GPIO_PINS(71);
> +DECLARE_MSM_GPIO_PINS(72);
> +DECLARE_MSM_GPIO_PINS(73);
> +DECLARE_MSM_GPIO_PINS(74);
> +DECLARE_MSM_GPIO_PINS(75);
> +DECLARE_MSM_GPIO_PINS(76);
> +DECLARE_MSM_GPIO_PINS(77);
> +DECLARE_MSM_GPIO_PINS(78);
> +DECLARE_MSM_GPIO_PINS(79);
> +DECLARE_MSM_GPIO_PINS(80);
> +DECLARE_MSM_GPIO_PINS(81);
> +DECLARE_MSM_GPIO_PINS(82);
> +DECLARE_MSM_GPIO_PINS(83);
> +DECLARE_MSM_GPIO_PINS(84);
> +DECLARE_MSM_GPIO_PINS(85);
> +DECLARE_MSM_GPIO_PINS(86);
> +DECLARE_MSM_GPIO_PINS(87);
> +DECLARE_MSM_GPIO_PINS(88);
> +DECLARE_MSM_GPIO_PINS(89);
> +DECLARE_MSM_GPIO_PINS(90);
> +DECLARE_MSM_GPIO_PINS(91);
> +DECLARE_MSM_GPIO_PINS(92);
> +DECLARE_MSM_GPIO_PINS(93);
> +DECLARE_MSM_GPIO_PINS(94);
> +DECLARE_MSM_GPIO_PINS(95);
> +DECLARE_MSM_GPIO_PINS(96);
> +DECLARE_MSM_GPIO_PINS(97);
> +DECLARE_MSM_GPIO_PINS(98);
> +DECLARE_MSM_GPIO_PINS(99);
> +DECLARE_MSM_GPIO_PINS(100);
> +DECLARE_MSM_GPIO_PINS(101);
> +DECLARE_MSM_GPIO_PINS(102);
> +DECLARE_MSM_GPIO_PINS(103);
> +DECLARE_MSM_GPIO_PINS(104);
> +DECLARE_MSM_GPIO_PINS(105);
> +DECLARE_MSM_GPIO_PINS(106);
> +DECLARE_MSM_GPIO_PINS(107);
> +DECLARE_MSM_GPIO_PINS(108);
> +DECLARE_MSM_GPIO_PINS(109);
> +DECLARE_MSM_GPIO_PINS(110);
> +DECLARE_MSM_GPIO_PINS(111);
> +DECLARE_MSM_GPIO_PINS(112);
> +DECLARE_MSM_GPIO_PINS(113);
> +DECLARE_MSM_GPIO_PINS(114);
> +DECLARE_MSM_GPIO_PINS(115);
> +DECLARE_MSM_GPIO_PINS(116);
> +DECLARE_MSM_GPIO_PINS(117);
> +DECLARE_MSM_GPIO_PINS(118);
> +DECLARE_MSM_GPIO_PINS(119);
> +DECLARE_MSM_GPIO_PINS(120);
> +DECLARE_MSM_GPIO_PINS(121);
> +DECLARE_MSM_GPIO_PINS(122);
> +DECLARE_MSM_GPIO_PINS(123);
> +DECLARE_MSM_GPIO_PINS(124);
> +DECLARE_MSM_GPIO_PINS(125);
> +DECLARE_MSM_GPIO_PINS(126);
> +DECLARE_MSM_GPIO_PINS(127);
> +DECLARE_MSM_GPIO_PINS(128);
> +DECLARE_MSM_GPIO_PINS(129);
> +DECLARE_MSM_GPIO_PINS(130);
> +DECLARE_MSM_GPIO_PINS(131);
> +DECLARE_MSM_GPIO_PINS(132);
> +DECLARE_MSM_GPIO_PINS(133);
> +DECLARE_MSM_GPIO_PINS(134);
> +DECLARE_MSM_GPIO_PINS(135);
> +DECLARE_MSM_GPIO_PINS(136);
> +DECLARE_MSM_GPIO_PINS(137);
> +DECLARE_MSM_GPIO_PINS(138);
> +DECLARE_MSM_GPIO_PINS(139);
> +DECLARE_MSM_GPIO_PINS(140);
> +DECLARE_MSM_GPIO_PINS(141);
> +DECLARE_MSM_GPIO_PINS(142);
> +DECLARE_MSM_GPIO_PINS(143);
> +DECLARE_MSM_GPIO_PINS(144);
> +DECLARE_MSM_GPIO_PINS(145);
> +DECLARE_MSM_GPIO_PINS(146);
> +DECLARE_MSM_GPIO_PINS(147);
> +DECLARE_MSM_GPIO_PINS(148);
> +DECLARE_MSM_GPIO_PINS(149);
> +DECLARE_MSM_GPIO_PINS(150);
> +DECLARE_MSM_GPIO_PINS(151);
> +DECLARE_MSM_GPIO_PINS(152);
> +DECLARE_MSM_GPIO_PINS(153);
> +DECLARE_MSM_GPIO_PINS(154);
> +DECLARE_MSM_GPIO_PINS(155);
> +DECLARE_MSM_GPIO_PINS(156);
> +DECLARE_MSM_GPIO_PINS(157);
> +DECLARE_MSM_GPIO_PINS(158);
> +DECLARE_MSM_GPIO_PINS(159);
> +DECLARE_MSM_GPIO_PINS(160);
> +DECLARE_MSM_GPIO_PINS(161);
> +DECLARE_MSM_GPIO_PINS(162);
> +DECLARE_MSM_GPIO_PINS(163);
> +DECLARE_MSM_GPIO_PINS(164);
> +DECLARE_MSM_GPIO_PINS(165);
> +DECLARE_MSM_GPIO_PINS(166);
> +DECLARE_MSM_GPIO_PINS(167);
> +DECLARE_MSM_GPIO_PINS(168);
> +DECLARE_MSM_GPIO_PINS(169);
> +DECLARE_MSM_GPIO_PINS(170);
> +DECLARE_MSM_GPIO_PINS(171);
> +DECLARE_MSM_GPIO_PINS(172);
> +DECLARE_MSM_GPIO_PINS(173);
> +DECLARE_MSM_GPIO_PINS(174);
> +
> +static const unsigned int ufs_reset_pins[] = { 175 };
> +static const unsigned int sdc2_clk_pins[] = { 176 };
> +static const unsigned int sdc2_cmd_pins[] = { 177 };
> +static const unsigned int sdc2_data_pins[] = { 178 };
> +
> +enum sm8150_functions {
> + msm_mux_adsp_ext,
> + msm_mux_agera_pll,
> + msm_mux_aoss_cti,
> + msm_mux_atest_char,
> + msm_mux_atest_char0,
> + msm_mux_atest_char1,
> + msm_mux_atest_char2,
> + msm_mux_atest_char3,
> + msm_mux_atest_usb1,
> + msm_mux_atest_usb2,
> + msm_mux_atest_usb10,
> + msm_mux_atest_usb11,
> + msm_mux_atest_usb12,
> + msm_mux_atest_usb13,
> + msm_mux_atest_usb20,
> + msm_mux_atest_usb21,
> + msm_mux_atest_usb22,
> + msm_mux_atest_usb23,
> + msm_mux_audio_ref,
> + msm_mux_btfm_slimbus,
> + msm_mux_cam_mclk,
> + msm_mux_cci_async,
> + msm_mux_cci_i2c,
> + msm_mux_cci_timer0,
> + msm_mux_cci_timer1,
> + msm_mux_cci_timer2,
> + msm_mux_cci_timer3,
> + msm_mux_cci_timer4,
> + msm_mux_cri_trng,
> + msm_mux_cri_trng0,
> + msm_mux_cri_trng1,
> + msm_mux_dbg_out,
> + msm_mux_ddr_bist,
> + msm_mux_ddr_pxi0,
> + msm_mux_ddr_pxi1,
> + msm_mux_ddr_pxi2,
> + msm_mux_ddr_pxi3,
> + msm_mux_edp_hot,
> + msm_mux_edp_lcd,
> + msm_mux_emac_phy,
> + msm_mux_emac_pps,
> + msm_mux_gcc_gp1,
> + msm_mux_gcc_gp2,
> + msm_mux_gcc_gp3,
> + msm_mux_gpio,
> + msm_mux_jitter_bist,
> + msm_mux_hs1_mi2s,
> + msm_mux_hs2_mi2s,
> + msm_mux_hs3_mi2s,
> + msm_mux_lpass_slimbus,
> + msm_mux_mdp_vsync,
> + msm_mux_mdp_vsync0,
> + msm_mux_mdp_vsync1,
> + msm_mux_mdp_vsync2,
> + msm_mux_mdp_vsync3,
> + msm_mux_mss_lte,
> + msm_mux_m_voc,
> + msm_mux_nav_pps,
> + msm_mux_pa_indicator,
> + msm_mux_pci_e0,
> + msm_mux_pci_e1,
> + msm_mux_phase_flag,
> + msm_mux_pll_bist,
> + msm_mux_pll_bypassnl,
> + msm_mux_pll_reset,
> + msm_mux_pri_mi2s,
> + msm_mux_pri_mi2s_ws,
> + msm_mux_prng_rosc,
> + msm_mux_qdss,
> + msm_mux_qdss_cti,
> + msm_mux_qlink_enable,
> + msm_mux_qlink_request,
> + msm_mux_qspi0,
> + msm_mux_qspi1,
> + msm_mux_qspi2,
> + msm_mux_qspi3,
> + msm_mux_qspi_clk,
> + msm_mux_qspi_cs,
> + msm_mux_qua_mi2s,
> + msm_mux_qup0,
> + msm_mux_qup1,
> + msm_mux_qup2,
> + msm_mux_qup3,
> + msm_mux_qup4,
> + msm_mux_qup5,
> + msm_mux_qup6,
> + msm_mux_qup7,
> + msm_mux_qup8,
> + msm_mux_qup9,
> + msm_mux_qup10,
> + msm_mux_qup11,
> + msm_mux_qup12,
> + msm_mux_qup13,
> + msm_mux_qup14,
> + msm_mux_qup15,
> + msm_mux_qup16,
> + msm_mux_qup17,
> + msm_mux_qup18,
> + msm_mux_qup19,
> + msm_mux_qup_l4,
> + msm_mux_qup_l5,
> + msm_mux_qup_l6,
> + msm_mux_rgmii,
> + msm_mux_sdc4,
> + msm_mux_sd_write,
> + msm_mux_sec_mi2s,
> + msm_mux_spkr_i2s,
> + msm_mux_sp_cmu,
> + msm_mux_ter_mi2s,
> + msm_mux_tgu_ch0,
> + msm_mux_tgu_ch2,
> + msm_mux_tgu_ch1,
> + msm_mux_tgu_ch3,
> + msm_mux_tsense_pwm1,
> + msm_mux_tsense_pwm2,
> + msm_mux_tsif1,
> + msm_mux_tsif2,
> + msm_mux_uim1,
> + msm_mux_uim2,
> + msm_mux_uim_batt,
> + msm_mux_usb2phy_ac,
> + msm_mux_usb_phy,
> + msm_mux_vfr_1,
> + msm_mux_vsense_trigger,
> + msm_mux_wlan1_adc1,
> + msm_mux_wlan1_adc0,
> + msm_mux_wlan2_adc1,
> + msm_mux_wlan2_adc0,
> + msm_mux_wmss_reset,
> + msm_mux__,
> +};
> +
> +static const char * const phase_flag_groups[] = {
> + "gpio18", "gpio19", "gpio20", "gpio55", "gpio56",
> + "gpio57", "gpio59", "gpio64", "gpio68", "gpio76",
> + "gpio79", "gpio80", "gpio90", "gpio91", "gpio92",
> + "gpio93", "gpio94", "gpio96", "gpio114", "gpio115",
> + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120",
> + "gpio121", "gpio122", "gpio126", "gpio127", "gpio128",
> + "gpio144", "gpio145",
> +};
> +
> +static const char * const emac_pps_groups[] = {
> + "gpio81",
> +};
> +
> +static const char * const qup12_groups[] = {
> + "gpio83", "gpio84", "gpio85", "gpio86",
> +};
> +
> +static const char * const qup16_groups[] = {
> + "gpio83", "gpio84", "gpio85", "gpio86",
> +};
> +
> +static const char * const tsif1_groups[] = {
> + "gpio88", "gpio89", "gpio90", "gpio91", "gpio97",
> +};
> +
> +static const char * const qup8_groups[] = {
> + "gpio88", "gpio89", "gpio90", "gpio91",
> +};
> +
> +static const char * const qspi_cs_groups[] = {
> + "gpio88", "gpio94",
> +};
> +
> +static const char * const tgu_ch3_groups[] = {
> + "gpio88",
> +};
> +
> +static const char * const qspi0_groups[] = {
> + "gpio89",
> +};
> +
> +static const char * const mdp_vsync0_groups[] = {
> + "gpio89",
> +};
> +
> +static const char * const mdp_vsync1_groups[] = {
> + "gpio89",
> +};
> +
> +static const char * const mdp_vsync2_groups[] = {
> + "gpio89",
> +};
> +
> +static const char * const mdp_vsync3_groups[] = {
> + "gpio89",
> +};
> +
> +static const char * const tgu_ch0_groups[] = {
> + "gpio89",
> +};
> +
> +static const char * const qspi1_groups[] = {
> + "gpio90",
> +};
> +
> +static const char * const sdc4_groups[] = {
> + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
> +};
> +
> +static const char * const tgu_ch1_groups[] = {
> + "gpio90",
> +};
> +
> +static const char * const wlan1_adc1_groups[] = {
> + "gpio90",
> +};
> +
> +static const char * const qspi2_groups[] = {
> + "gpio91",
> +};
> +
> +static const char * const vfr_1_groups[] = {
> + "gpio91",
> +};
> +
> +static const char * const tgu_ch2_groups[] = {
> + "gpio91",
> +};
> +
> +static const char * const wlan1_adc0_groups[] = {
> + "gpio91",
> +};
> +
> +static const char * const tsif2_groups[] = {
> + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
> +};
> +
> +static const char * const qup11_groups[] = {
> + "gpio92", "gpio93", "gpio94", "gpio95",
> +};
> +
> +static const char * const qspi_clk_groups[] = {
> + "gpio92",
> +};
> +
> +static const char * const wlan2_adc1_groups[] = {
> + "gpio92",
> +};
> +
> +static const char * const qspi3_groups[] = {
> + "gpio93",
> +};
> +
> +static const char * const wlan2_adc0_groups[] = {
> + "gpio93",
> +};
> +
> +static const char * const sd_write_groups[] = {
> + "gpio97",
> +};
> +
> +static const char * const qup7_groups[] = {
> + "gpio98", "gpio99", "gpio100", "gpio101",
> +};
> +
> +static const char * const ddr_bist_groups[] = {
> + "gpio98", "gpio99", "gpio145", "gpio146",
> +};
> +
> +static const char * const ddr_pxi3_groups[] = {
> + "gpio98", "gpio101",
> +};
> +
> +static const char * const atest_usb13_groups[] = {
> + "gpio99",
> +};
> +
> +static const char * const ddr_pxi1_groups[] = {
> + "gpio99", "gpio100",
> +};
> +
> +static const char * const pll_bypassnl_groups[] = {
> + "gpio100",
> +};
> +
> +static const char * const atest_usb12_groups[] = {
> + "gpio100",
> +};
> +
> +static const char * const pll_reset_groups[] = {
> + "gpio101",
> +};
> +
> +static const char * const pci_e1_groups[] = {
> + "gpio102", "gpio103",
> +};
> +
> +static const char * const uim2_groups[] = {
> + "gpio105", "gpio106", "gpio107", "gpio108",
> +};
> +
> +static const char * const uim1_groups[] = {
> + "gpio109", "gpio110", "gpio111", "gpio112",
> +};
> +
> +static const char * const uim_batt_groups[] = {
> + "gpio113",
> +};
> +
> +static const char * const usb2phy_ac_groups[] = {
> + "gpio113", "gpio123",
> +};
> +
> +static const char * const aoss_cti_groups[] = {
> + "gpio113",
> +};
> +
> +static const char * const qup1_groups[] = {
> + "gpio114", "gpio115", "gpio116", "gpio117",
> +};
> +
> +static const char * const rgmii_groups[] = {
> + "gpio4", "gpio5", "gpio6", "gpio7", "gpio59",
> + "gpio114", "gpio115", "gpio116", "gpio117",
> + "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
> +};
> +
> +static const char * const adsp_ext_groups[] = {
> + "gpio115",
> +};
> +
> +static const char * const qup5_groups[] = {
> + "gpio119", "gpio120", "gpio121", "gpio122",
> +};
> +
> +static const char * const atest_usb22_groups[] = {
> + "gpio123",
> +};
> +
> +static const char * const emac_phy_groups[] = {
> + "gpio124",
> +};
> +
> +static const char * const hs3_mi2s_groups[] = {
> + "gpio125", "gpio165", "gpio166", "gpio167", "gpio168",
> +};
> +
> +static const char * const sec_mi2s_groups[] = {
> + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130",
> +};
> +
> +static const char * const qup2_groups[] = {
> + "gpio126", "gpio127", "gpio128", "gpio129",
> +};
> +
> +static const char * const jitter_bist_groups[] = {
> + "gpio129",
> +};
> +
> +static const char * const atest_usb21_groups[] = {
> + "gpio129",
> +};
> +
> +static const char * const pll_bist_groups[] = {
> + "gpio130",
> +};
> +
> +static const char * const atest_usb20_groups[] = {
> + "gpio130",
> +};
> +
> +static const char * const atest_char0_groups[] = {
> + "gpio130",
> +};
> +
> +static const char * const ter_mi2s_groups[] = {
> + "gpio131", "gpio132", "gpio133", "gpio134", "gpio135",
> +};
> +
> +static const char * const gcc_gp1_groups[] = {
> + "gpio131", "gpio136",
> +};
> +
> +static const char * const atest_char1_groups[] = {
> + "gpio133",
> +};
> +
> +static const char * const atest_char2_groups[] = {
> + "gpio134",
> +};
> +
> +static const char * const atest_char3_groups[] = {
> + "gpio135",
> +};
> +
> +static const char * const qua_mi2s_groups[] = {
> + "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141",
> + "gpio142",
> +};
> +
> +static const char * const pri_mi2s_groups[] = {
> + "gpio143", "gpio144", "gpio146", "gpio147",
> +};
> +
> +static const char * const qup3_groups[] = {
> + "gpio144", "gpio145", "gpio146", "gpio147",
> +};
> +
> +static const char * const ddr_pxi0_groups[] = {
> + "gpio144", "gpio145",
> +};
> +
> +static const char * const pri_mi2s_ws_groups[] = {
> + "gpio145",
> +};
> +
> +static const char * const vsense_trigger_groups[] = {
> + "gpio145",
> +};
> +
> +static const char * const atest_usb1_groups[] = {
> + "gpio145",
> +};
> +
> +static const char * const atest_usb11_groups[] = {
> + "gpio146",
> +};
> +
> +static const char * const ddr_pxi2_groups[] = {
> + "gpio146", "gpio147",
> +};
> +
> +static const char * const dbg_out_groups[] = {
> + "gpio147",
> +};
> +
> +static const char * const atest_usb10_groups[] = {
> + "gpio147",
> +};
> +
> +static const char * const spkr_i2s_groups[] = {
> + "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
> +};
> +
> +static const char * const audio_ref_groups[] = {
> + "gpio148",
> +};
> +
> +static const char * const lpass_slimbus_groups[] = {
> + "gpio149", "gpio150", "gpio151", "gpio152",
> +};
> +
> +static const char * const tsense_pwm1_groups[] = {
> + "gpio150",
> +};
> +
> +static const char * const tsense_pwm2_groups[] = {
> + "gpio150",
> +};
> +
> +static const char * const btfm_slimbus_groups[] = {
> + "gpio153", "gpio154",
> +};
> +
> +static const char * const hs1_mi2s_groups[] = {
> + "gpio155", "gpio156", "gpio157", "gpio158", "gpio159",
> +};
> +
> +static const char * const cri_trng0_groups[] = {
> + "gpio159",
> +};
> +
> +static const char * const hs2_mi2s_groups[] = {
> + "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
> +};
> +
> +static const char * const cri_trng1_groups[] = {
> + "gpio160",
> +};
> +
> +static const char * const cri_trng_groups[] = {
> + "gpio161",
> +};
> +
> +static const char * const sp_cmu_groups[] = {
> + "gpio162",
> +};
> +
> +static const char * const prng_rosc_groups[] = {
> + "gpio163",
> +};
> +
> +static const char * const qup0_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3",
> +};
> +
> +static const char * const gpio_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
> + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
> + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
> + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
> + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
> + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
> + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
> + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
> + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
> + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
> + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
> + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
> + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
> + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
> + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
> + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
> + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
> + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
> + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
> + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
> + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
> + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
> + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
> + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
> + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
> + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
> + "gpio171", "gpio172", "gpio173", "gpio174",
> +};
> +
> +static const char * const qup6_groups[] = {
> + "gpio4", "gpio5", "gpio6", "gpio7",
> +};
> +
> +static const char * const qup_l6_groups[] = {
> + "gpio6", "gpio34", "gpio97", "gpio123",
> +};
> +
> +static const char * const qup_l5_groups[] = {
> + "gpio7", "gpio33", "gpio82", "gpio96",
> +};
> +
> +static const char * const mdp_vsync_groups[] = {
> + "gpio8", "gpio9", "gpio10", "gpio81", "gpio82",
> +};
> +
> +static const char * const edp_lcd_groups[] = {
> + "gpio9",
> +};
> +
> +static const char * const qup10_groups[] = {
> + "gpio9", "gpio10", "gpio11", "gpio12",
> +};
> +
> +static const char * const m_voc_groups[] = {
> + "gpio10",
> +};
> +
> +static const char * const edp_hot_groups[] = {
> + "gpio10",
> +};
> +
> +static const char * const cam_mclk_groups[] = {
> + "gpio13", "gpio14", "gpio15", "gpio16",
> +};
> +
> +static const char * const qdss_groups[] = {
> + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
> + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
> + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
> + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
> + "gpio33", "gpio39", "gpio40", "gpio41", "gpio42",
> + "gpio47", "gpio48", "gpio83", "gpio117", "gpio118",
> + "gpio119", "gpio120", "gpio121", "gpio132",
> + "gpio133", "gpio134",
> +};
> +
> +static const char * const cci_i2c_groups[] = {
> + "gpio17", "gpio18", "gpio19", "gpio20", "gpio31", "gpio32", "gpio33",
> + "gpio34",
> +};
> +
> +static const char * const cci_timer0_groups[] = {
> + "gpio21",
> +};
> +
> +static const char * const gcc_gp2_groups[] = {
> + "gpio21", "gpio137",
> +};
> +
> +static const char * const cci_timer1_groups[] = {
> + "gpio22",
> +};
> +
> +static const char * const gcc_gp3_groups[] = {
> + "gpio22", "gpio138",
> +};
> +
> +static const char * const cci_timer2_groups[] = {
> + "gpio23",
> +};
> +
> +static const char * const qup18_groups[] = {
> + "gpio23", "gpio24", "gpio25", "gpio26",
> +};
> +
> +static const char * const cci_timer3_groups[] = {
> + "gpio24",
> +};
> +
> +static const char * const cci_async_groups[] = {
> + "gpio24", "gpio25", "gpio26",
> +};
> +
> +static const char * const cci_timer4_groups[] = {
> + "gpio25",
> +};
> +
> +static const char * const qup15_groups[] = {
> + "gpio27", "gpio28", "gpio29", "gpio30",
> +};
> +
> +static const char * const pci_e0_groups[] = {
> + "gpio35", "gpio36",
> +};
> +
> +static const char * const qup_l4_groups[] = {
> + "gpio37", "gpio59", "gpio81", "gpio95",
> +};
> +
> +static const char * const agera_pll_groups[] = {
> + "gpio37",
> +};
> +
> +static const char * const usb_phy_groups[] = {
> + "gpio38",
> +};
> +
> +static const char * const qup9_groups[] = {
> + "gpio39", "gpio40", "gpio41", "gpio42",
> +};
> +
> +static const char * const qup13_groups[] = {
> + "gpio43", "gpio44", "gpio45", "gpio46",
> +};
> +
> +static const char * const qdss_cti_groups[] = {
> + "gpio45", "gpio46", "gpio49", "gpio50", "gpio56", "gpio57", "gpio58",
> + "gpio58",
> +};
> +
> +static const char * const qup14_groups[] = {
> + "gpio47", "gpio48", "gpio49", "gpio50",
> +};
> +
> +static const char * const qup4_groups[] = {
> + "gpio51", "gpio52", "gpio53", "gpio54",
> +};
> +
> +static const char * const qup17_groups[] = {
> + "gpio55", "gpio56", "gpio57", "gpio58",
> +};
> +
> +static const char * const qup19_groups[] = {
> + "gpio55", "gpio56", "gpio57", "gpio58",
> +};
> +
> +static const char * const atest_char_groups[] = {
> + "gpio59",
> +};
> +
> +static const char * const nav_pps_groups[] = {
> + "gpio60", "gpio60", "gpio76", "gpio76", "gpio77", "gpio77", "gpio81",
> + "gpio81", "gpio82", "gpio82",
> +};
> +
> +static const char * const atest_usb2_groups[] = {
> + "gpio60",
> +};
> +
> +static const char * const qlink_request_groups[] = {
> + "gpio61",
> +};
> +
> +static const char * const qlink_enable_groups[] = {
> + "gpio62",
> +};
> +
> +static const char * const wmss_reset_groups[] = {
> + "gpio63",
> +};
> +
> +static const char * const atest_usb23_groups[] = {
> + "gpio63",
> +};
> +
> +static const char * const pa_indicator_groups[] = {
> + "gpio68",
> +};
> +
> +static const char * const mss_lte_groups[] = {
> + "gpio69", "gpio70",
> +};
> +
> +static const struct msm_function sm8150_functions[] = {
> + FUNCTION(adsp_ext),
> + FUNCTION(agera_pll),
> + FUNCTION(aoss_cti),
> + FUNCTION(ddr_pxi2),
> + FUNCTION(atest_char),
> + FUNCTION(atest_char0),
> + FUNCTION(atest_char1),
> + FUNCTION(atest_char2),
> + FUNCTION(atest_char3),
> + FUNCTION(audio_ref),
> + FUNCTION(atest_usb1),
> + FUNCTION(atest_usb2),
> + FUNCTION(atest_usb10),
> + FUNCTION(atest_usb11),
> + FUNCTION(atest_usb12),
> + FUNCTION(atest_usb13),
> + FUNCTION(atest_usb20),
> + FUNCTION(atest_usb21),
> + FUNCTION(atest_usb22),
> + FUNCTION(atest_usb23),
> + FUNCTION(btfm_slimbus),
> + FUNCTION(cam_mclk),
> + FUNCTION(cci_async),
> + FUNCTION(cci_i2c),
> + FUNCTION(cci_timer0),
> + FUNCTION(cci_timer1),
> + FUNCTION(cci_timer2),
> + FUNCTION(cci_timer3),
> + FUNCTION(cci_timer4),
> + FUNCTION(cri_trng),
> + FUNCTION(cri_trng0),
> + FUNCTION(cri_trng1),
> + FUNCTION(dbg_out),
> + FUNCTION(ddr_bist),
> + FUNCTION(ddr_pxi0),
> + FUNCTION(ddr_pxi1),
> + FUNCTION(ddr_pxi3),
> + FUNCTION(edp_hot),
> + FUNCTION(edp_lcd),
> + FUNCTION(emac_phy),
> + FUNCTION(emac_pps),
> + FUNCTION(gcc_gp1),
> + FUNCTION(gcc_gp2),
> + FUNCTION(gcc_gp3),
> + FUNCTION(gpio),
> + FUNCTION(hs1_mi2s),
> + FUNCTION(hs2_mi2s),
> + FUNCTION(hs3_mi2s),
> + FUNCTION(jitter_bist),
> + FUNCTION(lpass_slimbus),
> + FUNCTION(mdp_vsync),
> + FUNCTION(mdp_vsync0),
> + FUNCTION(mdp_vsync1),
> + FUNCTION(mdp_vsync2),
> + FUNCTION(mdp_vsync3),
> + FUNCTION(mss_lte),
> + FUNCTION(m_voc),
> + FUNCTION(nav_pps),
> + FUNCTION(pa_indicator),
> + FUNCTION(pci_e0),
> + FUNCTION(phase_flag),
> + FUNCTION(pll_bypassnl),
> + FUNCTION(pll_bist),
> + FUNCTION(pci_e1),
> + FUNCTION(pll_reset),
> + FUNCTION(pri_mi2s),
> + FUNCTION(pri_mi2s_ws),
> + FUNCTION(prng_rosc),
> + FUNCTION(qdss),
> + FUNCTION(qdss_cti),
> + FUNCTION(qlink_request),
> + FUNCTION(qlink_enable),
> + FUNCTION(qspi0),
> + FUNCTION(qspi1),
> + FUNCTION(qspi2),
> + FUNCTION(qspi3),
> + FUNCTION(qspi_clk),
> + FUNCTION(qspi_cs),
> + FUNCTION(qua_mi2s),
> + FUNCTION(qup0),
> + FUNCTION(qup1),
> + FUNCTION(qup2),
> + FUNCTION(qup3),
> + FUNCTION(qup4),
> + FUNCTION(qup5),
> + FUNCTION(qup6),
> + FUNCTION(qup7),
> + FUNCTION(qup8),
> + FUNCTION(qup9),
> + FUNCTION(qup10),
> + FUNCTION(qup11),
> + FUNCTION(qup12),
> + FUNCTION(qup13),
> + FUNCTION(qup14),
> + FUNCTION(qup15),
> + FUNCTION(qup16),
> + FUNCTION(qup17),
> + FUNCTION(qup18),
> + FUNCTION(qup19),
> + FUNCTION(qup_l4),
> + FUNCTION(qup_l5),
> + FUNCTION(qup_l6),
> + FUNCTION(rgmii),
> + FUNCTION(sdc4),
> + FUNCTION(sd_write),
> + FUNCTION(sec_mi2s),
> + FUNCTION(spkr_i2s),
> + FUNCTION(sp_cmu),
> + FUNCTION(ter_mi2s),
> + FUNCTION(tgu_ch0),
> + FUNCTION(tgu_ch1),
> + FUNCTION(tgu_ch2),
> + FUNCTION(tgu_ch3),
> + FUNCTION(tsense_pwm1),
> + FUNCTION(tsense_pwm2),
> + FUNCTION(tsif1),
> + FUNCTION(tsif2),
> + FUNCTION(uim1),
> + FUNCTION(uim2),
> + FUNCTION(uim_batt),
> + FUNCTION(usb2phy_ac),
> + FUNCTION(usb_phy),
> + FUNCTION(vfr_1),
> + FUNCTION(vsense_trigger),
> + FUNCTION(wlan1_adc0),
> + FUNCTION(wlan1_adc1),
> + FUNCTION(wlan2_adc0),
> + FUNCTION(wlan2_adc1),
> + FUNCTION(wmss_reset),
> +};
> +
> +/*
> + * Every pin is maintained as a single group, and missing or non-existing pin
> + * would be maintained as dummy group to synchronize pin group index with
> + * pin descriptor registered with pinctrl core.
> + * Clients would not be able to request these dummy pin groups.
> + */
> +static const struct msm_pingroup sm8150_groups[] = {
> + [0] = PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _),
> + [1] = PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _),
> + [2] = PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _),
> + [3] = PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _),
> + [4] = PINGROUP(4, SOUTH, qup6, rgmii, _, _, _, _, _, _, _),
> + [5] = PINGROUP(5, SOUTH, qup6, rgmii, _, _, _, _, _, _, _),
> + [6] = PINGROUP(6, SOUTH, qup6, rgmii, qup_l6, _, _, _, _, _, _),
> + [7] = PINGROUP(7, SOUTH, qup6, rgmii, qup_l5, _, _, _, _, _, _),
> + [8] = PINGROUP(8, NORTH, mdp_vsync, _, _, _, _, _, _, _, _),
> + [9] = PINGROUP(9, NORTH, mdp_vsync, edp_lcd, qup10, _, _, _, _, _, _),
> + [10] = PINGROUP(10, NORTH, mdp_vsync, m_voc, edp_hot, qup10, _, _, _, _, _),
> + [11] = PINGROUP(11, NORTH, qup10, _, _, _, _, _, _, _, _),
> + [12] = PINGROUP(12, NORTH, qup10, _, _, _, _, _, _, _, _),
> + [13] = PINGROUP(13, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
> + [14] = PINGROUP(14, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
> + [15] = PINGROUP(15, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
> + [16] = PINGROUP(16, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
> + [17] = PINGROUP(17, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
> + [18] = PINGROUP(18, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
> + [19] = PINGROUP(19, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
> + [20] = PINGROUP(20, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
> + [21] = PINGROUP(21, EAST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _),
> + [22] = PINGROUP(22, EAST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _),
> + [23] = PINGROUP(23, EAST, cci_timer2, qup18, qdss, _, _, _, _, _, _),
> + [24] = PINGROUP(24, EAST, cci_timer3, cci_async, qup18, qdss, _, _, _, _, _),
> + [25] = PINGROUP(25, EAST, cci_timer4, cci_async, qup18, qdss, _, _, _, _, _),
> + [26] = PINGROUP(26, EAST, cci_async, qup18, qdss, _, _, _, _, _, _),
> + [27] = PINGROUP(27, EAST, qup15, _, qdss, _, _, _, _, _, _),
> + [28] = PINGROUP(28, EAST, qup15, qdss, _, _, _, _, _, _, _),
> + [29] = PINGROUP(29, EAST, qup15, qdss, _, _, _, _, _, _, _),
> + [30] = PINGROUP(30, EAST, qup15, qdss, _, _, _, _, _, _, _),
> + [31] = PINGROUP(31, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
> + [32] = PINGROUP(32, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
> + [33] = PINGROUP(33, NORTH, cci_i2c, qup_l5, qdss, _, _, _, _, _, _),
> + [34] = PINGROUP(34, NORTH, cci_i2c, qup_l6, _, _, _, _, _, _, _),
> + [35] = PINGROUP(35, NORTH, pci_e0, _, _, _, _, _, _, _, _),
> + [36] = PINGROUP(36, NORTH, pci_e0, _, _, _, _, _, _, _, _),
> + [37] = PINGROUP(37, NORTH, qup_l4, agera_pll, _, _, _, _, _, _, _),
> + [38] = PINGROUP(38, SOUTH, usb_phy, _, _, _, _, _, _, _, _),
> + [39] = PINGROUP(39, NORTH, qup9, qdss, _, _, _, _, _, _, _),
> + [40] = PINGROUP(40, NORTH, qup9, qdss, _, _, _, _, _, _, _),
> + [41] = PINGROUP(41, NORTH, qup9, qdss, _, _, _, _, _, _, _),
> + [42] = PINGROUP(42, NORTH, qup9, qdss, _, _, _, _, _, _, _),
> + [43] = PINGROUP(43, EAST, qup13, _, _, _, _, _, _, _, _),
> + [44] = PINGROUP(44, EAST, qup13, _, _, _, _, _, _, _, _),
> + [45] = PINGROUP(45, EAST, qup13, qdss_cti, _, _, _, _, _, _, _),
> + [46] = PINGROUP(46, EAST, qup13, qdss_cti, _, _, _, _, _, _, _),
> + [47] = PINGROUP(47, EAST, qup14, qdss, _, _, _, _, _, _, _),
> + [48] = PINGROUP(48, EAST, qup14, qdss, _, _, _, _, _, _, _),
> + [49] = PINGROUP(49, EAST, qup14, _, qdss_cti, _, _, _, _, _, _),
> + [50] = PINGROUP(50, EAST, qup14, qdss_cti, _, _, _, _, _, _, _),
> + [51] = PINGROUP(51, SOUTH, qup4, _, _, _, _, _, _, _, _),
> + [52] = PINGROUP(52, SOUTH, qup4, _, _, _, _, _, _, _, _),
> + [53] = PINGROUP(53, SOUTH, qup4, _, _, _, _, _, _, _, _),
> + [54] = PINGROUP(54, SOUTH, qup4, _, _, _, _, _, _, _, _),
> + [55] = PINGROUP(55, SOUTH, qup17, qup19, phase_flag, _, _, _, _, _, _),
> + [56] = PINGROUP(56, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
> + [57] = PINGROUP(57, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
> + [58] = PINGROUP(58, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
> + [59] = PINGROUP(59, SOUTH, rgmii, qup_l4, phase_flag, _, atest_char, _, _, _, _),
> + [60] = PINGROUP(60, SOUTH, _, nav_pps, nav_pps, atest_usb2, _, _, _, _, _),
> + [61] = PINGROUP(61, SOUTH, qlink_request, _, _, _, _, _, _, _, _),
> + [62] = PINGROUP(62, SOUTH, qlink_enable, _, _, _, _, _, _, _, _),
> + [63] = PINGROUP(63, SOUTH, wmss_reset, atest_usb23, _, _, _, _, _, _, _),
> + [64] = PINGROUP(64, SOUTH, _, phase_flag, _, _, _, _, _, _, _),
> + [65] = PINGROUP(65, SOUTH, _, _, _, _, _, _, _, _, _),
> + [66] = PINGROUP(66, SOUTH, _, _, _, _, _, _, _, _, _),
> + [67] = PINGROUP(67, SOUTH, _, _, _, _, _, _, _, _, _),
> + [68] = PINGROUP(68, SOUTH, _, pa_indicator, phase_flag, _, _, _, _, _, _),
> + [69] = PINGROUP(69, SOUTH, mss_lte, _, _, _, _, _, _, _, _),
> + [70] = PINGROUP(70, SOUTH, mss_lte, _, _, _, _, _, _, _, _),
> + [71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _),
> + [72] = PINGROUP(72, SOUTH, _, _, _, _, _, _, _, _, _),
> + [73] = PINGROUP(73, SOUTH, _, _, _, _, _, _, _, _, _),
> + [74] = PINGROUP(74, SOUTH, _, _, _, _, _, _, _, _, _),
> + [75] = PINGROUP(75, SOUTH, _, _, _, _, _, _, _, _, _),
> + [76] = PINGROUP(76, SOUTH, _, _, _, nav_pps, nav_pps, phase_flag, _, _, _),
> + [77] = PINGROUP(77, SOUTH, _, _, _, nav_pps, nav_pps, _, _, _, _),
> + [78] = PINGROUP(78, SOUTH, _, _, _, _, _, _, _, _, _),
> + [79] = PINGROUP(79, SOUTH, _, _, phase_flag, _, _, _, _, _, _),
> + [80] = PINGROUP(80, SOUTH, _, _, phase_flag, _, _, _, _, _, _),
> + [81] = PINGROUP(81, SOUTH, _, _, _, nav_pps, nav_pps, qup_l4, mdp_vsync, emac_pps, _),
> + [82] = PINGROUP(82, SOUTH, _, _, _, nav_pps, nav_pps, qup_l5, mdp_vsync, _, _),
> + [83] = PINGROUP(83, NORTH, qup12, qup16, _, qdss, _, _, _, _, _),
> + [84] = PINGROUP(84, NORTH, qup12, qup16, _, _, _, _, _, _, _),
> + [85] = PINGROUP(85, NORTH, qup12, qup16, _, _, _, _, _, _, _),
> + [86] = PINGROUP(86, NORTH, qup12, qup16, _, _, _, _, _, _, _),
> + [87] = PINGROUP(87, EAST, _, _, _, _, _, _, _, _, _),
> + [88] = PINGROUP(88, NORTH, tsif1, qup8, qspi_cs, tgu_ch3, _, _, _, _, _),
> + [89] = PINGROUP(89, NORTH, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, _),
> + [90] = PINGROUP(90, NORTH, tsif1, qup8, qspi1, sdc4, phase_flag, tgu_ch1, _, _, wlan1_adc1),
> + [91] = PINGROUP(91, NORTH, tsif1, qup8, qspi2, sdc4, vfr_1, phase_flag, tgu_ch2, _, _),
> + [92] = PINGROUP(92, NORTH, tsif2, qup11, qspi_clk, sdc4, phase_flag, _, wlan2_adc1, _, _),
> + [93] = PINGROUP(93, NORTH, tsif2, qup11, qspi3, sdc4, phase_flag, _, wlan2_adc0, _, _),
> + [94] = PINGROUP(94, NORTH, tsif2, qup11, qspi_cs, sdc4, phase_flag, _, _, _, _),
> + [95] = PINGROUP(95, NORTH, tsif2, qup11, sdc4, qup_l4, _, _, _, _, _),
> + [96] = PINGROUP(96, NORTH, tsif2, qup_l5, phase_flag, _, _, _, _, _, _),
> + [97] = PINGROUP(97, NORTH, sd_write, tsif1, qup_l6, _, _, _, _, _, _),
> + [98] = PINGROUP(98, SOUTH, qup7, ddr_bist, ddr_pxi3, _, _, _, _, _, _),
> + [99] = PINGROUP(99, SOUTH, qup7, ddr_bist, atest_usb13, ddr_pxi1, _, _, _, _, _),
> + [100] = PINGROUP(100, SOUTH, qup7, pll_bypassnl, atest_usb12, ddr_pxi1, _, _, _, _, _),
> + [101] = PINGROUP(101, SOUTH, qup7, pll_reset, ddr_pxi3, _, _, _, _, _, _),
> + [102] = PINGROUP(102, NORTH, pci_e1, _, _, _, _, _, _, _, _),
> + [103] = PINGROUP(103, NORTH, pci_e1, _, _, _, _, _, _, _, _),
> + [104] = PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _),
> + [105] = PINGROUP(105, WEST, uim2, _, _, _, _, _, _, _, _),
> + [106] = PINGROUP(106, WEST, uim2, _, _, _, _, _, _, _, _),
> + [107] = PINGROUP(107, WEST, uim2, _, _, _, _, _, _, _, _),
> + [108] = PINGROUP(108, WEST, uim2, _, _, _, _, _, _, _, _),
> + [109] = PINGROUP(109, WEST, uim1, _, _, _, _, _, _, _, _),
> + [110] = PINGROUP(110, WEST, uim1, _, _, _, _, _, _, _, _),
> + [111] = PINGROUP(111, WEST, uim1, _, _, _, _, _, _, _, _),
> + [112] = PINGROUP(112, WEST, uim1, _, _, _, _, _, _, _, _),
> + [113] = PINGROUP(113, WEST, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _),
> + [114] = PINGROUP(114, SOUTH, qup1, rgmii, phase_flag, _, _, _, _, _, _),
> + [115] = PINGROUP(115, SOUTH, qup1, rgmii, phase_flag, adsp_ext, _, _, _, _, _),
> + [116] = PINGROUP(116, SOUTH, qup1, rgmii, phase_flag, _, _, _, _, _, _),
> + [117] = PINGROUP(117, SOUTH, qup1, rgmii, phase_flag, _, qdss, _, _, _, _),
> + [118] = PINGROUP(118, SOUTH, rgmii, phase_flag, _, qdss, _, _, _, _, _),
> + [119] = PINGROUP(119, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
> + [120] = PINGROUP(120, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
> + [121] = PINGROUP(121, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
> + [122] = PINGROUP(122, SOUTH, qup5, rgmii, phase_flag, _, _, _, _, _, _),
> + [123] = PINGROUP(123, SOUTH, usb2phy_ac, qup_l6, atest_usb22, _, _, _, _, _, _),
> + [124] = PINGROUP(124, SOUTH, emac_phy, _, _, _, _, _, _, _, _),
> + [125] = PINGROUP(125, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
> + [126] = PINGROUP(126, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
> + [127] = PINGROUP(127, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
> + [128] = PINGROUP(128, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
> + [129] = PINGROUP(129, SOUTH, sec_mi2s, qup2, jitter_bist, atest_usb21, _, _, _, _, _),
> + [130] = PINGROUP(130, SOUTH, sec_mi2s, pll_bist, atest_usb20, atest_char0, _, _, _, _, _),
> + [131] = PINGROUP(131, SOUTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
> + [132] = PINGROUP(132, SOUTH, ter_mi2s, _, qdss, _, _, _, _, _, _),
> + [133] = PINGROUP(133, SOUTH, ter_mi2s, qdss, atest_char1, _, _, _, _, _, _),
> + [134] = PINGROUP(134, SOUTH, ter_mi2s, qdss, atest_char2, _, _, _, _, _, _),
> + [135] = PINGROUP(135, SOUTH, ter_mi2s, atest_char3, _, _, _, _, _, _, _),
> + [136] = PINGROUP(136, SOUTH, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _),
> + [137] = PINGROUP(137, SOUTH, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _),
> + [138] = PINGROUP(138, SOUTH, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _),
> + [139] = PINGROUP(139, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
> + [140] = PINGROUP(140, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
> + [141] = PINGROUP(141, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
> + [142] = PINGROUP(142, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
> + [143] = PINGROUP(143, SOUTH, pri_mi2s, _, _, _, _, _, _, _, _),
> + [144] = PINGROUP(144, SOUTH, pri_mi2s, qup3, phase_flag, _, ddr_pxi0, _, _, _, _),
> + [145] = PINGROUP(145, SOUTH, pri_mi2s_ws, qup3, phase_flag, ddr_bist, _, vsense_trigger, atest_usb1, ddr_pxi0, _),
> + [146] = PINGROUP(146, SOUTH, pri_mi2s, qup3, ddr_bist, atest_usb11, ddr_pxi2, _, _, _, _),
> + [147] = PINGROUP(147, SOUTH, pri_mi2s, qup3, dbg_out, atest_usb10, ddr_pxi2, _, _, _, _),
> + [148] = PINGROUP(148, SOUTH, spkr_i2s, audio_ref, _, _, _, _, _, _, _),
> + [149] = PINGROUP(149, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
> + [150] = PINGROUP(150, SOUTH, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _),
> + [151] = PINGROUP(151, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
> + [152] = PINGROUP(152, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
> + [153] = PINGROUP(153, SOUTH, btfm_slimbus, _, _, _, _, _, _, _, _),
> + [154] = PINGROUP(154, SOUTH, btfm_slimbus, _, _, _, _, _, _, _, _),
> + [155] = PINGROUP(155, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
> + [156] = PINGROUP(156, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
> + [157] = PINGROUP(157, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
> + [158] = PINGROUP(158, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
> + [159] = PINGROUP(159, WEST, hs1_mi2s, cri_trng0, _, _, _, _, _, _, _),
> + [160] = PINGROUP(160, WEST, hs2_mi2s, cri_trng1, _, _, _, _, _, _, _),
> + [161] = PINGROUP(161, WEST, hs2_mi2s, cri_trng, _, _, _, _, _, _, _),
> + [162] = PINGROUP(162, WEST, hs2_mi2s, sp_cmu, _, _, _, _, _, _, _),
> + [163] = PINGROUP(163, WEST, hs2_mi2s, prng_rosc, _, _, _, _, _, _, _),
> + [164] = PINGROUP(164, WEST, hs2_mi2s, _, _, _, _, _, _, _, _),
> + [165] = PINGROUP(165, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
> + [166] = PINGROUP(166, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
> + [167] = PINGROUP(167, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
> + [168] = PINGROUP(168, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
> + [169] = PINGROUP(169, NORTH, _, _, _, _, _, _, _, _, _),
> + [170] = PINGROUP(170, NORTH, _, _, _, _, _, _, _, _, _),
> + [171] = PINGROUP(171, NORTH, _, _, _, _, _, _, _, _, _),
> + [172] = PINGROUP(172, NORTH, _, _, _, _, _, _, _, _, _),
> + [173] = PINGROUP(173, NORTH, _, _, _, _, _, _, _, _, _),
> + [174] = PINGROUP(174, NORTH, _, _, _, _, _, _, _, _, _),
> + [175] = UFS_RESET(ufs_reset, 0xB6000),
> + [176] = SDC_QDSD_PINGROUP(sdc2_clk, 0xB2000, 14, 6),
> + [177] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xB2000, 11, 3),
> + [178] = SDC_QDSD_PINGROUP(sdc2_data, 0xB2000, 9, 0),
> +};
> +
> +static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
> + .pins = sm8150_pins,
> + .npins = ARRAY_SIZE(sm8150_pins),
> + .functions = sm8150_functions,
> + .nfunctions = ARRAY_SIZE(sm8150_functions),
> + .groups = sm8150_groups,
> + .ngroups = ARRAY_SIZE(sm8150_groups),
> + .ngpios = 176,
> + .tiles = sm8150_tiles,
> + .ntiles = ARRAY_SIZE(sm8150_tiles),
> +};
> +
> +static int sm8150_pinctrl_probe(struct platform_device *pdev)
> +{
> + return msm_pinctrl_probe(pdev, &sm8150_pinctrl);
> +}
> +
> +static const struct of_device_id sm8150_pinctrl_of_match[] = {
> + { .compatible = "qcom,sm8150-pinctrl", },
> + { },
> +};
> +
> +static struct platform_driver sm8150_pinctrl_driver = {
> + .driver = {
> + .name = "sm8150-pinctrl",
> + .of_match_table = sm8150_pinctrl_of_match,
> + },
> + .probe = sm8150_pinctrl_probe,
> + .remove = msm_pinctrl_remove,
> +};
> +
> +static int __init sm8150_pinctrl_init(void)
> +{
> + return platform_driver_register(&sm8150_pinctrl_driver);
> +}
> +arch_initcall(sm8150_pinctrl_init);
> +
> +static void __exit sm8150_pinctrl_exit(void)
> +{
> + platform_driver_unregister(&sm8150_pinctrl_driver);
> +}
> +module_exit(sm8150_pinctrl_exit);
> +
> +MODULE_DESCRIPTION("QTI sm8150 pinctrl driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DEVICE_TABLE(of, sm8150_pinctrl_of_match);
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH v3] pinctrl: qcom: Add irq_enable callback for msm gpio
From: Linus Walleij @ 2019-07-03 8:26 UTC (permalink / raw)
To: Neeraj Upadhyay
Cc: Bjorn Andersson, Stephen Boyd, Timur Tabi, MSM,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org,
Srinivas Ramana
In-Reply-To: <1561472086-23360-1-git-send-email-neeraju@codeaurora.org>
On Tue, Jun 25, 2019 at 4:14 PM Neeraj Upadhyay <neeraju@codeaurora.org> wrote:
> From: Srinivas Ramana <sramana@codeaurora.org>
>
> Introduce the irq_enable callback which will be same as irq_unmask
> except that it will also clear the status bit before unmask.
>
> This will help in clearing any erroneous interrupts that would
> have got latched when the interrupt is not in use.
>
> There may be devices like UART which can use the same gpio line
> for data rx as well as a wakeup gpio when in suspend. The data that
> was flowing on the line may latch the interrupt and when we enable
> the interrupt before going to suspend, this would trigger the
> unexpected interrupt. This change helps clearing the interrupt
> so that these unexpected interrupts gets cleared.
>
> Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
> Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
> ---
>
> Changes since v2:
> - Renamed function to msm_gpio_irq_clear_unmask()
Patch applied, unless Bjorn complains!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2 0/8] pinctrl: aspeed: Preparation for AST2600
From: Linus Walleij @ 2019-07-03 8:40 UTC (permalink / raw)
To: Andrew Jeffery
Cc: open list:GPIO SUBSYSTEM, Ryan Chen, Rob Herring, Mark Rutland,
Joel Stanley, linux-aspeed, OpenBMC Maillist,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-kernel@vger.kernel.org
In-Reply-To: <20190628023838.15426-1-andrew@aj.id.au>
Hi Andrew,
On Fri, Jun 28, 2019 at 4:39 AM Andrew Jeffery <andrew@aj.id.au> wrote:
>
> Hello!
>
> The ASPEED AST2600 is in the pipeline, and we have enough information to start
> preparing to upstream support for it. This series lays some ground work;
> splitting the bindings and dicing the implementation up a little further to
> facilitate differences between the 2600 and previous SoC generations.
>
> v2 addresses Rob's comments on the bindings conversion patches. v1 can be found
> here:
I have applied this series, I had to strip some changes of the header
because it was based on some SPDX cleanups upstream but no
big deal I think. Check the result please.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 39/39] docs: gpio: add sysfs interface to the admin-guide
From: Linus Walleij @ 2019-07-03 8:44 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Linux Doc Mailing List, Mauro Carvalho Chehab,
linux-kernel@vger.kernel.org, Jonathan Corbet,
Bartosz Golaszewski, Rafael J. Wysocki, Len Brown, Harry Wei,
Alex Shi, open list:GPIO SUBSYSTEM, ACPI Devel Maling List
In-Reply-To: <1ecff14ec37c0c434f003d93c4b86b1cd3dac834.1561724493.git.mchehab+samsung@kernel.org>
On Fri, Jun 28, 2019 at 2:30 PM Mauro Carvalho Chehab
<mchehab+samsung@kernel.org> wrote:
> While this is stated as obsoleted, the sysfs interface described
> there is still valid, and belongs to the admin-guide.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This doesn't apply to my tree because of dependencies in the
index so I guess it's best if you merge it:
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] gpio: max77650: add MODULE_ALIAS()
From: Bartosz Golaszewski @ 2019-07-03 8:46 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-kernel, linux-gpio, Bartosz Golaszewski
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Define a MODULE_ALIAS() in the gpio sub-driver for max77650 so that
the appropriate module gets loaded together with the core mfd driver.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
drivers/gpio/gpio-max77650.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-max77650.c b/drivers/gpio/gpio-max77650.c
index 3f03f4e8956c..3075f2513c6f 100644
--- a/drivers/gpio/gpio-max77650.c
+++ b/drivers/gpio/gpio-max77650.c
@@ -188,3 +188,4 @@ module_platform_driver(max77650_gpio_driver);
MODULE_DESCRIPTION("MAXIM 77650/77651 GPIO driver");
MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:max77650-gpio");
--
2.21.0
^ permalink raw reply related
* Re: [PATCH 1/4 v1] gpio: Add support for hierarchical IRQ domains
From: Brian Masney @ 2019-07-03 9:22 UTC (permalink / raw)
To: Linus Walleij
Cc: linux-gpio, Bartosz Golaszewski, Thomas Gleixner, Marc Zyngier,
Lina Iyer, Jon Hunter, Sowjanya Komatineni, Bitan Biswas,
linux-tegra, David Daney, Masahiro Yamada, Thierry Reding
In-Reply-To: <20190624132531.6184-1-linus.walleij@linaro.org>
Hi Linus,
On Mon, Jun 24, 2019 at 03:25:28PM +0200, Linus Walleij wrote:
> static int gpiochip_to_irq(struct gpio_chip *chip, unsigned offset)
> {
> + struct irq_domain *domain = chip->irq.domain;
> +
> if (!gpiochip_irqchip_irq_valid(chip, offset))
> return -ENXIO;
>
> - return irq_create_mapping(chip->irq.domain, offset);
> + if (irq_domain_is_hierarchy(domain)) {
> + struct irq_fwspec spec;
> +
> + spec.fwnode = domain->fwnode;
> + spec.param_count = 2;
> + spec.param[0] = offset;
> + spec.param[1] = IRQ_TYPE_NONE;
> +
> + return irq_create_fwspec_mapping(&spec);
> + }
spmi-gpio's to_irq() needs to add one to the offset:
static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
{
struct pmic_gpio_state *state = gpiochip_get_data(chip);
struct irq_fwspec fwspec;
fwspec.fwnode = state->fwnode;
fwspec.param_count = 2;
fwspec.param[0] = pin + PMIC_GPIO_PHYSICAL_OFFSET;
/*
* Set the type to a safe value temporarily. This will be overwritten
* later with the proper value by irq_set_type.
*/
fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
return irq_create_fwspec_mapping(&fwspec);
}
ssbi-gpio will have the same problem as well.
What do you think about adding a new field to the struct gpio_irq_chip
inside the CONFIG_IRQ_DOMAIN_HIERARCHY ifdef called something like
to_irq_offset? (I'm bad at naming things.)
Also, instead of hardcoding IRQ_TYPE_NONE, what do you think about using
the default_type field that's available?
Brian
^ permalink raw reply
* Re: gpio desc flags being lost
From: Chris Packham @ 2019-07-03 9:29 UTC (permalink / raw)
To: Linus Walleij
Cc: Bartosz Golaszewski, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <CACRpkdZD7x1eeatXRTtU5k7Zoj5tfG8V98SjaO=xubwaa9teTQ@mail.gmail.com>
On 3/07/19 6:28 PM, Linus Walleij wrote:
> On Wed, Jul 3, 2019 at 7:35 AM Chris Packham
> <Chris.Packham@alliedtelesis.co.nz> wrote:
>
>> Doing a bit of debugging so far I see that after startup the desc->flags
>> for those gpios is 0. But for the hogged ones it should be 0x800 (or 0x801).
>
> Yeah that is wrong.
>
>> I'll do some proper bisecting tomorrow, but figured you might want to
>> know sooner rather than later.
>
> Thanks, I have another critical GPIO fix queued so would be great if we
> can fix this too before v5.2 is released.
Bit of an update. v4.19.54 works, v5.1.15 is broken. I'll keep bisecting
between those tomorrow.
^ permalink raw reply
* [PATCH] gpio: pl061: drop duplicate printing of device name
From: Enrico Weigelt, metux IT consult @ 2019-07-03 9:42 UTC (permalink / raw)
To: linux-kernel; +Cc: linus.walleij, bgolaszewski, linux-gpio
From: Enrico Weigelt <info@metux.net>
The dev_info() call already prints the device name, so there's
no need to explicitly include it in the message for second time.
Signed-off-by: Enrico Weigelt <info@metux.net>
---
drivers/gpio/gpio-pl061.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index 84af248..83a44dd 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -349,7 +349,7 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
return ret;
amba_set_drvdata(adev, pl061);
- dev_info(dev, "PL061 GPIO chip %s registered\n", dev_name(dev));
+ dev_info(dev, "PL061 GPIO chip registered\n");
return 0;
}
--
1.9.1
^ permalink raw reply related
* Re: [PATCH v1 1/2] pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
From: Enrico Weigelt, metux IT consult @ 2019-07-03 9:44 UTC (permalink / raw)
To: Andy Shevchenko, Mika Westerberg, Linus Walleij, linux-gpio,
Hans de Goede
In-Reply-To: <20190703003018.75186-1-andriy.shevchenko@linux.intel.com>
On 03.07.19 02:30, Andy Shevchenko wrote:
> By the fact byt_get_gpio_mux() returns a value of mux settings as
> it is represented in hardware. Use defined macro instead of magic numbers
> to clarify this.
Reviewed-By: Enrico Weigelt <info@metux.net>
--
Enrico Weigelt, metux IT consult
Free software and Linux embedded engineering
info@metux.net -- +49-151-27565287
^ permalink raw reply
* Re: [PATCH] gpio/spi: Fix spi-gpio regression on active high CS
From: Mark Brown @ 2019-07-03 10:58 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-spi, linux-gpio, Andrey Smirnov
In-Reply-To: <20190702193959.11150-1-linus.walleij@linaro.org>
[-- Attachment #1: Type: text/plain, Size: 459 bytes --]
On Tue, Jul 02, 2019 at 09:39:59PM +0200, Linus Walleij wrote:
> Mark: I will apply this to the GPIO tree, so I think it is
> safe for you to drop my revert of Andrey's patch once this
> hits mainline. I will try to expediate it, I feel a bit
> responsible.
No worries, thanks for getting to the bottom of this! Could you
send a revert to me after the merge window if I forget to drop
the patch? I'll hold off on sending the current fix to Linus for
now.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH v1 1/2] pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
From: Mika Westerberg @ 2019-07-03 11:00 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: Linus Walleij, linux-gpio, Hans de Goede
In-Reply-To: <20190703003018.75186-1-andriy.shevchenko@linux.intel.com>
On Wed, Jul 03, 2019 at 03:30:17AM +0300, Andy Shevchenko wrote:
> By the fact byt_get_gpio_mux() returns a value of mux settings as
> it is represented in hardware. Use defined macro instead of magic numbers
> to clarify this.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
^ permalink raw reply
* Re: [PATCH v1 2/2] pinctrl: baytrail: Re-use data structures from pinctrl-intel.h
From: Mika Westerberg @ 2019-07-03 11:02 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: Linus Walleij, linux-gpio, Hans de Goede
In-Reply-To: <20190703003018.75186-2-andriy.shevchenko@linux.intel.com>
On Wed, Jul 03, 2019 at 03:30:18AM +0300, Andy Shevchenko wrote:
> We have some data structures duplicated across the drivers.
> Let's deduplicate them by using ones that being provided by
> pinctrl-intel.h.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/pinctrl/intel/pinctrl-baytrail.c | 299 +++++------------------
> 1 file changed, 60 insertions(+), 239 deletions(-)
Nice cleanup!
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
^ permalink raw reply
* Re: [RFC/RFT v3 04/14] clk: meson: eeclk: add setup callback
From: Neil Armstrong @ 2019-07-03 11:45 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: jbrunet, khilman, linux-arm-kernel, linux-amlogic, linux-kernel,
linux-clk, linux-gpio, amergnat
In-Reply-To: <CAFBinCA1gUUbEj=++1rGcFQ1RdyxSheofAo=TKw3-UaenFAcug@mail.gmail.com>
On 03/07/2019 01:16, Martin Blumenstingl wrote:
> +Cc Alexandre Mergnat
>
> On Mon, Jul 1, 2019 at 11:13 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Add a setup() callback in the eeclk structure, to call an optional
>> call() function at end of eeclk probe to setup clocks.
>>
>> It's used for the G12A clock controller to setup the CPU clock notifiers.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> this will probably work fine, but I want do double check first
>
> are we planning to get rid of meson-eeclk (mid-term)?
AFAIK no, but maybe I'm not aware of it !
Neil
> Alex has some patches to get rid of all these IN_PREFIX logic.
> I'm asking because if we want to get rid of meson-eeclk it may be the
> time to do so now to have less logic to migrate later on
>
>
> Martin
>
^ permalink raw reply
* Re: [RFC/RFT v3 07/14] clk: meson: g12a: add notifiers to handle cpu clock change
From: Neil Armstrong @ 2019-07-03 11:50 UTC (permalink / raw)
To: Martin Blumenstingl, sboyd
Cc: jbrunet, khilman, linux-arm-kernel, linux-amlogic, linux-kernel,
linux-clk, linux-gpio
In-Reply-To: <CAFBinCAnKeGYkyCmEMugWuQaSxgBp4DqtHN3b0rLJY6jwOF0QA@mail.gmail.com>
On 03/07/2019 01:28, Martin Blumenstingl wrote:
> Hi Stephen, Hi Neil,
>
> On Mon, Jul 1, 2019 at 11:13 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> In order to implement clock switching for the CLKID_CPU_CLK and
>> CLKID_CPUB_CLK, notifiers are added on specific points of the
>> clock tree :
>>
>> cpu_clk / cpub_clk
>> | \- cpu_clk_dyn
>> | | \- cpu_clk_premux0
>> | | |- cpu_clk_postmux0
>> | | | |- cpu_clk_dyn0_div
>> | | | \- xtal/fclk_div2/fclk_div3
>> | | \- xtal/fclk_div2/fclk_div3
>> | \- cpu_clk_premux1
>> | |- cpu_clk_postmux1
>> | | |- cpu_clk_dyn1_div
>> | | \- xtal/fclk_div2/fclk_div3
>> | \- xtal/fclk_div2/fclk_div3
>> \ sys_pll / sys1_pll
>>
>> This for each cluster, a single one for G12A, two for G12B.
>>
>> Each cpu_clk_premux1 tree is marked as read-only and CLK_SET_RATE_NO_REPARENT,
>> to be used as "parking" clock in a safe clock frequency.
> it seems that this is one case where the "coordinated clocks" feature
> would come handy: [0]
We could still migrate over it later on.
> Stephen, do you know if those patches stopped in March or if there's
> still some ongoing effort to get them ready?
>
> [...]
>> -/*
>> - * Internal sys pll emulation configuration parameters
>> - */
>> -static const struct reg_sequence g12a_sys_init_regs[] = {
>> - { .reg = HHI_SYS_PLL_CNTL1, .def = 0x00000000 },
>> - { .reg = HHI_SYS_PLL_CNTL2, .def = 0x00000000 },
>> - { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
>> - { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
>> - { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
>> - { .reg = HHI_SYS_PLL_CNTL6, .def = 0x56540000 },
>> +static const struct pll_mult_range g12a_sys_pll_mult_range = {
>> + .min = 128,
>> + .max = 250,
>> };
>>
>> static struct clk_regmap g12a_sys_pll_dco = {
>> @@ -124,14 +118,15 @@ static struct clk_regmap g12a_sys_pll_dco = {
>> .shift = 29,
>> .width = 1,
>> },
>> - .init_regs = g12a_sys_init_regs,
>> - .init_count = ARRAY_SIZE(g12a_sys_init_regs),
>> + .range = &g12a_sys_pll_mult_range,
> Neil, I believe that this should be a separate patch with a
> description which explains why we don't need the "init regs" anymore
Sure
>
>> },
>> .hw.init = &(struct clk_init_data){
>> .name = "sys_pll_dco",
>> - .ops = &meson_clk_pll_ro_ops,
>> + .ops = &meson_clk_pll_ops,
>> .parent_names = (const char *[]){ IN_PREFIX "xtal" },
>> .num_parents = 1,
>> + /* This clock feeds the CPU, avoid disabling it */
>> + .flags = CLK_IS_CRITICAL,
> maybe we should have a separate patch for making the CPU clock tree
> mutable as well
Indeed
>
> [...]
>> +/* This divider uses bit 26 to take change in account */
>> +static int g12b_cpub_clk_mux0_div_set_rate(struct clk_hw *hw,
>> + unsigned long rate,
>> + unsigned long parent_rate)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
>> + unsigned int val;
>> + int ret;
>> +
>> + ret = divider_get_val(rate, parent_rate, div->table, div->width,
>> + div->flags);
>> + if (ret < 0)
>> + return ret;
>> +
>> + val = (unsigned int)ret << div->shift;
>> +
>> + regmap_update_bits(clk->map, HHI_SYS_CPUB_CLK_CNTL,
>> + SYS_CPU_DYN_ENABLE, SYS_CPU_DYN_ENABLE);
>> +
>> + return regmap_update_bits(clk->map, div->offset,
>> + clk_div_mask(div->width) << div->shift |
>> + SYS_CPU_DYN_ENABLE, val);
>> +};
> the public S922X datasheet doesn't mention bit 26
> do I understand the semantics correctly?:
> - set SYS_CPU_DYN_ENABLE
> - update the divider
> - unset SYS_CPU_DYN_ENABLE
Exact, it's how Amlogic uses it, seems the HW takes the divider value
only on the "falling edge" of this bit !
>
> too bad it's not a gate which we could model with
> CLK_SET_RATE_GATE/CLK_SET_RATE_UNGATE
Yep, but it only works when I write the new divider value *and* I remove the bit.
It must be a glitch-free divider mechanism.
Neil
>
>
> Martin
>
> [0] https://patchwork.kernel.org/patch/10838949/
>
^ permalink raw reply
* Re: [RFC/RFT v3 09/14] arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi
From: Neil Armstrong @ 2019-07-03 11:51 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: jbrunet, khilman, linux-arm-kernel, linux-amlogic, linux-kernel,
linux-clk, linux-gpio
In-Reply-To: <CAFBinCA537EV9kzz+5syaF1Q-stTJ4no+NBdcYD3QL-FJSoWfQ@mail.gmail.com>
On 03/07/2019 01:54, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Jul 1, 2019 at 11:13 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> To simplify the representation of differences betweem the G12A and G12B
>> SoCs, move the common nodes into a meson-g12-common.dtsi file and
>> express the CPU nodes and differences in meson-g12a.dtsi and meson-g12b.dtsi.
>>
>> This separation will help for DVFS and future Amlogic SM1 Family support.
>>
>> The sd_emmc_a quirk is added in the g12a/g12b since since it's already
>> known the sd_emmc_a controller is fixed in the next SM1 SoC family.
> too bad they named the upcoming SoC family SM1
Yeah weird naming, but seems SM1 is the new "AI" oriented SoC family
>
> does it make sense to name this file "meson-g12a-g12b-sm1-common.dtsi" instead?
> do you know whether there will be a successor to G12B and what it's
> code-name will be?
meson-g12a-g12b-sm1-common seems a bit long to me...
We don't have naming of the future SoCs, since SM1 is only available on
prototypes yet.
Neil
>
>
> Martin
>
^ permalink raw reply
* Re: [RFC/RFT v3 11/14] arm64: dts: meson-g12a: add cpus OPP table
From: Neil Armstrong @ 2019-07-03 11:53 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: jbrunet, khilman, linux-arm-kernel, linux-amlogic, linux-kernel,
linux-clk, linux-gpio
In-Reply-To: <CAFBinCBg57gh1x3CKs-YrCvTD0WR2s5zVGWtycb=RGqMiQ-VgA@mail.gmail.com>
On 03/07/2019 01:47, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Jul 1, 2019 at 11:13 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Add the OPP table taken from the vendor u200 and u211 DTS.
>>
>> The Amlogic G12A SoC seems to available in 3 types :
>> - low-speed: up to 1,8GHz
>> - mid-speed: up to 1,908GHz
>> - high-speed: up to 2.1GHz
>>
>> And the S905X2 opp voltages are slightly higher than the S905D2
>> OPP voltages for the low-speed table.
>>
>> This adds the conservative OPP table with the S905X2 higher voltages
>> and the maximum low-speed OPP frequency.
> have you considered all three as separate voltage tables?
> you're other patches are assigning the OPP table to the CPU in the
> board.dts anyways, so it's easy to use different OPP tables for
> different boards
We can't assume the board and the CPU type :-/
Kevin told me about cpufreq policy, where we could add a policy reading the
eFUSE and changing the max frequency, then we could add the whole OPP table.
Neil
>
^ permalink raw reply
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