* Re: [PATCH] platform/x86: pcengines-apu2 needs gpiolib
From: Enrico Weigelt, metux IT consult @ 2019-07-13 14:36 UTC (permalink / raw)
To: Arnd Bergmann, Darren Hart, Andy Shevchenko
Cc: linux-gpio, linus.walleij, bgolaszewski, platform-driver-x86,
Andy Shevchenko, Enrico Weigelt, metux IT consult, Randy Dunlap,
Rafael J. Wysocki, linux-kernel
In-Reply-To: <20190712085437.4007720-1-arnd@arndb.de>
On 12.07.19 10:54, Arnd Bergmann wrote:
Hi,
> diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
> index e869a5c760b6..cf48b9068843 100644
> --- a/drivers/platform/x86/Kconfig
> +++ b/drivers/platform/x86/Kconfig
> @@ -1324,8 +1324,8 @@ config PCENGINES_APU2
> tristate "PC Engines APUv2/3 front button and LEDs driver"
> depends on INPUT && INPUT_KEYBOARD
> depends on LEDS_CLASS
> - select GPIO_AMD_FCH
> - select KEYBOARD_GPIO_POLLED
> + select GPIO_AMD_FCH if GPIOLIB
> + select KEYBOARD_GPIO_POLLED if GPIOLIB
> select LEDS_GPIO
> help
> This driver provides support for the front button and LEDs on
That might compile but the driver won't work, if KEYBOARD_GPIO_POLLED
or GPIO_AMD_FCH isn't there.
--mtx
--
Enrico Weigelt, metux IT consult
Free software and Linux embedded engineering
info@metux.net -- +49-151-27565287
^ permalink raw reply
* Re: [PATCH] platform/x86: pcengines-apu2 needs gpiolib
From: Arnd Bergmann @ 2019-07-13 15:34 UTC (permalink / raw)
To: Enrico Weigelt, metux IT consult
Cc: Darren Hart, Andy Shevchenko, open list:GPIO SUBSYSTEM,
Linus Walleij, Bartosz Golaszewski, Platform Driver,
Andy Shevchenko, Enrico Weigelt, metux IT consult, Randy Dunlap,
Rafael J. Wysocki, Linux Kernel Mailing List
In-Reply-To: <fb36b507-e637-e4d9-fdd4-2947eb7faf14@metux.net>
On Sat, Jul 13, 2019 at 4:36 PM Enrico Weigelt, metux IT consult
<lkml@metux.net> wrote:
> On 12.07.19 10:54, Arnd Bergmann wrote:
> > diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
> > index e869a5c760b6..cf48b9068843 100644
> > --- a/drivers/platform/x86/Kconfig
> > +++ b/drivers/platform/x86/Kconfig
> > @@ -1324,8 +1324,8 @@ config PCENGINES_APU2
> > tristate "PC Engines APUv2/3 front button and LEDs driver"
> > depends on INPUT && INPUT_KEYBOARD
> > depends on LEDS_CLASS
> > - select GPIO_AMD_FCH
> > - select KEYBOARD_GPIO_POLLED
> > + select GPIO_AMD_FCH if GPIOLIB
> > + select KEYBOARD_GPIO_POLLED if GPIOLIB
> > select LEDS_GPIO
> > help
> > This driver provides support for the front button and LEDs on
>
> That might compile but the driver won't work, if KEYBOARD_GPIO_POLLED
> or GPIO_AMD_FCH isn't there.
Right, I agree it's a bit inconsistent. A better way would probably
be to turn all of the 'select' statements into 'depends on' here, or
possibly just remove them and document in the help text what others
are required.
Generally using 'select' in order to save users from thinking causes
more problems than it helps, as the build problems in this driver
have already illustrated.
Arnd
^ permalink raw reply
* Re: [GIT PULL] Pin control bulk changes for v5.3
From: pr-tracker-bot @ 2019-07-13 22:50 UTC (permalink / raw)
To: Linus Walleij; +Cc: Linus Torvalds, linux-kernel, open list:GPIO SUBSYSTEM
In-Reply-To: <CACRpkdaaO14KOdsPBqjyx+78ohdGJ9Z0YrF+GcG7-geO1w1R8A@mail.gmail.com>
The pull request you sent on Fri, 12 Jul 2019 11:10:34 +0200:
> git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git tags/pinctrl-v5.3-1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/43c95d3694cc448fdf50bd53b7ff3a5bb4655883
Thank you!
--
Deet-doot-dot, I am a bot.
https://korg.wiki.kernel.org/userdoc/prtracker
^ permalink raw reply
* Ingenic pinctrl patchs.
From: Zhou Yanjie @ 2019-07-14 3:53 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-gpio, devicetree, paul.burton, linus.walleij,
robh+dt, mark.rutland
Add support for Ingenic JZ4760, JZ4760B, X1000, X1000E and X1500.
^ permalink raw reply
* [PATCH 1/6] dt-bindings: pinctrl: Add JZ4760 and JZ4760B bindings.
From: Zhou Yanjie @ 2019-07-14 3:53 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-gpio, devicetree, paul.burton, linus.walleij,
robh+dt, mark.rutland
In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com>
Add the pinctrl bindings for the JZ4760 Soc and
the JZ4760B Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
index af20b0e..a80ff68 100644
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
@@ -11,8 +11,8 @@ naming scheme "PxN" where x is a character identifying the GPIO port with
which the pin is associated and N is an integer from 0 to 31 identifying the
pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to
-PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a
-total of 192 pins.
+PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 contains 6
+GPIO ports, PA to PF, for a total of 192 pins.
Required properties:
@@ -21,6 +21,8 @@ Required properties:
- compatible: One of:
- "ingenic,jz4740-pinctrl"
- "ingenic,jz4725b-pinctrl"
+ - "ingenic,jz4760-pinctrl"
+ - "ingenic,jz4760b-pinctrl"
- "ingenic,jz4770-pinctrl"
- "ingenic,jz4780-pinctrl"
- reg: Address range of the pinctrl registers.
@@ -31,6 +33,7 @@ Required properties for sub-nodes (GPIO chips):
- compatible: Must contain one of:
- "ingenic,jz4740-gpio"
+ - "ingenic,jz4760-gpio"
- "ingenic,jz4770-gpio"
- "ingenic,jz4780-gpio"
- reg: The GPIO bank number.
--
2.7.4
^ permalink raw reply related
* [PATCH 2/6] pinctrl: Ingenic: Add pinctrl driver for JZ4760 and JZ4760B.
From: Zhou Yanjie @ 2019-07-14 3:53 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-gpio, devicetree, paul.burton, linus.walleij,
robh+dt, mark.rutland
In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com>
Add support for probing the pinctrl-ingenic driver on the
JZ4760 Soc and the JZ4760B Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/pinctrl/pinctrl-ingenic.c | 336 ++++++++++++++++++++++++++++++++++----
1 file changed, 305 insertions(+), 31 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index c8ef3b9..ec61b083 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -35,11 +35,11 @@
#define JZ4740_GPIO_TRIG 0x70
#define JZ4740_GPIO_FLAG 0x80
-#define JZ4770_GPIO_INT 0x10
-#define JZ4770_GPIO_PAT1 0x30
-#define JZ4770_GPIO_PAT0 0x40
-#define JZ4770_GPIO_FLAG 0x50
-#define JZ4770_GPIO_PEN 0x70
+#define JZ4760_GPIO_INT 0x10
+#define JZ4760_GPIO_PAT1 0x30
+#define JZ4760_GPIO_PAT0 0x40
+#define JZ4760_GPIO_FLAG 0x50
+#define JZ4760_GPIO_PEN 0x70
#define REG_SET(x) ((x) + 0x4)
#define REG_CLEAR(x) ((x) + 0x8)
@@ -49,6 +49,8 @@
enum jz_version {
ID_JZ4740,
ID_JZ4725B,
+ ID_JZ4760,
+ ID_JZ4760B,
ID_JZ4770,
ID_JZ4780,
};
@@ -338,6 +340,269 @@ static const struct ingenic_chip_info jz4725b_chip_info = {
.pull_downs = jz4740_pull_downs,
};
+static const u32 jz4760_pull_ups[6] = {
+ 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f,
+};
+
+static const u32 jz4760_pull_downs[6] = {
+ 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
+};
+
+static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
+static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
+static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
+static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
+static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
+static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
+static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
+static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
+static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
+static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
+static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
+static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
+static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
+static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
+static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
+static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
+static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
+static int jz4760_nemc_8bit_data_pins[] = {
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+};
+static int jz4760_nemc_16bit_data_pins[] = {
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+};
+static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
+static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
+static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
+static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
+static int jz4760_nemc_wait_pins[] = { 0x1b, };
+static int jz4760_nemc_cs1_pins[] = { 0x15, };
+static int jz4760_nemc_cs2_pins[] = { 0x16, };
+static int jz4760_nemc_cs3_pins[] = { 0x17, };
+static int jz4760_nemc_cs4_pins[] = { 0x18, };
+static int jz4760_nemc_cs5_pins[] = { 0x19, };
+static int jz4760_nemc_cs6_pins[] = { 0x1a, };
+static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
+static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
+static int jz4760_cim_pins[] = {
+ 0x26, 0x27, 0x28, 0x29,
+ 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+};
+static int jz4760_lcd_24bit_pins[] = {
+ 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
+ 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
+ 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
+ 0x58, 0x59, 0x5a, 0x5b,
+};
+static int jz4760_pwm_pwm0_pins[] = { 0x80, };
+static int jz4760_pwm_pwm1_pins[] = { 0x81, };
+static int jz4760_pwm_pwm2_pins[] = { 0x82, };
+static int jz4760_pwm_pwm3_pins[] = { 0x83, };
+static int jz4760_pwm_pwm4_pins[] = { 0x84, };
+static int jz4760_pwm_pwm5_pins[] = { 0x85, };
+static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
+static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
+
+static int jz4760_uart0_data_funcs[] = { 0, 0, };
+static int jz4760_uart0_hwflow_funcs[] = { 0, 0, };
+static int jz4760_uart1_data_funcs[] = { 0, 0, };
+static int jz4760_uart1_hwflow_funcs[] = { 0, 0, };
+static int jz4760_uart2_data_funcs[] = { 0, 0, };
+static int jz4760_uart2_hwflow_funcs[] = { 0, 0, };
+static int jz4760_uart3_data_funcs[] = { 0, 1, };
+static int jz4760_uart3_hwflow_funcs[] = { 0, 0, };
+static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
+static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
+static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
+static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
+static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
+static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
+static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
+static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
+static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
+static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
+static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
+static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
+static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
+static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
+static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
+static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, };
+static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, };
+static int jz4760_nemc_rd_we_funcs[] = { 0, 0, };
+static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, };
+static int jz4760_nemc_wait_funcs[] = { 0, };
+static int jz4760_nemc_cs1_funcs[] = { 0, };
+static int jz4760_nemc_cs2_funcs[] = { 0, };
+static int jz4760_nemc_cs3_funcs[] = { 0, };
+static int jz4760_nemc_cs4_funcs[] = { 0, };
+static int jz4760_nemc_cs5_funcs[] = { 0, };
+static int jz4760_nemc_cs6_funcs[] = { 0, };
+static int jz4760_i2c0_funcs[] = { 0, 0, };
+static int jz4760_i2c1_funcs[] = { 0, 0, };
+static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4760_lcd_24bit_funcs[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0,
+};
+static int jz4760_pwm_pwm0_funcs[] = { 0, };
+static int jz4760_pwm_pwm1_funcs[] = { 0, };
+static int jz4760_pwm_pwm2_funcs[] = { 0, };
+static int jz4760_pwm_pwm3_funcs[] = { 0, };
+static int jz4760_pwm_pwm4_funcs[] = { 0, };
+static int jz4760_pwm_pwm5_funcs[] = { 0, };
+static int jz4760_pwm_pwm6_funcs[] = { 0, };
+static int jz4760_pwm_pwm7_funcs[] = { 0, };
+
+static const struct group_desc jz4760_groups[] = {
+ INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data),
+ INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow),
+ INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data),
+ INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow),
+ INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data),
+ INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow),
+ INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data),
+ INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow),
+ INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a),
+ INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a),
+ INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e),
+ INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e),
+ INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e),
+ INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d),
+ INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d),
+ INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e),
+ INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e),
+ INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e),
+ INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b),
+ INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b),
+ INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e),
+ INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e),
+ INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e),
+ INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data),
+ INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data),
+ INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale),
+ INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr),
+ INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we),
+ INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe),
+ INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait),
+ INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1),
+ INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2),
+ INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3),
+ INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4),
+ INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5),
+ INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6),
+ INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0),
+ INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1),
+ INGENIC_PIN_GROUP("cim-data", jz4760_cim),
+ INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit),
+ { "lcd-no-pins", },
+ INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0),
+ INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1),
+ INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2),
+ INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3),
+ INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4),
+ INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5),
+ INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6),
+ INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7),
+};
+
+static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
+static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
+static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
+static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
+static const char *jz4760_mmc0_groups[] = {
+ "mmc0-1bit-a", "mmc0-4bit-a",
+ "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
+};
+static const char *jz4760_mmc1_groups[] = {
+ "mmc1-1bit-d", "mmc1-4bit-d",
+ "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
+};
+static const char *jz4760_mmc2_groups[] = {
+ "mmc2-1bit-b", "mmc2-4bit-b",
+ "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
+};
+static const char *jz4760_nemc_groups[] = {
+ "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
+ "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
+};
+static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
+static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
+static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
+static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
+static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
+static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
+static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
+static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
+static const char *jz4760_cim_groups[] = { "cim-data", };
+static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
+static const char *jz4760_pwm0_groups[] = { "pwm0", };
+static const char *jz4760_pwm1_groups[] = { "pwm1", };
+static const char *jz4760_pwm2_groups[] = { "pwm2", };
+static const char *jz4760_pwm3_groups[] = { "pwm3", };
+static const char *jz4760_pwm4_groups[] = { "pwm4", };
+static const char *jz4760_pwm5_groups[] = { "pwm5", };
+static const char *jz4760_pwm6_groups[] = { "pwm6", };
+static const char *jz4760_pwm7_groups[] = { "pwm7", };
+
+static const struct function_desc jz4760_functions[] = {
+ { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
+ { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
+ { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
+ { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
+ { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
+ { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
+ { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
+ { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
+ { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
+ { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
+ { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
+ { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
+ { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
+ { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
+ { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
+ { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
+ { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
+ { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
+ { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
+ { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
+ { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
+ { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
+ { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
+ { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
+ { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
+ { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
+};
+
+static const struct ingenic_chip_info jz4760_chip_info = {
+ .num_chips = 6,
+ .groups = jz4760_groups,
+ .num_groups = ARRAY_SIZE(jz4760_groups),
+ .functions = jz4760_functions,
+ .num_functions = ARRAY_SIZE(jz4760_functions),
+ .pull_ups = jz4760_pull_ups,
+ .pull_downs = jz4760_pull_downs,
+};
+
+static const struct ingenic_chip_info jz4760b_chip_info = {
+ .num_chips = 6,
+ .groups = jz4760_groups,
+ .num_groups = ARRAY_SIZE(jz4760_groups),
+ .functions = jz4760_functions,
+ .num_functions = ARRAY_SIZE(jz4760_functions),
+ .pull_ups = jz4760_pull_ups,
+ .pull_downs = jz4760_pull_downs,
+};
+
static const u32 jz4770_pull_ups[6] = {
0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f,
};
@@ -775,8 +1040,8 @@ static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
u8 offset, int value)
{
- if (jzgc->jzpc->version >= ID_JZ4770)
- ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
+ if (jzgc->jzpc->version >= ID_JZ4760)
+ ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value);
else
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
}
@@ -786,9 +1051,9 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc,
{
u8 reg1, reg2;
- if (jzgc->jzpc->version >= ID_JZ4770) {
- reg1 = JZ4770_GPIO_PAT1;
- reg2 = JZ4770_GPIO_PAT0;
+ if (jzgc->jzpc->version >= ID_JZ4760) {
+ reg1 = JZ4760_GPIO_PAT1;
+ reg2 = JZ4760_GPIO_PAT0;
} else {
reg1 = JZ4740_GPIO_TRIG;
reg2 = JZ4740_GPIO_DIR;
@@ -837,8 +1102,8 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd)
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
int irq = irqd->hwirq;
- if (jzgc->jzpc->version >= ID_JZ4770)
- ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
+ if (jzgc->jzpc->version >= ID_JZ4760)
+ ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true);
else
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
@@ -853,8 +1118,8 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd)
ingenic_gpio_irq_mask(irqd);
- if (jzgc->jzpc->version >= ID_JZ4770)
- ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
+ if (jzgc->jzpc->version >= ID_JZ4760)
+ ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false);
else
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
}
@@ -878,8 +1143,8 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd)
irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
}
- if (jzgc->jzpc->version >= ID_JZ4770)
- ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
+ if (jzgc->jzpc->version >= ID_JZ4760)
+ ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false);
else
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
}
@@ -935,8 +1200,8 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc)
chained_irq_enter(irq_chip, desc);
- if (jzgc->jzpc->version >= ID_JZ4770)
- flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
+ if (jzgc->jzpc->version >= ID_JZ4760)
+ flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG);
else
flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
@@ -1001,8 +1266,8 @@ static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
struct ingenic_pinctrl *jzpc = jzgc->jzpc;
unsigned int pin = gc->base + offset;
- if (jzpc->version >= ID_JZ4770)
- return ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1);
+ if (jzpc->version >= ID_JZ4760)
+ return ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1);
if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
return true;
@@ -1027,11 +1292,11 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
'A' + offt, idx, func);
- if (jzpc->version >= ID_JZ4770) {
- ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
+ if (jzpc->version >= ID_JZ4760) {
+ ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
- ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
- ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
+ ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
+ ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
} else {
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
@@ -1080,10 +1345,10 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
'A' + offt, idx, input ? "in" : "out");
- if (jzpc->version >= ID_JZ4770) {
- ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
+ if (jzpc->version >= ID_JZ4760) {
+ ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
- ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
+ ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
} else {
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
@@ -1110,8 +1375,8 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
bool pull;
- if (jzpc->version >= ID_JZ4770)
- pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
+ if (jzpc->version >= ID_JZ4760)
+ pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN);
else
pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
@@ -1142,8 +1407,8 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
unsigned int pin, bool enabled)
{
- if (jzpc->version >= ID_JZ4770)
- ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !enabled);
+ if (jzpc->version >= ID_JZ4760)
+ ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !enabled);
else
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled);
}
@@ -1263,6 +1528,8 @@ static const struct regmap_config ingenic_pinctrl_regmap_config = {
static const struct of_device_id ingenic_pinctrl_of_match[] = {
{ .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 },
{ .compatible = "ingenic,jz4725b-pinctrl", .data = (void *)ID_JZ4725B },
+ { .compatible = "ingenic,jz4760-pinctrl", .data = (void *) ID_JZ4760 },
+ { .compatible = "ingenic,jz4760b-pinctrl", .data = (void *) ID_JZ4760B },
{ .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 },
{ .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 },
{},
@@ -1270,6 +1537,7 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = {
static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
{ .compatible = "ingenic,jz4740-gpio", },
+ { .compatible = "ingenic,jz4760-gpio", },
{ .compatible = "ingenic,jz4770-gpio", },
{ .compatible = "ingenic,jz4780-gpio", },
{},
@@ -1391,6 +1659,10 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
chip_info = &jz4780_chip_info;
else if (jzpc->version >= ID_JZ4770)
chip_info = &jz4770_chip_info;
+ else if (jzpc->version >= ID_JZ4760B)
+ chip_info = &jz4760b_chip_info;
+ else if (jzpc->version >= ID_JZ4760)
+ chip_info = &jz4760_chip_info;
else if (jzpc->version >= ID_JZ4725B)
chip_info = &jz4725b_chip_info;
else
@@ -1467,6 +1739,8 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
static const struct platform_device_id ingenic_pinctrl_ids[] = {
{ "jz4740-pinctrl", ID_JZ4740 },
{ "jz4725b-pinctrl", ID_JZ4725B },
+ { "jz4760-pinctrl", ID_JZ4760 },
+ { "jz4760b-pinctrl", ID_JZ4760B },
{ "jz4770-pinctrl", ID_JZ4770 },
{ "jz4780-pinctrl", ID_JZ4780 },
{},
--
2.7.4
^ permalink raw reply related
* [PATCH 3/6] dt-bindings: pinctrl: Add X1000 and X1000E bindings.
From: Zhou Yanjie @ 2019-07-14 3:53 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-gpio, devicetree, paul.burton, linus.walleij,
robh+dt, mark.rutland
In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com>
Add the pinctrl bindings for the X1000 Soc and
the X1000E Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
.../devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
index a80ff68..7e2ee46 100644
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
@@ -1,18 +1,18 @@
-Ingenic jz47xx pin controller
+Ingenic XBurst pin controller
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
-For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may
+For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
be used as GPIOs, multiplexed device functions are configured within the
GPIO port configuration registers and it is typical to refer to pins using the
naming scheme "PxN" where x is a character identifying the GPIO port with
which the pin is associated and N is an integer from 0 to 31 identifying the
pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
-PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to
-PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 contains 6
-GPIO ports, PA to PF, for a total of 192 pins.
+PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO
+ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780
+contains 6 GPIO ports, PA to PF, for a total of 192 pins.
Required properties:
@@ -25,6 +25,8 @@ Required properties:
- "ingenic,jz4760b-pinctrl"
- "ingenic,jz4770-pinctrl"
- "ingenic,jz4780-pinctrl"
+ - "ingenic,x1000-pinctrl"
+ - "ingenic,x1000e-pinctrl"
- reg: Address range of the pinctrl registers.
@@ -36,6 +38,7 @@ Required properties for sub-nodes (GPIO chips):
- "ingenic,jz4760-gpio"
- "ingenic,jz4770-gpio"
- "ingenic,jz4780-gpio"
+ - "ingenic,x1000-gpio"
- reg: The GPIO bank number.
- interrupt-controller: Marks the device node as an interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
--
2.7.4
^ permalink raw reply related
* [PATCH 4/6] pinctrl: Ingenic: Add pinctrl driver for X1000 and X1000E.
From: Zhou Yanjie @ 2019-07-14 3:53 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-gpio, devicetree, paul.burton, linus.walleij,
robh+dt, mark.rutland
In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com>
Add support for probing the pinctrl-ingenic driver on the
X1000 Soc and the X1000E Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/pinctrl/pinctrl-ingenic.c | 307 ++++++++++++++++++++++++++++++++++++--
1 file changed, 296 insertions(+), 11 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index ec61b083..5bb4ae5 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -41,6 +41,9 @@
#define JZ4760_GPIO_FLAG 0x50
#define JZ4760_GPIO_PEN 0x70
+#define X1000_GPIO_PZ_BASE 0x700
+#define X1000_GPIO_PZ_GID2LD 0x7f0
+
#define REG_SET(x) ((x) + 0x4)
#define REG_CLEAR(x) ((x) + 0x8)
@@ -53,6 +56,8 @@ enum jz_version {
ID_JZ4760B,
ID_JZ4770,
ID_JZ4780,
+ ID_X1000,
+ ID_X1000E,
};
struct ingenic_chip_info {
@@ -1009,6 +1014,210 @@ static const struct ingenic_chip_info jz4780_chip_info = {
.pull_downs = jz4770_pull_downs,
};
+static const u32 x1000_pull_ups[4] = {
+ 0xffffffff, 0x8dffffff, 0x7d3fffff, 0xffffffff,
+};
+
+static const u32 x1000_pull_downs[4] = {
+ 0x00000000, 0x02000000, 0x02000000, 0x00000000,
+};
+
+static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
+static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
+static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
+static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
+static int x1000_uart1_hwflow_d_pins[] = { 0x64, 0x65, };
+static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
+static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
+static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
+static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
+static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
+static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
+static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
+static int x1000_nemc_8bit_data_pins[] = {
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+};
+static int x1000_nemc_16bit_data_pins[] = {
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+};
+static int x1000_nemc_addr_pins[] = {
+ 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
+ 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
+};
+static int x1000_nemc_rd_we_pins[] = { 0x30, 0x31, };
+static int x1000_nemc_wait_pins[] = { 0x34, };
+static int x1000_nemc_cs1_pins[] = { 0x32, };
+static int x1000_nemc_cs2_pins[] = { 0x33, };
+static int x1000_i2c0_pins[] = { 0x38, 0x37, };
+static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
+static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
+static int x1000_i2c2_pins[] = { 0x61, 0x60, };
+static int x1000_cim_pins[] = {
+ 0x08, 0x09, 0x0a, 0x0b,
+ 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
+};
+static int x1000_lcd_8bit_pins[] = {
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x30, 0x31, 0x32, 0x33, 0x34,
+};
+static int x1000_lcd_16bit_pins[] = {
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+};
+static int x1000_pwm_pwm0_pins[] = { 0x59, };
+static int x1000_pwm_pwm1_pins[] = { 0x5a, };
+static int x1000_pwm_pwm2_pins[] = { 0x5b, };
+static int x1000_pwm_pwm3_pins[] = { 0x26, };
+static int x1000_pwm_pwm4_pins[] = { 0x58, };
+static int x1000_mac_pins[] = {
+ 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
+};
+
+static int x1000_uart0_data_funcs[] = { 0, 0, };
+static int x1000_uart0_hwflow_funcs[] = { 0, 0, };
+static int x1000_uart1_data_a_funcs[] = { 2, 2, };
+static int x1000_uart1_data_d_funcs[] = { 1, 1, };
+static int x1000_uart1_hwflow_d_funcs[] = { 1, 1, };
+static int x1000_uart2_data_a_funcs[] = { 2, 2, };
+static int x1000_uart2_data_d_funcs[] = { 0, 0, };
+static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, };
+static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, };
+static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, };
+static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, };
+static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, };
+static int x1000_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int x1000_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int x1000_nemc_addr_funcs[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+};
+static int x1000_nemc_rd_we_funcs[] = { 0, 0, };
+static int x1000_nemc_wait_funcs[] = { 0, };
+static int x1000_nemc_cs1_funcs[] = { 0, };
+static int x1000_nemc_cs2_funcs[] = { 0, };
+static int x1000_i2c0_funcs[] = { 0, 0, };
+static int x1000_i2c1_a_funcs[] = { 2, 2, };
+static int x1000_i2c1_c_funcs[] = { 0, 0, };
+static int x1000_i2c2_funcs[] = { 1, 1, };
+static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+static int x1000_lcd_8bit_funcs[] = {
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+};
+static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
+static int x1000_pwm_pwm0_funcs[] = { 0, };
+static int x1000_pwm_pwm1_funcs[] = { 1, };
+static int x1000_pwm_pwm2_funcs[] = { 1, };
+static int x1000_pwm_pwm3_funcs[] = { 2, };
+static int x1000_pwm_pwm4_funcs[] = { 0, };
+static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static const struct group_desc x1000_groups[] = {
+ INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data),
+ INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),
+ INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),
+ INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),
+ INGENIC_PIN_GROUP("uart1-hwflow-d", x1000_uart1_hwflow_d),
+ INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),
+ INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),
+ INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),
+ INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),
+ INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),
+ INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),
+ INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),
+ INGENIC_PIN_GROUP("nemc-8bit-data", x1000_nemc_8bit_data),
+ INGENIC_PIN_GROUP("nemc-16bit-data", x1000_nemc_16bit_data),
+ INGENIC_PIN_GROUP("nemc-addr", x1000_nemc_addr),
+ INGENIC_PIN_GROUP("nemc-rd-we", x1000_nemc_rd_we),
+ INGENIC_PIN_GROUP("nemc-wait", x1000_nemc_wait),
+ INGENIC_PIN_GROUP("nemc-cs1", x1000_nemc_cs1),
+ INGENIC_PIN_GROUP("nemc-cs2", x1000_nemc_cs2),
+ INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),
+ INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
+ INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
+ INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2),
+ INGENIC_PIN_GROUP("cim-data", x1000_cim),
+ INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit),
+ INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit),
+ { "lcd-no-pins", },
+ INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0),
+ INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1),
+ INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2),
+ INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3),
+ INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4),
+ INGENIC_PIN_GROUP("mac", x1000_mac),
+};
+
+static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
+static const char *x1000_uart1_groups[] = {
+ "uart1-data-a", "uart1-data-d", "uart1-hwflow-d",
+};
+static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
+static const char *x1000_mmc0_groups[] = {
+ "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
+};
+static const char *x1000_mmc1_groups[] = {
+ "mmc1-1bit-e", "mmc1-4bit-e",
+};
+static const char *x1000_nemc_groups[] = {
+ "nemc-8bit-data", "nemc-16bit-data",
+ "nemc-addr", "nemc-rd-we", "nemc-wait",
+};
+static const char *x1000_cs1_groups[] = { "nemc-cs1", };
+static const char *x1000_cs2_groups[] = { "nemc-cs2", };
+static const char *x1000_i2c0_groups[] = { "i2c0-data", };
+static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
+static const char *x1000_i2c2_groups[] = { "i2c2-data", };
+static const char *x1000_cim_groups[] = { "cim-data", };
+static const char *x1000_lcd_groups[] = {
+ "lcd-8bit", "lcd-16bit", "lcd-no-pins",
+};
+static const char *x1000_pwm0_groups[] = { "pwm0", };
+static const char *x1000_pwm1_groups[] = { "pwm1", };
+static const char *x1000_pwm2_groups[] = { "pwm2", };
+static const char *x1000_pwm3_groups[] = { "pwm3", };
+static const char *x1000_pwm4_groups[] = { "pwm4", };
+static const char *x1000_mac_groups[] = { "mac", };
+
+static const struct function_desc x1000_functions[] = {
+ { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
+ { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
+ { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
+ { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
+ { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
+ { "nemc", x1000_nemc_groups, ARRAY_SIZE(x1000_nemc_groups), },
+ { "nemc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
+ { "nemc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
+ { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
+ { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
+ { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
+ { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
+ { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
+ { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
+ { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
+ { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
+ { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
+ { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
+ { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
+};
+
+static const struct ingenic_chip_info x1000_chip_info = {
+ .num_chips = 4,
+ .groups = x1000_groups,
+ .num_groups = ARRAY_SIZE(x1000_groups),
+ .functions = x1000_functions,
+ .num_functions = ARRAY_SIZE(x1000_functions),
+ .pull_ups = x1000_pull_ups,
+ .pull_downs = x1000_pull_downs,
+};
+
+static const struct ingenic_chip_info x1000e_chip_info = {
+ .num_chips = 4,
+ .groups = x1000_groups,
+ .num_groups = ARRAY_SIZE(x1000_groups),
+ .functions = x1000_functions,
+ .num_functions = ARRAY_SIZE(x1000_functions),
+ .pull_ups = x1000_pull_ups,
+ .pull_downs = x1000_pull_downs,
+};
+
static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
{
unsigned int val;
@@ -1029,6 +1238,23 @@ static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
}
+static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
+ u8 reg, u8 offset, bool set)
+{
+ if (set)
+ reg = REG_SET(reg);
+ else
+ reg = REG_CLEAR(reg);
+
+ regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset));
+}
+
+static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
+{
+ regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_GID2LD,
+ jzgc->gc.base / PINS_PER_GPIO_CHIP);
+}
+
static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
u8 offset)
{
@@ -1061,21 +1287,45 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc,
switch (type) {
case IRQ_TYPE_EDGE_RISING:
- ingenic_gpio_set_bit(jzgc, reg2, offset, true);
- ingenic_gpio_set_bit(jzgc, reg1, offset, true);
+ if (jzgc->jzpc->version >= ID_X1000) {
+ ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);
+ ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);
+ ingenic_gpio_shadow_set_bit_load(jzgc);
+ } else {
+ ingenic_gpio_set_bit(jzgc, reg2, offset, true);
+ ingenic_gpio_set_bit(jzgc, reg1, offset, true);
+ }
break;
case IRQ_TYPE_EDGE_FALLING:
- ingenic_gpio_set_bit(jzgc, reg2, offset, false);
- ingenic_gpio_set_bit(jzgc, reg1, offset, true);
+ if (jzgc->jzpc->version >= ID_X1000) {
+ ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);
+ ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);
+ ingenic_gpio_shadow_set_bit_load(jzgc);
+ } else {
+ ingenic_gpio_set_bit(jzgc, reg2, offset, false);
+ ingenic_gpio_set_bit(jzgc, reg1, offset, true);
+ }
break;
case IRQ_TYPE_LEVEL_HIGH:
- ingenic_gpio_set_bit(jzgc, reg2, offset, true);
- ingenic_gpio_set_bit(jzgc, reg1, offset, false);
+ if (jzgc->jzpc->version >= ID_X1000) {
+ ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);
+ ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);
+ ingenic_gpio_shadow_set_bit_load(jzgc);
+ } else {
+ ingenic_gpio_set_bit(jzgc, reg2, offset, true);
+ ingenic_gpio_set_bit(jzgc, reg1, offset, false);
+ }
break;
case IRQ_TYPE_LEVEL_LOW:
default:
- ingenic_gpio_set_bit(jzgc, reg2, offset, false);
- ingenic_gpio_set_bit(jzgc, reg1, offset, false);
+ if (jzgc->jzpc->version >= ID_X1000) {
+ ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);
+ ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);
+ ingenic_gpio_shadow_set_bit_load(jzgc);
+ } else {
+ ingenic_gpio_set_bit(jzgc, reg2, offset, false);
+ ingenic_gpio_set_bit(jzgc, reg1, offset, false);
+ }
break;
}
}
@@ -1248,6 +1498,21 @@ static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
(set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
}
+static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
+ unsigned int pin, u8 reg, bool set)
+{
+ unsigned int idx = pin % PINS_PER_GPIO_CHIP;
+
+ regmap_write(jzpc->map, X1000_GPIO_PZ_BASE +
+ (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
+}
+
+static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
+ unsigned int pin)
+{
+ regmap_write(jzpc->map, X1000_GPIO_PZ_GID2LD, pin / PINS_PER_GPIO_CHIP);
+}
+
static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
unsigned int pin, u8 reg)
{
@@ -1292,7 +1557,13 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
'A' + offt, idx, func);
- if (jzpc->version >= ID_JZ4760) {
+ if (jzpc->version >= ID_X1000) {
+ ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
+ ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
+ ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
+ ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
+ ingenic_shadow_config_pin_load(jzpc, pin);
+ } else if (jzpc->version >= ID_JZ4760) {
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
@@ -1345,7 +1616,12 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
'A' + offt, idx, input ? "in" : "out");
- if (jzpc->version >= ID_JZ4760) {
+ if (jzpc->version >= ID_X1000) {
+ ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
+ ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
+ ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
+ ingenic_shadow_config_pin_load(jzpc, pin);
+ } else if (jzpc->version >= ID_JZ4760) {
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
@@ -1532,6 +1808,8 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = {
{ .compatible = "ingenic,jz4760b-pinctrl", .data = (void *) ID_JZ4760B },
{ .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 },
{ .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 },
+ { .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 },
+ { .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E },
{},
};
@@ -1540,6 +1818,7 @@ static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
{ .compatible = "ingenic,jz4760-gpio", },
{ .compatible = "ingenic,jz4770-gpio", },
{ .compatible = "ingenic,jz4780-gpio", },
+ { .compatible = "ingenic,x1000-gpio", },
{},
};
@@ -1655,7 +1934,11 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
else
jzpc->version = (enum jz_version)id->driver_data;
- if (jzpc->version >= ID_JZ4780)
+ if (jzpc->version >= ID_X1000E)
+ chip_info = &x1000e_chip_info;
+ else if (jzpc->version >= ID_X1000)
+ chip_info = &x1000_chip_info;
+ else if (jzpc->version >= ID_JZ4780)
chip_info = &jz4780_chip_info;
else if (jzpc->version >= ID_JZ4770)
chip_info = &jz4770_chip_info;
@@ -1743,6 +2026,8 @@ static const struct platform_device_id ingenic_pinctrl_ids[] = {
{ "jz4760b-pinctrl", ID_JZ4760B },
{ "jz4770-pinctrl", ID_JZ4770 },
{ "jz4780-pinctrl", ID_JZ4780 },
+ { "x1000-pinctrl", ID_X1000 },
+ { "x1000e-pinctrl", ID_X1000E },
{},
};
--
2.7.4
^ permalink raw reply related
* [PATCH 5/6] dt-bindings: pinctrl: Add X1500 bindings.
From: Zhou Yanjie @ 2019-07-14 3:53 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-gpio, devicetree, paul.burton, linus.walleij,
robh+dt, mark.rutland
In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com>
Add the pinctrl bindings for the X1500 Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
index 7e2ee46..0014d98 100644
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
@@ -27,6 +27,7 @@ Required properties:
- "ingenic,jz4780-pinctrl"
- "ingenic,x1000-pinctrl"
- "ingenic,x1000e-pinctrl"
+ - "ingenic,x1500-pinctrl"
- reg: Address range of the pinctrl registers.
--
2.7.4
^ permalink raw reply related
* [PATCH 6/6] pinctrl: Ingenic: Add pinctrl driver for X1500.
From: Zhou Yanjie @ 2019-07-14 3:53 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-gpio, devicetree, paul.burton, linus.walleij,
robh+dt, mark.rutland
In-Reply-To: <1563076436-5338-1-git-send-email-zhouyanjie@zoho.com>
Add support for probing the pinctrl-ingenic driver on the
X1500 Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/pinctrl/pinctrl-ingenic.c | 118 +++++++++++++++++++++++++++++++++++++-
1 file changed, 117 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index 5bb4ae5..6e26830 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -3,6 +3,7 @@
* Ingenic SoCs pinctrl driver
*
* Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
+ * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
*/
#include <linux/compiler.h>
@@ -58,6 +59,7 @@ enum jz_version {
ID_JZ4780,
ID_X1000,
ID_X1000E,
+ ID_X1500,
};
struct ingenic_chip_info {
@@ -1218,6 +1220,116 @@ static const struct ingenic_chip_info x1000e_chip_info = {
.pull_downs = x1000_pull_downs,
};
+static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
+static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
+static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
+static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
+static int x1500_uart1_hwflow_d_pins[] = { 0x64, 0x65, };
+static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
+static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
+static int x1500_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
+static int x1500_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
+static int x1500_i2c0_pins[] = { 0x38, 0x37, };
+static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
+static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
+static int x1500_i2c2_pins[] = { 0x61, 0x60, };
+static int x1500_cim_pins[] = {
+ 0x08, 0x09, 0x0a, 0x0b,
+ 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
+};
+static int x1500_pwm_pwm0_pins[] = { 0x59, };
+static int x1500_pwm_pwm1_pins[] = { 0x5a, };
+static int x1500_pwm_pwm2_pins[] = { 0x5b, };
+static int x1500_pwm_pwm3_pins[] = { 0x26, };
+static int x1500_pwm_pwm4_pins[] = { 0x58, };
+
+static int x1500_uart0_data_funcs[] = { 0, 0, };
+static int x1500_uart0_hwflow_funcs[] = { 0, 0, };
+static int x1500_uart1_data_a_funcs[] = { 2, 2, };
+static int x1500_uart1_data_d_funcs[] = { 1, 1, };
+static int x1500_uart1_hwflow_d_funcs[] = { 1, 1, };
+static int x1500_uart2_data_a_funcs[] = { 2, 2, };
+static int x1500_uart2_data_d_funcs[] = { 0, 0, };
+static int x1500_mmc0_1bit_funcs[] = { 1, 1, 1, };
+static int x1500_mmc0_4bit_funcs[] = { 1, 1, 1, };
+static int x1500_i2c0_funcs[] = { 0, 0, };
+static int x1500_i2c1_a_funcs[] = { 2, 2, };
+static int x1500_i2c1_c_funcs[] = { 0, 0, };
+static int x1500_i2c2_funcs[] = { 1, 1, };
+static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+static int x1500_pwm_pwm0_funcs[] = { 0, };
+static int x1500_pwm_pwm1_funcs[] = { 1, };
+static int x1500_pwm_pwm2_funcs[] = { 1, };
+static int x1500_pwm_pwm3_funcs[] = { 2, };
+static int x1500_pwm_pwm4_funcs[] = { 0, };
+
+static const struct group_desc x1500_groups[] = {
+ INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data),
+ INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow),
+ INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a),
+ INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d),
+ INGENIC_PIN_GROUP("uart1-hwflow-d", x1500_uart1_hwflow_d),
+ INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a),
+ INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d),
+ INGENIC_PIN_GROUP("mmc0-1bit", x1500_mmc0_1bit),
+ INGENIC_PIN_GROUP("mmc0-4bit", x1500_mmc0_4bit),
+ INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0),
+ INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),
+ INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),
+ INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2),
+ INGENIC_PIN_GROUP("cim-data", x1500_cim),
+ { "lcd-no-pins", },
+ INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0),
+ INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1),
+ INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2),
+ INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3),
+ INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4),
+};
+
+static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
+static const char *x1500_uart1_groups[] = {
+ "uart1-data-a", "uart1-data-d", "uart1-hwflow-d",
+};
+static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
+static const char *x1500_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
+static const char *x1500_i2c0_groups[] = { "i2c0-data", };
+static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
+static const char *x1500_i2c2_groups[] = { "i2c2-data", };
+static const char *x1500_cim_groups[] = { "cim-data", };
+static const char *x1500_lcd_groups[] = { "lcd-no-pins", };
+static const char *x1500_pwm0_groups[] = { "pwm0", };
+static const char *x1500_pwm1_groups[] = { "pwm1", };
+static const char *x1500_pwm2_groups[] = { "pwm2", };
+static const char *x1500_pwm3_groups[] = { "pwm3", };
+static const char *x1500_pwm4_groups[] = { "pwm4", };
+
+static const struct function_desc x1500_functions[] = {
+ { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
+ { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
+ { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
+ { "mmc0", x1500_mmc0_groups, ARRAY_SIZE(x1500_mmc0_groups), },
+ { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
+ { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
+ { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
+ { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
+ { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), },
+ { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
+ { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
+ { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
+ { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
+ { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
+};
+
+static const struct ingenic_chip_info x1500_chip_info = {
+ .num_chips = 4,
+ .groups = x1500_groups,
+ .num_groups = ARRAY_SIZE(x1500_groups),
+ .functions = x1500_functions,
+ .num_functions = ARRAY_SIZE(x1500_functions),
+ .pull_ups = x1000_pull_ups,
+ .pull_downs = x1000_pull_downs,
+};
+
static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
{
unsigned int val;
@@ -1810,6 +1922,7 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = {
{ .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 },
{ .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 },
{ .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E },
+ { .compatible = "ingenic,x1500-pinctrl", .data = (void *) ID_X1500 },
{},
};
@@ -1934,7 +2047,9 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
else
jzpc->version = (enum jz_version)id->driver_data;
- if (jzpc->version >= ID_X1000E)
+ if (jzpc->version >= ID_X1500)
+ chip_info = &x1500_chip_info;
+ else if (jzpc->version >= ID_X1000E)
chip_info = &x1000e_chip_info;
else if (jzpc->version >= ID_X1000)
chip_info = &x1000_chip_info;
@@ -2028,6 +2143,7 @@ static const struct platform_device_id ingenic_pinctrl_ids[] = {
{ "jz4780-pinctrl", ID_JZ4780 },
{ "x1000-pinctrl", ID_X1000 },
{ "x1000e-pinctrl", ID_X1000E },
+ { "x1500-pinctrl", ID_X1500 },
{},
};
--
2.7.4
^ permalink raw reply related
* Re: [PATCH] platform/x86: pcengines-apu2 needs gpiolib
From: Andy Shevchenko @ 2019-07-14 16:41 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Darren Hart, Andy Shevchenko, open list:GPIO SUBSYSTEM,
Linus Walleij, Bartosz Golaszewski, Platform Driver,
Enrico Weigelt, metux IT consult, Randy Dunlap, Rafael J. Wysocki,
Linux Kernel Mailing List
In-Reply-To: <20190712085437.4007720-1-arnd@arndb.de>
On Fri, Jul 12, 2019 at 11:54 AM Arnd Bergmann <arnd@arndb.de> wrote:
>
> I ran into another build issue in randconfig testing for this driver,
> when CONFIG_GPIOLIB is not set:
>
> WARNING: unmet direct dependencies detected for GPIO_AMD_FCH
> Depends on [n]: GPIOLIB [=n] && HAS_IOMEM [=y]
> Selected by [y]:
> - PCENGINES_APU2 [=y] && X86 [=y] && X86_PLATFORM_DEVICES [=y] && INPUT [=y] && INPUT_KEYBOARD [=y] && LEDS_CLASS [=y]
>
> WARNING: unmet direct dependencies detected for KEYBOARD_GPIO_POLLED
> Depends on [n]: !UML && INPUT [=y] && INPUT_KEYBOARD [=y] && GPIOLIB [=n]
> Selected by [y]:
> - PCENGINES_APU2 [=y] && X86 [=y] && X86_PLATFORM_DEVICES [=y] && INPUT [=y] && INPUT_KEYBOARD [=y] && LEDS_CLASS [=y]
>
> Make the 'select' statements conditional on that so we don't have to
> introduce another 'select'.
>
Thanks, I have applied the fix from YueHaibing, the idea is to depened
on GPIOLIB.
> Fixes: f8eb0235f659 ("x86: pcengines apuv2 gpio/leds/keys platform driver")
> Fixes: a422bf11bdb4 ("platform/x86: fix PCENGINES_APU2 Kconfig warning")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> drivers/platform/x86/Kconfig | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
> index e869a5c760b6..cf48b9068843 100644
> --- a/drivers/platform/x86/Kconfig
> +++ b/drivers/platform/x86/Kconfig
> @@ -1324,8 +1324,8 @@ config PCENGINES_APU2
> tristate "PC Engines APUv2/3 front button and LEDs driver"
> depends on INPUT && INPUT_KEYBOARD
> depends on LEDS_CLASS
> - select GPIO_AMD_FCH
> - select KEYBOARD_GPIO_POLLED
> + select GPIO_AMD_FCH if GPIOLIB
> + select KEYBOARD_GPIO_POLLED if GPIOLIB
> select LEDS_GPIO
> help
> This driver provides support for the front button and LEDs on
> --
> 2.20.0
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH] platform/x86: Fix PCENGINES_APU2 Kconfig warning
From: Andy Shevchenko @ 2019-07-14 16:42 UTC (permalink / raw)
To: Enrico Weigelt, metux IT consult
Cc: YueHaibing, Darren Hart, Andy Shevchenko, Linus Walleij,
Randy Dunlap, Enrico Weigelt, metux IT consult,
Linux Kernel Mailing List, Platform Driver,
open list:GPIO SUBSYSTEM
In-Reply-To: <603661e6-8694-4787-6cee-61cc6ba61fc2@metux.net>
On Mon, Jul 8, 2019 at 1:43 PM Enrico Weigelt, metux IT consult
<lkml@metux.net> wrote:
>
> On 04.07.19 08:27, YueHaibing wrote:
> > Fix Kconfig warning for PCENGINES_APU2 symbol:
> >
> > WARNING: unmet direct dependencies detected for GPIO_AMD_FCH
> > Depends on [n]: GPIOLIB [=n] && HAS_IOMEM [=y]
> > Selected by [y]:
> > - PCENGINES_APU2 [=y] && X86 [=y] && X86_PLATFORM_DEVICES [=y] && INPUT [=y] && INPUT_KEYBOARD [=y] && LEDS_CLASS [=y]
> >
> > WARNING: unmet direct dependencies detected for KEYBOARD_GPIO_POLLED
> > Depends on [n]: !UML && INPUT [=y] && INPUT_KEYBOARD [=y] && GPIOLIB [=n]
> > Selected by [y]:
> > - PCENGINES_APU2 [=y] && X86 [=y] && X86_PLATFORM_DEVICES [=y] && INPUT [=y] && INPUT_KEYBOARD [=y] && LEDS_CLASS [=y]
> >
> > Add GPIOLIB dependency to fix it.
>
Applied.
> hmm, I'm not really happy w/ the kernel config system at that point:
>
> If the select on the gpio driver would just subsequently enable gpiolib,
> everything would be fine. But that contradicts how subsystems are
> currently handled - you first have to enable gpio subsystem before
> choosing anything that depends on it :(
>
> Could it make sense to refactor gpiolib in a way that pieces directly
> needed by gpio consumers or drivers (hmm, perhaps have separate
> dependency symbols for consumer vs driver) can be selected directly,
> even if the big gpio subsystem knob is disabled ? (but the other things
> like userland interfaces would remain disabled) ?
>
> OTOH, for this particular patch:
>
> Ack-By: Enrico Weigelt <info@metux.net>
Patchwork doesn't recognize non-standard tags, thus the patch went
without it to the upstream.
>
>
> --mtx
>
> --
> Enrico Weigelt, metux IT consult
> Free software and Linux embedded engineering
> info@metux.net -- +49-151-27565287
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH V5 11/18] clk: tegra210: Add support for Tegra210 clocks
From: Dmitry Osipenko @ 2019-07-14 21:41 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <a9b5c364-52b4-bee1-5881-47197f043950@nvidia.com>
13.07.2019 8:54, Sowjanya Komatineni пишет:
>
> On 6/29/19 8:10 AM, Dmitry Osipenko wrote:
>> 28.06.2019 5:12, Sowjanya Komatineni пишет:
>>> This patch adds system suspend and resume support for Tegra210
>>> clocks.
>>>
>>> All the CAR controller settings are lost on suspend when core power
>>> goes off.
>>>
>>> This patch has implementation for saving and restoring all the PLLs
>>> and clocks context during system suspend and resume to have the
>>> clocks back to same state for normal operation.
>>>
>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>> drivers/clk/tegra/clk-tegra210.c | 115
>>> ++++++++++++++++++++++++++++++++++++++-
>>> drivers/clk/tegra/clk.c | 14 +++++
>>> drivers/clk/tegra/clk.h | 1 +
>>> 3 files changed, 127 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/clk/tegra/clk-tegra210.c
>>> b/drivers/clk/tegra/clk-tegra210.c
>>> index 1c08c53482a5..1b839544e086 100644
>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>> @@ -9,10 +9,12 @@
>>> #include <linux/clkdev.h>
>>> #include <linux/of.h>
>>> #include <linux/of_address.h>
>>> +#include <linux/of_platform.h>
>>> #include <linux/delay.h>
>>> #include <linux/export.h>
>>> #include <linux/mutex.h>
>>> #include <linux/clk/tegra.h>
>>> +#include <linux/syscore_ops.h>
>>> #include <dt-bindings/clock/tegra210-car.h>
>>> #include <dt-bindings/reset/tegra210-car.h>
>>> #include <linux/iopoll.h>
>>> @@ -20,6 +22,7 @@
>>> #include <soc/tegra/pmc.h>
>>> #include "clk.h"
>>> +#include "clk-dfll.h"
>>> #include "clk-id.h"
>>> /*
>>> @@ -225,6 +228,7 @@
>>> #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
>>> #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
>>> +#define CPU_SOFTRST_CTRL 0x380
>>> #define LVL2_CLK_GATE_OVRA 0xf8
>>> #define LVL2_CLK_GATE_OVRC 0x3a0
>>> @@ -2820,6 +2824,7 @@ static int tegra210_enable_pllu(void)
>>> struct tegra_clk_pll_freq_table *fentry;
>>> struct tegra_clk_pll pllu;
>>> u32 reg;
>>> + int ret;
>>> for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
>>> if (fentry->input_rate == pll_ref_freq)
>>> @@ -2847,10 +2852,10 @@ static int tegra210_enable_pllu(void)
>>> fence_udelay(1, clk_base);
>>> reg |= PLL_ENABLE;
>>> writel(reg, clk_base + PLLU_BASE);
>>> + fence_udelay(1, clk_base);
>>> - readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
>>> - reg & PLL_BASE_LOCK, 2, 1000);
>>> - if (!(reg & PLL_BASE_LOCK)) {
>>> + ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
>>> + if (ret) {
>>> pr_err("Timed out waiting for PLL_U to lock\n");
>>> return -ETIMEDOUT;
>>> }
>>> @@ -3283,6 +3288,103 @@ static void tegra210_disable_cpu_clock(u32 cpu)
>>> }
>>> #ifdef CONFIG_PM_SLEEP
>>> +static u32 cpu_softrst_ctx[3];
>>> +static struct platform_device *dfll_pdev;
>>> +#define car_readl(_base, _off) readl_relaxed(clk_base + (_base) +
>>> ((_off) * 4))
>>> +#define car_writel(_val, _base, _off) \
>>> + writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
>>> +
>>> +static int tegra210_clk_suspend(void)
>>> +{
>>> + unsigned int i;
>>> + struct device_node *node;
>>> +
>>> + tegra_cclkg_burst_policy_save_context();
>>> +
>>> + if (!dfll_pdev) {
>>> + node = of_find_compatible_node(NULL, NULL,
>>> + "nvidia,tegra210-dfll");
>>> + if (node)
>>> + dfll_pdev = of_find_device_by_node(node);
>>> +
>>> + of_node_put(node);
>>> + if (!dfll_pdev)
>>> + pr_err("dfll node not found. no suspend for dfll\n");
>>> + }
>>> +
>>> + if (dfll_pdev)
>>> + tegra_dfll_suspend(dfll_pdev);
>>> +
>>> + /* Enable PLLP_OUT_CPU after dfll suspend */
>>> + tegra_clk_set_pllp_out_cpu(true);
>>> +
>>> + tegra_sclk_cclklp_burst_policy_save_context();
>>> +
>>> + clk_save_context();
>>> +
>>> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
>>> + cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void tegra210_clk_resume(void)
>>> +{
>>> + unsigned int i;
>>> + struct clk_hw *parent;
>>> + struct clk *clk;
>>> +
>>> + /*
>>> + * clk_restore_context restores clocks as per the clock tree.
>>> + *
>>> + * dfllCPU_out is first in the clock tree to get restored and it
>>> + * involves programming DFLL controller along with restoring CPUG
>>> + * clock burst policy.
>>> + *
>>> + * DFLL programming needs dfll_ref and dfll_soc peripheral clocks
>>> + * to be restores which are part ofthe peripheral clocks.
^ white-space
Please use spellchecker to avoid typos.
>>> + * So, peripheral clocks restore should happen prior to dfll clock
>>> + * restore.
>>> + */
>>> +
>>> + tegra_clk_osc_resume(clk_base);
>>> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
>>> + car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i);
>>> +
>>> + /* restore all plls and peripheral clocks */
>>> + tegra210_init_pllu();
>>> + clk_restore_context();
>>> +
>>> + fence_udelay(5, clk_base);
>>> +
>>> + /* resume SCLK and CPULP clocks */
>>> + tegra_sclk_cpulp_burst_policy_restore_context();
>>> +
>>> + /*
>>> + * restore CPUG clocks:
>>> + * - enable DFLL in open loop mode
>>> + * - switch CPUG to DFLL clock source
>>> + * - close DFLL loop
>>> + * - sync PLLX state
>>> + */
>>> + if (dfll_pdev)
>>> + tegra_dfll_resume(dfll_pdev, false);
>>> +
>>> + tegra_cclkg_burst_policy_restore_context();
>>> + fence_udelay(2, clk_base);
>>> +
>>> + if (dfll_pdev)
>>> + tegra_dfll_resume(dfll_pdev, true);
>>> +
>>> + parent =
>>> clk_hw_get_parent(__clk_get_hw(clks[TEGRA210_CLK_CCLK_G]));
>>> + clk = clks[TEGRA210_CLK_PLL_X];
>>> + if (parent != __clk_get_hw(clk))
>>> + tegra_clk_sync_state_pll(__clk_get_hw(clk));
>>> +
>>> + /* Disable PLL_OUT_CPU after DFLL resume */
>>> + tegra_clk_set_pllp_out_cpu(false);
>>> +}
>>> +
>>> static void tegra210_cpu_clock_suspend(void)
>>> {
>>> /* switch coresite to clk_m, save off original source */
>>> @@ -3298,6 +3400,11 @@ static void tegra210_cpu_clock_resume(void)
>>> }
>>> #endif
>>> +static struct syscore_ops tegra_clk_syscore_ops = {
>>> + .suspend = tegra210_clk_suspend,
>>> + .resume = tegra210_clk_resume,
>>> +};
>>> +
>>> static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
>>> .wait_for_reset = tegra210_wait_cpu_in_reset,
>>> .disable_clock = tegra210_disable_cpu_clock,
>>> @@ -3583,5 +3690,7 @@ static void __init tegra210_clock_init(struct
>>> device_node *np)
>>> tegra210_mbist_clk_init();
>>> tegra_cpu_car_ops = &tegra210_cpu_car_ops;
>>> +
>>> + register_syscore_ops(&tegra_clk_syscore_ops);
>>> }
>> Is it really worthwhile to use syscore_ops for suspend/resume given
>> that drivers for
>> won't resume before the CLK driver anyway? Are there any other options
>> for CLK
>> suspend/resume?
>>
>> I'm also not sure whether PM runtime API could be used at all in the
>> context of
>> syscore_ops ..
>>
>> Secondly, what about to use generic clk_save_context() /
>> clk_restore_context()
>> helpers for the suspend-resume? It looks to me that some other
>> essential (and proper)
>> platform driver (soc/tegra/? PMC?) should suspend-resume the clocks
>> using the generic
>> CLK Framework API.
>
> Clock resume should happen very early to restore peripheral and cpu
> clocks very early than peripheral drivers resume happens.
If all peripheral drivers properly requested all of the necessary clocks
and CLK driver was a platform driver, then I guess the probe should have
been naturally ordered. But that's not very achievable with the
currently available infrastructure in the kernel, so I'm not arguing
that the clocks should be explicitly resumed before the users.
> this patch series uses clk_save_context and clk_restore_context for
> corresponding divider, pll, pllout.. save and restore context.
Now I see that indeed this API is utilized in this patch, thank you for
the clarification.
> But as there is dependency on dfll resume and cpu and pllx clocks
> restore, couldnt use clk_save_context and clk_restore_context for dfll.
>
> So implemented recommended dfll resume sequence in main Tegra210 clock
> driver along with invoking clk_save_context/clk_restore_context where
> all other clocks save/restore happens as per clock tree traversal.
Could you please clarify what part of peripherals clocks is required for
DFLL's restore? Couldn't DFLL driver be changed to avoid that quirkness
and thus to make DFLL driver suspend/resume the clock?
^ permalink raw reply
* Re: [PATCH V5 02/18] pinctrl: tegra: Add suspend and resume support
From: Dmitry Osipenko @ 2019-07-14 21:41 UTC (permalink / raw)
To: Sowjanya Komatineni, Linus Walleij
Cc: thierry.reding@gmail.com, Jon Hunter, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Stefan Agner, Mark Rutland,
Peter De Schrijver, Prashant Gaikwad, Stephen Boyd, linux-clk,
open list:GPIO SUBSYSTEM, jckuo, Joseph Lo, talho, linux-tegra,
linux-kernel@vger.kernel.org, Mikko Perttunen, spatra,
Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <db7ac8e6-bfad-bc60-b46e-d886025872e4@nvidia.com>
13.07.2019 8:31, Sowjanya Komatineni пишет:
>
> On 7/4/19 3:40 AM, Dmitry Osipenko wrote:
>> 04.07.2019 10:31, Linus Walleij пишет:
>>> On Sat, Jun 29, 2019 at 5:58 PM Dmitry Osipenko <digetx@gmail.com>
>>> wrote:
>>>
>>>> Oh, also what about GPIO-pinctrl suspend resume ordering .. is it
>>>> okay that pinctrl
>>>> will be resumed after GPIO? Shouldn't a proper pin-muxing be
>>>> selected at first?
>>> Thierry sent some initial patches about this I think. We need to use
>>> device links for this to work properly so he adds support for
>>> linking the pinctrl and GPIO devices through the ranges.
>>>
>>> For links between pin control handles and their consumers, see also:
>>> 036f394dd77f pinctrl: Enable device link creation for pin control
>>> c6045b4e3cad pinctrl: stmfx: enable links creations
>>> 489b64d66325 pinctrl: stm32: Add links to consumers
>>>
>>> I am using STM32 as guinea pig for this, consider adding links also
>>> from the Tegra pinctrl. I might simply make these pinctrl consumer
>>> to producer links default because I think it makes a lot sense.
>> IIUC, currently the plan is to resume pinctrl *after* GPIO for
>> Tegra210 [1]. But this
>> contradicts to what was traditionally done for older Tegras where
>> pinctrl was always
>> resumed first and apparently it won't work well for the GPIO ranges as
>> well. I think this
>> and the other patchsets related to suspend-resume still need some more
>> thought.
>>
>> [1] https://patchwork.kernel.org/patch/11012077/
>
> Park bit was introduced from Tegra210 onwards and during suspend/resume,
> requirement of gpio restore prior to pinctrl restore is not required for
> prior Tegra210.
>
> Also currently pinctrl suspend/resume implementation for prior Tegra210
> is not yet upstreamed but having gpio restore prior to pinmux during
> suspend/resume should not cause any issue for prior tegra's as well as
> gpio resume restores pins back to same gpio config as they were during
> suspend entry.
>
Okay!
^ permalink raw reply
* Re: [PATCH 2/3 v2] dt-bindings: gpio: aspeed: Add SGPIO support
From: Andrew Jeffery @ 2019-07-15 2:25 UTC (permalink / raw)
To: Hongwei Zhang, Joel Stanley, Linus Walleij, devicetree
Cc: Rob Herring, Mark Rutland, Bartosz Golaszewski, linux-aspeed,
linux-kernel, linux-arm-kernel, linux-gpio
In-Reply-To: <1562962440-15908-1-git-send-email-hongweiz@ami.com>
Hello Hongwei,
On Sat, 13 Jul 2019, at 05:44, Hongwei Zhang wrote:
> Add bindings to support SGPIO on AST2400 or AST2500.
>
> Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
> ---
> .../devicetree/bindings/gpio/sgpio-aspeed.txt | 43 ++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100755 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
>
> diff --git a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
> b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
> new file mode 100755
> index 0000000..3ae2b79
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
> @@ -0,0 +1,43 @@
> +Aspeed SGPIO controller Device Tree Bindings
> +-------------------------------------------
> +
> +Required properties:
> +- compatible : Either "aspeed,ast2400-sgpio" or "aspeed,ast2500-sgpio"
> +
> +- #gpio-cells : Should be two
> + - First cell is the GPIO line number
> + - Second cell is used to specify optional
> + parameters (unused)
> +
> +- reg : Address and length of the register set for the device
> +- gpio-controller : Marks the device node as a GPIO controller.
> +- interrupts : Interrupt specifier (see interrupt bindings for
> + details)
> +
> +- interrupt-controller : Mark the GPIO controller as an
> interrupt-controller
> +
> +- nr-gpios : number of GPIO pins to serialise. (should be multiple of
> 8, up to 80 pins)
> + if not specified, defaults to 80.
This appears to be a statement about the driver implementation, but bindings
documents are about describing hardware. Reading the datasheet it actually
appears the ASPEED SGPIO hardware comes up in what is "technically" a
forbidden state (equivalent to `nr-gpios = <0>;`), though the device is also
disabled at this point, so it's probably moot. The point is the true default
value from a hardware perspective is 0, not 80, so if we're going to talk about
default values, 0 would be more appropriate. However:
You've also listed nr-gpios under the "Required properties" header, but the
description suggests it's optional. It's either one or the other, please lets be
clear about it. On that front, lets make it nr-gpios *not* optional (i.e. make it
required) thus force the specification of how many SGPIOs we want to emit
on the bus. This value is coupled to the platform design, so I don't think
there's ever a scenario where we want nr-gpios to take a default value.
> +
> +- clocks : A phandle to the APB clock for SGPM clock
> division
> +
> +- bus-frequency : SGPM CLK frequency, if not specified defaults to 1
> MHz
Again here with the default value - SGPM CLK period is derived from PCLK by
the expression `period = PCLK * 2 *(GPIO254[31:16] + 1)`, where GPIO254's
initialisation state is `GPIO254[31:16] = 0`, which gives a default SGPM bus
frequency of PCLK / 2. This is likely not going to be 1MHz (more like ~12MHz).
Lets just make the property required. That way we avoid any ambiguity about
the bus frequency and thus don't need words about defaults that turn out to
be about the driver, not about the hardware.
Finally, when updating patches in response to feedback, please send the full
series again, and bump the series version number. That way people can review
a coherent set of patches and not have to hunt around and (fail to) collate the
correct combination. It makes it easier to say "Reviewed-by:" on your patches :)
Cheers,
Andrew
^ permalink raw reply
* Re: [PATCH v2 1/2] gpio: em: remove the gpiochip before removing the irq domain
From: Bartosz Golaszewski @ 2019-07-15 9:58 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linus Walleij, Phil Reid, open list:GPIO SUBSYSTEM,
Linux Kernel Mailing List, Bartosz Golaszewski, stable,
Niklas Söderlund
In-Reply-To: <CAMuHMdWzEOVLUZM_rFfMKqF_G_gZXBpV7TC-OXmN8YKw6_occQ@mail.gmail.com>
czw., 11 lip 2019 o 10:47 Geert Uytterhoeven <geert@linux-m68k.org> napisał(a):
>
> CC Niklas, who has the hardware
>
> On Thu, Jul 11, 2019 at 10:29 AM Bartosz Golaszewski <brgl@bgdev.pl> wrote:
> > From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >
> > In commit 8764c4ca5049 ("gpio: em: use the managed version of
> > gpiochip_add_data()") we implicitly altered the ordering of resource
> > freeing: since gpiochip_remove() calls gpiochip_irqchip_remove()
> > internally, we now can potentially use the irq_domain after it was
> > destroyed in the remove() callback (as devm resources are freed after
> > remove() has returned).
> >
> > Use devm_add_action_or_reset() to keep the ordering right and entirely
> > kill the remove() callback in the driver.
> >
> > Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
> > Fixes: 8764c4ca5049 ("gpio: em: use the managed version of gpiochip_add_data()")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
Patch applied.
^ permalink raw reply
* [GIT PULL] gpio fixes for v5.3-rc1
From: Bartosz Golaszewski @ 2019-07-15 9:59 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, Bartosz Golaszewski
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Linus,
please pull the following fixes applied to my tree during this merge window.
The following changes since commit fec88ab0af9706b2201e5daf377c5031c62d11f7:
Merge tag 'for-linus-hmm' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma (2019-07-14 19:42:11 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git tags/gpio-v5.3-rc1-fixes-for-linus
for you to fetch changes up to 19ec11a2233d24a7811836fa735203aaccf95a23:
gpio: em: remove the gpiochip before removing the irq domain (2019-07-15 11:52:42 +0200)
----------------------------------------------------------------
GPIO fixes for v5.3-rc1
- silence error messages on probe deferral in gpio-davinci
- fix a memory leak in gpiolib-of
- fix a potential use-after-free error in gpio-em
----------------------------------------------------------------
Bartosz Golaszewski (1):
gpio: em: remove the gpiochip before removing the irq domain
Keerthy (1):
gpio: davinci: silence error prints in case of EPROBE_DEFER
Nishka Dasgupta (1):
gpiolib: of: fix a memory leak in of_gpio_flags_quirks()
drivers/gpio/gpio-davinci.c | 5 +++--
drivers/gpio/gpio-em.c | 33 +++++++++++++++------------------
drivers/gpio/gpiolib-of.c | 1 +
3 files changed, 19 insertions(+), 20 deletions(-)
^ permalink raw reply
* [PATCH AUTOSEL 5.2 090/249] gpio: omap: fix lack of irqstatus_raw0 for OMAP4
From: Sasha Levin @ 2019-07-15 13:44 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Russell King, Grygorii Strashko, Tony Lindgren, Linus Walleij,
Sasha Levin, linux-omap, linux-gpio
In-Reply-To: <20190715134655.4076-1-sashal@kernel.org>
From: Russell King <rmk+kernel@armlinux.org.uk>
[ Upstream commit 64ea3e9094a1f13b96c33244a3fb3a0f45690bd2 ]
Commit 384ebe1c2849 ("gpio/omap: Add DT support to GPIO driver") added
the register definition tables to the gpio-omap driver. Subsequently to
that commit, commit 4e962e8998cc ("gpio/omap: remove cpu_is_omapxxxx()
checks from *_runtime_resume()") added definitions for irqstatus_raw*
registers to the legacy OMAP4 definitions, but missed the DT
definitions.
This causes an unintentional change of behaviour for the 1.101 errata
workaround on OMAP4 platforms. Fix this oversight.
Fixes: 4e962e8998cc ("gpio/omap: remove cpu_is_omapxxxx() checks from *_runtime_resume()")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpio/gpio-omap.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 9276ef616430..7632c98aa3a4 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1453,6 +1453,8 @@ static struct omap_gpio_reg_offs omap4_gpio_regs = {
.clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
.irqstatus = OMAP4_GPIO_IRQSTATUS0,
.irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
+ .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
+ .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
.irqenable = OMAP4_GPIO_IRQSTATUSSET0,
.irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
.set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
--
2.20.1
^ permalink raw reply related
* [PATCH AUTOSEL 5.2 091/249] gpio: omap: ensure irq is enabled before wakeup
From: Sasha Levin @ 2019-07-15 13:44 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Russell King, Grygorii Strashko, Tony Lindgren, Linus Walleij,
Sasha Levin, linux-omap, linux-gpio
In-Reply-To: <20190715134655.4076-1-sashal@kernel.org>
From: Russell King <rmk+kernel@armlinux.org.uk>
[ Upstream commit c859e0d479b3b4f6132fc12637c51e01492f31f6 ]
Documentation states:
NOTE: There must be a correlation between the wake-up enable and
interrupt-enable registers. If a GPIO pin has a wake-up configured
on it, it must also have the corresponding interrupt enabled (on
one of the two interrupt lines).
Ensure that this condition is always satisfied by enabling the detection
events after enabling the interrupt, and disabling the detection before
disabling the interrupt. This ensures interrupt/wakeup events can not
happen until both the wakeup and interrupt enables correlate.
If we do any clearing, clear between the interrupt enable/disable and
trigger setting.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpio/gpio-omap.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 7632c98aa3a4..746aa9caf934 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -829,9 +829,9 @@ static void omap_gpio_irq_shutdown(struct irq_data *d)
raw_spin_lock_irqsave(&bank->lock, flags);
bank->irq_usage &= ~(BIT(offset));
- omap_set_gpio_irqenable(bank, offset, 0);
- omap_clear_gpio_irqstatus(bank, offset);
omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
+ omap_clear_gpio_irqstatus(bank, offset);
+ omap_set_gpio_irqenable(bank, offset, 0);
if (!LINE_USED(bank->mod_usage, offset))
omap_clear_gpio_debounce(bank, offset);
omap_disable_gpio_module(bank, offset);
@@ -867,8 +867,8 @@ static void omap_gpio_mask_irq(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&bank->lock, flags);
- omap_set_gpio_irqenable(bank, offset, 0);
omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
+ omap_set_gpio_irqenable(bank, offset, 0);
raw_spin_unlock_irqrestore(&bank->lock, flags);
}
@@ -880,9 +880,6 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&bank->lock, flags);
- if (trigger)
- omap_set_gpio_triggering(bank, offset, trigger);
-
omap_set_gpio_irqenable(bank, offset, 1);
/*
@@ -890,9 +887,13 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
* is cleared, thus after the handler has run. OMAP4 needs this done
* after enabing the interrupt to clear the wakeup status.
*/
- if (bank->level_mask & BIT(offset))
+ if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
+ trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
omap_clear_gpio_irqstatus(bank, offset);
+ if (trigger)
+ omap_set_gpio_triggering(bank, offset, trigger);
+
raw_spin_unlock_irqrestore(&bank->lock, flags);
}
--
2.20.1
^ permalink raw reply related
* [PATCH AUTOSEL 5.2 179/249] gpio: Fix return value mismatch of function gpiod_get_from_of_node()
From: Sasha Levin @ 2019-07-15 13:45 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Waibel Georg, Georg Waibel, Krzysztof Kozlowski, Linus Walleij,
Mark Brown, Sasha Levin, linux-gpio, linux-samsung-soc
In-Reply-To: <20190715134655.4076-1-sashal@kernel.org>
From: Waibel Georg <Georg.Waibel@sensor-technik.de>
[ Upstream commit 025bf37725f1929542361eef2245df30badf242e ]
In case the requested gpio property is not found in the device tree, some
callers of gpiod_get_from_of_node() expect a return value of NULL, others
expect -ENOENT.
In particular devm_fwnode_get_index_gpiod_from_child() expects -ENOENT.
Currently it gets a NULL, which breaks the loop that tries all
gpio_suffixes. The result is that a gpio property is not found, even
though it is there.
This patch changes gpiod_get_from_of_node() to return -ENOENT instead
of NULL when the requested gpio property is not found in the device
tree. Additionally it modifies all calling functions to properly
evaluate the return value.
Another approach would be to leave the return value of
gpiod_get_from_of_node() as is and fix the bug in
devm_fwnode_get_index_gpiod_from_child(). Other callers would still need
to be reworked. The effort would be the same as with the chosen solution.
Signed-off-by: Georg Waibel <georg.waibel@sensor-technik.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpio/gpiolib.c | 6 +-----
drivers/regulator/da9211-regulator.c | 2 ++
drivers/regulator/s2mps11.c | 4 +++-
drivers/regulator/s5m8767.c | 4 +++-
drivers/regulator/tps65090-regulator.c | 7 ++++---
5 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index e013d417a936..be1d1d2f8aaa 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -4244,8 +4244,7 @@ EXPORT_SYMBOL_GPL(gpiod_get_index);
*
* Returns:
* On successful request the GPIO pin is configured in accordance with
- * provided @dflags. If the node does not have the requested GPIO
- * property, NULL is returned.
+ * provided @dflags.
*
* In case of error an ERR_PTR() is returned.
*/
@@ -4267,9 +4266,6 @@ struct gpio_desc *gpiod_get_from_of_node(struct device_node *node,
index, &flags);
if (!desc || IS_ERR(desc)) {
- /* If it is not there, just return NULL */
- if (PTR_ERR(desc) == -ENOENT)
- return NULL;
return desc;
}
diff --git a/drivers/regulator/da9211-regulator.c b/drivers/regulator/da9211-regulator.c
index da37b4ccd834..0309823d2c72 100644
--- a/drivers/regulator/da9211-regulator.c
+++ b/drivers/regulator/da9211-regulator.c
@@ -289,6 +289,8 @@ static struct da9211_pdata *da9211_parse_regulators_dt(
0,
GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
"da9211-enable");
+ if (IS_ERR(pdata->gpiod_ren[n]))
+ pdata->gpiod_ren[n] = NULL;
n++;
}
diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c
index 134c62db36c5..b518a81f75a3 100644
--- a/drivers/regulator/s2mps11.c
+++ b/drivers/regulator/s2mps11.c
@@ -821,7 +821,9 @@ static void s2mps14_pmic_dt_parse_ext_control_gpio(struct platform_device *pdev,
0,
GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
"s2mps11-regulator");
- if (IS_ERR(gpio[reg])) {
+ if (PTR_ERR(gpio[reg]) == -ENOENT)
+ gpio[reg] = NULL;
+ else if (IS_ERR(gpio[reg])) {
dev_err(&pdev->dev, "Failed to get control GPIO for %d/%s\n",
reg, rdata[reg].name);
continue;
diff --git a/drivers/regulator/s5m8767.c b/drivers/regulator/s5m8767.c
index bb9d1a083299..6ca27e9d5ef7 100644
--- a/drivers/regulator/s5m8767.c
+++ b/drivers/regulator/s5m8767.c
@@ -574,7 +574,9 @@ static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
0,
GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
"s5m8767");
- if (IS_ERR(rdata->ext_control_gpiod))
+ if (PTR_ERR(rdata->ext_control_gpiod) == -ENOENT)
+ rdata->ext_control_gpiod = NULL;
+ else if (IS_ERR(rdata->ext_control_gpiod))
return PTR_ERR(rdata->ext_control_gpiod);
rdata->id = i;
diff --git a/drivers/regulator/tps65090-regulator.c b/drivers/regulator/tps65090-regulator.c
index ca39b3d55123..10ea4b5a0f55 100644
--- a/drivers/regulator/tps65090-regulator.c
+++ b/drivers/regulator/tps65090-regulator.c
@@ -371,11 +371,12 @@ static struct tps65090_platform_data *tps65090_parse_dt_reg_data(
"dcdc-ext-control-gpios", 0,
gflags,
"tps65090");
- if (IS_ERR(rpdata->gpiod))
- return ERR_CAST(rpdata->gpiod);
- if (!rpdata->gpiod)
+ if (PTR_ERR(rpdata->gpiod) == -ENOENT) {
dev_err(&pdev->dev,
"could not find DCDC external control GPIO\n");
+ rpdata->gpiod = NULL;
+ } else if (IS_ERR(rpdata->gpiod))
+ return ERR_CAST(rpdata->gpiod);
}
if (of_property_read_u32(tps65090_matches[idx].of_node,
--
2.20.1
^ permalink raw reply related
* [PATCH AUTOSEL 5.2 228/249] gpiolib: Fix references to gpiod_[gs]et_*value_cansleep() variants
From: Sasha Levin @ 2019-07-15 13:46 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Geert Uytterhoeven, Linus Walleij, Sasha Levin, linux-gpio
In-Reply-To: <20190715134655.4076-1-sashal@kernel.org>
From: Geert Uytterhoeven <geert+renesas@glider.be>
[ Upstream commit 3285170f28a850638794cdfe712eb6d93e51e706 ]
Commit 372e722ea4dd4ca1 ("gpiolib: use descriptors internally") renamed
the functions to use a "gpiod" prefix, and commit 79a9becda8940deb
("gpiolib: export descriptor-based GPIO interface") introduced the "raw"
variants, but both changes forgot to update the comments.
Readd a similar reference to gpiod_set_value(), which was accidentally
removed by commit 1e77fc82110ac36f ("gpio: Add missing open drain/source
handling to gpiod_set_value_cansleep()").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190701142738.25219-1-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpio/gpiolib.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index be1d1d2f8aaa..bb3104d2eb0c 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -3025,7 +3025,7 @@ int gpiod_get_array_value_complex(bool raw, bool can_sleep,
int gpiod_get_raw_value(const struct gpio_desc *desc)
{
VALIDATE_DESC(desc);
- /* Should be using gpio_get_value_cansleep() */
+ /* Should be using gpiod_get_raw_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
return gpiod_get_raw_value_commit(desc);
}
@@ -3046,7 +3046,7 @@ int gpiod_get_value(const struct gpio_desc *desc)
int value;
VALIDATE_DESC(desc);
- /* Should be using gpio_get_value_cansleep() */
+ /* Should be using gpiod_get_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
value = gpiod_get_raw_value_commit(desc);
@@ -3317,7 +3317,7 @@ int gpiod_set_array_value_complex(bool raw, bool can_sleep,
void gpiod_set_raw_value(struct gpio_desc *desc, int value)
{
VALIDATE_DESC_VOID(desc);
- /* Should be using gpiod_set_value_cansleep() */
+ /* Should be using gpiod_set_raw_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
gpiod_set_raw_value_commit(desc, value);
}
@@ -3358,6 +3358,7 @@ static void gpiod_set_value_nocheck(struct gpio_desc *desc, int value)
void gpiod_set_value(struct gpio_desc *desc, int value)
{
VALIDATE_DESC_VOID(desc);
+ /* Should be using gpiod_set_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
gpiod_set_value_nocheck(desc, value);
}
--
2.20.1
^ permalink raw reply related
* [PATCH AUTOSEL 5.1 158/219] gpio: Fix return value mismatch of function gpiod_get_from_of_node()
From: Sasha Levin @ 2019-07-15 14:02 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Waibel Georg, Georg Waibel, Krzysztof Kozlowski, Linus Walleij,
Mark Brown, Sasha Levin, linux-gpio, linux-samsung-soc
In-Reply-To: <20190715140341.6443-1-sashal@kernel.org>
From: Waibel Georg <Georg.Waibel@sensor-technik.de>
[ Upstream commit 025bf37725f1929542361eef2245df30badf242e ]
In case the requested gpio property is not found in the device tree, some
callers of gpiod_get_from_of_node() expect a return value of NULL, others
expect -ENOENT.
In particular devm_fwnode_get_index_gpiod_from_child() expects -ENOENT.
Currently it gets a NULL, which breaks the loop that tries all
gpio_suffixes. The result is that a gpio property is not found, even
though it is there.
This patch changes gpiod_get_from_of_node() to return -ENOENT instead
of NULL when the requested gpio property is not found in the device
tree. Additionally it modifies all calling functions to properly
evaluate the return value.
Another approach would be to leave the return value of
gpiod_get_from_of_node() as is and fix the bug in
devm_fwnode_get_index_gpiod_from_child(). Other callers would still need
to be reworked. The effort would be the same as with the chosen solution.
Signed-off-by: Georg Waibel <georg.waibel@sensor-technik.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpio/gpiolib.c | 6 +-----
drivers/regulator/da9211-regulator.c | 2 ++
drivers/regulator/s2mps11.c | 4 +++-
drivers/regulator/s5m8767.c | 4 +++-
drivers/regulator/tps65090-regulator.c | 7 ++++---
5 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index bca3e7740ef6..fd1344056e1d 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -4232,8 +4232,7 @@ EXPORT_SYMBOL_GPL(gpiod_get_index);
*
* Returns:
* On successful request the GPIO pin is configured in accordance with
- * provided @dflags. If the node does not have the requested GPIO
- * property, NULL is returned.
+ * provided @dflags.
*
* In case of error an ERR_PTR() is returned.
*/
@@ -4255,9 +4254,6 @@ struct gpio_desc *gpiod_get_from_of_node(struct device_node *node,
index, &flags);
if (!desc || IS_ERR(desc)) {
- /* If it is not there, just return NULL */
- if (PTR_ERR(desc) == -ENOENT)
- return NULL;
return desc;
}
diff --git a/drivers/regulator/da9211-regulator.c b/drivers/regulator/da9211-regulator.c
index 4d7fe4819c1c..4e95e3d0fcd5 100644
--- a/drivers/regulator/da9211-regulator.c
+++ b/drivers/regulator/da9211-regulator.c
@@ -299,6 +299,8 @@ static struct da9211_pdata *da9211_parse_regulators_dt(
0,
GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
"da9211-enable");
+ if (IS_ERR(pdata->gpiod_ren[n]))
+ pdata->gpiod_ren[n] = NULL;
n++;
}
diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c
index 134c62db36c5..b518a81f75a3 100644
--- a/drivers/regulator/s2mps11.c
+++ b/drivers/regulator/s2mps11.c
@@ -821,7 +821,9 @@ static void s2mps14_pmic_dt_parse_ext_control_gpio(struct platform_device *pdev,
0,
GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
"s2mps11-regulator");
- if (IS_ERR(gpio[reg])) {
+ if (PTR_ERR(gpio[reg]) == -ENOENT)
+ gpio[reg] = NULL;
+ else if (IS_ERR(gpio[reg])) {
dev_err(&pdev->dev, "Failed to get control GPIO for %d/%s\n",
reg, rdata[reg].name);
continue;
diff --git a/drivers/regulator/s5m8767.c b/drivers/regulator/s5m8767.c
index bb9d1a083299..6ca27e9d5ef7 100644
--- a/drivers/regulator/s5m8767.c
+++ b/drivers/regulator/s5m8767.c
@@ -574,7 +574,9 @@ static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
0,
GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
"s5m8767");
- if (IS_ERR(rdata->ext_control_gpiod))
+ if (PTR_ERR(rdata->ext_control_gpiod) == -ENOENT)
+ rdata->ext_control_gpiod = NULL;
+ else if (IS_ERR(rdata->ext_control_gpiod))
return PTR_ERR(rdata->ext_control_gpiod);
rdata->id = i;
diff --git a/drivers/regulator/tps65090-regulator.c b/drivers/regulator/tps65090-regulator.c
index 0614551796a1..f6466db57900 100644
--- a/drivers/regulator/tps65090-regulator.c
+++ b/drivers/regulator/tps65090-regulator.c
@@ -381,11 +381,12 @@ static struct tps65090_platform_data *tps65090_parse_dt_reg_data(
"dcdc-ext-control-gpios", 0,
gflags,
"tps65090");
- if (IS_ERR(rpdata->gpiod))
- return ERR_CAST(rpdata->gpiod);
- if (!rpdata->gpiod)
+ if (PTR_ERR(rpdata->gpiod) == -ENOENT) {
dev_err(&pdev->dev,
"could not find DCDC external control GPIO\n");
+ rpdata->gpiod = NULL;
+ } else if (IS_ERR(rpdata->gpiod))
+ return ERR_CAST(rpdata->gpiod);
}
if (of_property_read_u32(tps65090_matches[idx].of_node,
--
2.20.1
^ permalink raw reply related
* [PATCH AUTOSEL 5.1 200/219] gpiolib: Fix references to gpiod_[gs]et_*value_cansleep() variants
From: Sasha Levin @ 2019-07-15 14:03 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Geert Uytterhoeven, Linus Walleij, Sasha Levin, linux-gpio
In-Reply-To: <20190715140341.6443-1-sashal@kernel.org>
From: Geert Uytterhoeven <geert+renesas@glider.be>
[ Upstream commit 3285170f28a850638794cdfe712eb6d93e51e706 ]
Commit 372e722ea4dd4ca1 ("gpiolib: use descriptors internally") renamed
the functions to use a "gpiod" prefix, and commit 79a9becda8940deb
("gpiolib: export descriptor-based GPIO interface") introduced the "raw"
variants, but both changes forgot to update the comments.
Readd a similar reference to gpiod_set_value(), which was accidentally
removed by commit 1e77fc82110ac36f ("gpio: Add missing open drain/source
handling to gpiod_set_value_cansleep()").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190701142738.25219-1-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpio/gpiolib.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index fd1344056e1d..b8a5c1e3b99d 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -3012,7 +3012,7 @@ int gpiod_get_array_value_complex(bool raw, bool can_sleep,
int gpiod_get_raw_value(const struct gpio_desc *desc)
{
VALIDATE_DESC(desc);
- /* Should be using gpio_get_value_cansleep() */
+ /* Should be using gpiod_get_raw_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
return gpiod_get_raw_value_commit(desc);
}
@@ -3033,7 +3033,7 @@ int gpiod_get_value(const struct gpio_desc *desc)
int value;
VALIDATE_DESC(desc);
- /* Should be using gpio_get_value_cansleep() */
+ /* Should be using gpiod_get_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
value = gpiod_get_raw_value_commit(desc);
@@ -3304,7 +3304,7 @@ int gpiod_set_array_value_complex(bool raw, bool can_sleep,
void gpiod_set_raw_value(struct gpio_desc *desc, int value)
{
VALIDATE_DESC_VOID(desc);
- /* Should be using gpiod_set_value_cansleep() */
+ /* Should be using gpiod_set_raw_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
gpiod_set_raw_value_commit(desc, value);
}
@@ -3345,6 +3345,7 @@ static void gpiod_set_value_nocheck(struct gpio_desc *desc, int value)
void gpiod_set_value(struct gpio_desc *desc, int value)
{
VALIDATE_DESC_VOID(desc);
+ /* Should be using gpiod_set_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
gpiod_set_value_nocheck(desc, value);
}
--
2.20.1
^ permalink raw reply related
* [PATCH AUTOSEL 4.19 060/158] gpio: omap: ensure irq is enabled before wakeup
From: Sasha Levin @ 2019-07-15 14:16 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Russell King, Grygorii Strashko, Tony Lindgren, Linus Walleij,
Sasha Levin, linux-omap, linux-gpio
In-Reply-To: <20190715141809.8445-1-sashal@kernel.org>
From: Russell King <rmk+kernel@armlinux.org.uk>
[ Upstream commit c859e0d479b3b4f6132fc12637c51e01492f31f6 ]
Documentation states:
NOTE: There must be a correlation between the wake-up enable and
interrupt-enable registers. If a GPIO pin has a wake-up configured
on it, it must also have the corresponding interrupt enabled (on
one of the two interrupt lines).
Ensure that this condition is always satisfied by enabling the detection
events after enabling the interrupt, and disabling the detection before
disabling the interrupt. This ensures interrupt/wakeup events can not
happen until both the wakeup and interrupt enables correlate.
If we do any clearing, clear between the interrupt enable/disable and
trigger setting.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpio/gpio-omap.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 9254bcf7f647..feabac40743e 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -837,9 +837,9 @@ static void omap_gpio_irq_shutdown(struct irq_data *d)
raw_spin_lock_irqsave(&bank->lock, flags);
bank->irq_usage &= ~(BIT(offset));
- omap_set_gpio_irqenable(bank, offset, 0);
- omap_clear_gpio_irqstatus(bank, offset);
omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
+ omap_clear_gpio_irqstatus(bank, offset);
+ omap_set_gpio_irqenable(bank, offset, 0);
if (!LINE_USED(bank->mod_usage, offset))
omap_clear_gpio_debounce(bank, offset);
omap_disable_gpio_module(bank, offset);
@@ -881,8 +881,8 @@ static void omap_gpio_mask_irq(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&bank->lock, flags);
- omap_set_gpio_irqenable(bank, offset, 0);
omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
+ omap_set_gpio_irqenable(bank, offset, 0);
raw_spin_unlock_irqrestore(&bank->lock, flags);
}
@@ -894,9 +894,6 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&bank->lock, flags);
- if (trigger)
- omap_set_gpio_triggering(bank, offset, trigger);
-
omap_set_gpio_irqenable(bank, offset, 1);
/*
@@ -904,9 +901,13 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
* is cleared, thus after the handler has run. OMAP4 needs this done
* after enabing the interrupt to clear the wakeup status.
*/
- if (bank->level_mask & BIT(offset))
+ if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
+ trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
omap_clear_gpio_irqstatus(bank, offset);
+ if (trigger)
+ omap_set_gpio_triggering(bank, offset, trigger);
+
raw_spin_unlock_irqrestore(&bank->lock, flags);
}
--
2.20.1
^ permalink raw reply related
* [PATCH AUTOSEL 4.19 144/158] gpiolib: Fix references to gpiod_[gs]et_*value_cansleep() variants
From: Sasha Levin @ 2019-07-15 14:17 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Geert Uytterhoeven, Linus Walleij, Sasha Levin, linux-gpio
In-Reply-To: <20190715141809.8445-1-sashal@kernel.org>
From: Geert Uytterhoeven <geert+renesas@glider.be>
[ Upstream commit 3285170f28a850638794cdfe712eb6d93e51e706 ]
Commit 372e722ea4dd4ca1 ("gpiolib: use descriptors internally") renamed
the functions to use a "gpiod" prefix, and commit 79a9becda8940deb
("gpiolib: export descriptor-based GPIO interface") introduced the "raw"
variants, but both changes forgot to update the comments.
Readd a similar reference to gpiod_set_value(), which was accidentally
removed by commit 1e77fc82110ac36f ("gpio: Add missing open drain/source
handling to gpiod_set_value_cansleep()").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190701142738.25219-1-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpio/gpiolib.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index fd713326dcfc..4a48c7c47709 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -2877,7 +2877,7 @@ int gpiod_get_array_value_complex(bool raw, bool can_sleep,
int gpiod_get_raw_value(const struct gpio_desc *desc)
{
VALIDATE_DESC(desc);
- /* Should be using gpio_get_value_cansleep() */
+ /* Should be using gpiod_get_raw_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
return gpiod_get_raw_value_commit(desc);
}
@@ -2898,7 +2898,7 @@ int gpiod_get_value(const struct gpio_desc *desc)
int value;
VALIDATE_DESC(desc);
- /* Should be using gpio_get_value_cansleep() */
+ /* Should be using gpiod_get_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
value = gpiod_get_raw_value_commit(desc);
@@ -3123,7 +3123,7 @@ int gpiod_set_array_value_complex(bool raw, bool can_sleep,
void gpiod_set_raw_value(struct gpio_desc *desc, int value)
{
VALIDATE_DESC_VOID(desc);
- /* Should be using gpiod_set_value_cansleep() */
+ /* Should be using gpiod_set_raw_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
gpiod_set_raw_value_commit(desc, value);
}
@@ -3164,6 +3164,7 @@ static void gpiod_set_value_nocheck(struct gpio_desc *desc, int value)
void gpiod_set_value(struct gpio_desc *desc, int value)
{
VALIDATE_DESC_VOID(desc);
+ /* Should be using gpiod_set_value_cansleep() */
WARN_ON(desc->gdev->chip->can_sleep);
gpiod_set_value_nocheck(desc, value);
}
--
2.20.1
^ permalink raw reply related
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