* Re: [PATCH 00/18] ARM: Add minimal Raspberry Pi 4 support
From: Nicolas Saenz Julienne @ 2019-07-25 8:22 UTC (permalink / raw)
To: Stefan Wahren, Christoph Hellwig
Cc: Eric Anholt, Florian Fainelli, Ray Jui, Scott Branden,
Matthias Brugger, Rob Herring, Mark Rutland, Linus Walleij,
Michael Turquette, Stephen Boyd, Ulf Hansson, Adrian Hunter,
bcm-kernel-feedback-list, linux-arm-kernel, linux-rpi-kernel,
linux-gpio, linux-mmc
In-Reply-To: <5f9b11f54c66fd0487837f7e58af3adf7f86635f.camel@suse.de>
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> > > Any thoughts on this?
> > >
> > > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> > > index 5e5f1fabc3d4..3db8deed83a6 100644
> > > --- a/arch/arm/mach-bcm/Kconfig
> > > +++ b/arch/arm/mach-bcm/Kconfig
> > > @@ -168,6 +168,7 @@ config ARCH_BCM2835
> > > select PINCTRL
> > > select PINCTRL_BCM2835
> > > select MFD_CORE
> > > + select DMABOUNCE
> > > help
> > > This enables support for the Broadcom BCM2835 and BCM2836 SoCs.
> > > This SoC is used in the Raspberry Pi and Roku 2 devices.
> > > diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-
> > > bcm/board_bcm2835.c
> > > index c09cf25596af..be788849c4bb 100644
> > > --- a/arch/arm/mach-bcm/board_bcm2835.c
> > > +++ b/arch/arm/mach-bcm/board_bcm2835.c
> > > @@ -3,6 +3,8 @@
> > > * Copyright (C) 2010 Broadcom
> > > */
> > >
> > > +#include <linux/device.h>
> > > +#include <linux/dma-mapping.h>
> > > #include <linux/init.h>
> > > #include <linux/irqchip.h>
> > > #include <linux/of_address.h>
> > > @@ -24,8 +26,37 @@ static const char * const bcm2835_compat[] = {
> > > NULL
> > > };
> > >
> > > +static int bcm2835_needs_bounce(struct device *dev, dma_addr_t dma_addr,
> > > size_t size)
> > > +{
> > > + /*
> > > + * The accepted dma addresses are [0xc0000000, 0xffffffff] which
> > > map
> > > to
> > > + * ram's [0x00000000, 0x3fffffff].
> > > + */
> > > + return dma_addr < 3ULL * SZ_1G;
> > > +}
> > > +
> > > +/*
> > > + * Setup DMA mask to 1GB on devices hanging from soc interconnect
> > > + */
> > > +static int bcm2835_platform_notify(struct device *dev)
> > > +{
> > > + if (dev->parent && !strcmp("soc", dev_name(dev->parent))) {
> > > + dev->dma_mask = &dev->coherent_dma_mask;
> > > + dev->coherent_dma_mask = DMA_BIT_MASK(30); /* 1GB */
> > Shouldn't this come from the device tree?
>
> Yes, actually I could use the 'dma-ranges' parsing code I suggested on the
> arm64 RFC. The same goes with 'dma_zone_size = SZ_1G', it ideally should be
> calculated based on the device-tree.
>
> The way I see it I'm not sure it's worth the effort, in arm64 we have no
> choice
> as there are no board files. But here we seem to be the only ones with this
> specific DMA addressing constraint, so fixing it in arm/common doesn't seem
> like it's going to benefit anyone else. Let's see how the arm arch maintainers
> react though.
>
> There is one catch though. I missed it earlier as I was excited to see the
> board boot, but some devices are failing to set their DMA masks:
>
> [ 1.989576] dwc2 fe980000.usb: can't set coherent DMA mask: -5
>
> It seems that other users of dmabounce also implement their own
> dma_supported(). I have to look into it.
Sadly it seems there are some limitations in dmabounce I didn't take into
account earlier. Among other things it can't deal with HighMem out of the box
and even when trying to adapt it to our needs, fails to do so as it allocates
using GFP_ATOMIC, which rules out using the CMA when allocating coherent
memory. Sorry for the noise, I got carried away too soon.
I did a dirty hack hooking up dma-direct/swiotlb to the board. It seems to be
working fine after some tweaks in arm's dma_capable(). That said I want to test
it further before sending anything ;).
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^ permalink raw reply
* Re: [PATCH V6 01/21] irqchip: tegra: Do not disable COP IRQ during suspend
From: Sowjanya Komatineni @ 2019-07-24 23:09 UTC (permalink / raw)
To: Dmitry Osipenko, Marc Zyngier
Cc: thierry.reding, jonathanh, tglx, jason, linus.walleij, stefan,
mark.rutland, pdeschrijver, pgaikwad, sboyd, linux-clk,
linux-gpio, jckuo, josephl, talho, linux-tegra, linux-kernel,
mperttunen, spatra, robh+dt, devicetree
In-Reply-To: <8e9f821c-3717-510d-c64f-8a1cc2452c25@gmail.com>
On 7/22/19 4:35 PM, Dmitry Osipenko wrote:
> 22.07.2019 21:38, Marc Zyngier пишет:
>> On Mon, 22 Jul 2019 09:21:21 -0700
>> Sowjanya Komatineni <skomatineni@nvidia.com> wrote:
>>
>>> On 7/22/19 3:57 AM, Dmitry Osipenko wrote:
>>>> 22.07.2019 13:13, Marc Zyngier пишет:
>>>>> On 22/07/2019 10:54, Dmitry Osipenko wrote:
>>>>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>>>>> Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry
>>>>>>> sequence and sc7 entry firmware is run from COP/BPMP-Lite.
>>>>>>>
>>>>>>> So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence
>>>>>>> for Tegra210.
>>>>>>>
>>>>>>> This patch has fix for leaving the COP IRQ enabled for Tegra210 during
>>>>>>> interrupt controller suspend operation.
>>>>>>>
>>>>>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>> ---
>>>>>>> drivers/irqchip/irq-tegra.c | 20 ++++++++++++++++++--
>>>>>>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>>>>>>
>>>>>>> diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
>>>>>>> index e1f771c72fc4..851f88cef508 100644
>>>>>>> --- a/drivers/irqchip/irq-tegra.c
>>>>>>> +++ b/drivers/irqchip/irq-tegra.c
>>>>>>> @@ -44,6 +44,7 @@ static unsigned int num_ictlrs;
>>>>>>>
>>>>>>> struct tegra_ictlr_soc {
>>>>>>> unsigned int num_ictlrs;
>>>>>>> + bool supports_sc7;
>>>>>>> };
>>>>>>>
>>>>>>> static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
>>>>>>> @@ -56,6 +57,7 @@ static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
>>>>>>>
>>>>>>> static const struct tegra_ictlr_soc tegra210_ictlr_soc = {
>>>>>>> .num_ictlrs = 6,
>>>>>>> + .supports_sc7 = true,
>>>>>>> };
>>>>>>>
>>>>>>> static const struct of_device_id ictlr_matches[] = {
>>>>>>> @@ -67,6 +69,7 @@ static const struct of_device_id ictlr_matches[] = {
>>>>>>>
>>>>>>> struct tegra_ictlr_info {
>>>>>>> void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
>>>>>>> + const struct tegra_ictlr_soc *soc;
>>>>>>> #ifdef CONFIG_PM_SLEEP
>>>>>>> u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
>>>>>>> u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
>>>>>>> @@ -147,8 +150,20 @@ static int tegra_ictlr_suspend(void)
>>>>>>> lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
>>>>>>> lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
>>>>>>>
>>>>>>> - /* Disable COP interrupts */
>>>>>>> - writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
>>>>>>> + /*
>>>>>>> + * AVP/COP/BPMP-Lite is the Tegra boot processor.
>>>>>>> + *
>>>>>>> + * Tegra210 system suspend flow uses sc7entry firmware which
>>>>>>> + * is executed by COP/BPMP and it includes disabling COP IRQ,
>>>>>>> + * clamping CPU rail, turning off VDD_CPU, and preparing the
>>>>>>> + * system to go to SC7/LP0.
>>>>>>> + *
>>>>>>> + * COP/BPMP wakes up when COP IRQ is triggered and runs
>>>>>>> + * sc7entry-firmware. So need to keep COP interrupt enabled.
>>>>>>> + */
>>>>>>> + if (!lic->soc->supports_sc7)
>>>>>>> + /* Disable COP interrupts if SC7 is not supported */
>>>>>> All Tegra SoCs support SC7, hence the 'supports_sc7' and the comment
>>>>>> doesn't sound correct to me. Something like 'firmware_sc7' should suit
>>>>>> better here.
>>>>> If what you're saying is true, then the whole patch is wrong, and the
>>>>> SC7 property should come from DT.
>>>> It should be safe to assume that all of existing Tegra210 devices use
>>>> the firmware for SC7, hence I wouldn't say that the patch is entirely
>>>> wrong. To me it's not entirely correct.
>>> Yes, all existing Tegra210 platforms uses sc7 entry firmware for SC7 and
>>> AVP/COP IRQ need to be kept enabled as during suspend ATF triggers IRQ
>>> to COP for SC7 entry fw execution.
> Okay, as I already wrote before, it looks to me that a more proper
> solution should be to just remove everything related to COP from this
> driver instead of adding custom quirks for T210.
>
> The disabling / restoring of COP interrupts should be relevant only for
> the multimedia firmware on older Tegra SoCs. That firmware won't be ever
> supported in the upstream simply because NVIDIA abandoned the support
> for older hardware in the downstream and because it is not possible due
> to some legal weirdness (IIUC). The only variant for upstream is
> reverse-engineering of hardware (not the firmware BLOB) and writing
> proper opensource drivers for the upstream kernel, which we're already
> doing and have success to a some extent.
>
>> That's not the question. Dmitry says that the SC7 support is not a
>> property of the SoC, but mostly a platform decision on whether the
>> firmware supports SC7 or not.
>>
>> To me, that's a clear indication that this should not be hardcoded in
>> the driver, but instead obtained dynamically, via DT or otherwise.
> We already have an nvidia,suspend-mode property in the device-tree of
> the Power Management Controller node (all Tegra SoCs) which defines what
> suspending type is supported by a particular board.
>
>>>>>>> + writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
>>>>>> Secondly, I'm also not sure why COP interrupts need to be disabled for
>>>>>> pre-T210 at all, since COP is unused. This looks to me like it was
>>>>>> cut-n-pasted from downstream kernel without a good reason and could be
>>>>>> simply removed.
>>>>> Please verify that this is actually the case. Tegra-2 definitely needed
>>>>> some level of poking, and I'm not keen on changing anything there until
>>>>> you (or someone else) has verified it on actual HW (see e307cc8941fc).
>>>> Tested on Tegra20 and Tegra30, LP1 suspend-resume works perfectly fine
>>>> with all COP bits removed from the driver.
>>>>
>>>> AFAIK, the reason why downstream needed that disabling is that it uses
>>>> proprietary firmware which is running on the COP and that firmware is
>>>> usually a BLOB audio/video DEC-ENC driver which doesn't cleanup
>>>> interrupts after itself. That firmware is not applicable for the
>>>> upstream kernel, hence there is no need to care about it.
>>>>
>>>>> Joseph, can you please shed some light here?
>>> SC7 entry flow uses 3rd party ATF (arm-trusted FW) blob which is the
>>> one that actually loads SC7 entry firmware and triggers IRQ to
>>> AVP/COP which causes COP to wakeup and run SC7 entry FW.
>>>
>>> So when SC7 support is enabled, IRQ need to be kept enabled and when
>>> SC7 FW starts execution, it will disable COP IRQ.
>> This looks like a lot of undocumented assumptions on what firmware
>> does, as well as what firmware *is*. What I gather from this thread is
>> that there is at least two versions of firmware (a "proprietary
>> firmware" for "downstream kernels", and another one for mainline), and
>> that they do different things.
>>
>> Given that we cannot know what people actually run, I don't think we
>> can safely remove anything unless this gets tested on the full spectrum
>> of HW/FW combination.
> I'm not sure whether multiple firmware variations exist in the wild for
> Tegra210. Maybe Sowjanya or somebody else from NVIDIA could clarify. I
> think there should be some efforts in regards to a fully opensource
> firmware on Tegra210, but I'm not following it and have no idea about
> the status.
>
> You're right that there are multiple variants of suspend-resuming flow
> on Tegra SoCs. The older 32bit Tegra SoC generations have a variety of
> options in regards to suspend-resuming, including firmware-less variants
> on platforms that are having kernel running in secure mode (dev boards,
> most of Tegra20 consumer devices) and Trusted-Foundations firmware
> variant for insecure platforms (consumer devices). And yes, vendor
> firmware creates a lot of headache in regards to bringing support into
> upstream because it usually does a lot of odd undocumented things which
> may also vary depending on a firmware version (bootloader, etc) and it
> also usually difficult to replace it with an opensource alternative due
> to a crypto signing.
Tried without this patch which keeps COP IRQ disabled and I see SC7
entry FW execution happens still.
Digging through the ATF FW code, I see on SC7 entry firmware loading
into IRAM, COP processor is reset with RESET VECTOR set to SC7 entry
firmware location in IRAM and on reset de-assert & unhalt COP, SC7
firmware starts execution.
Will remove this patch in next version...
^ permalink raw reply
* Re: [PATCH] pinctrl: qcom: Pass irqchip when adding gpiochip
From: Bjorn Andersson @ 2019-07-24 20:00 UTC (permalink / raw)
To: Linus Walleij, Lina Iyer; +Cc: linux-gpio, Thierry Reding
In-Reply-To: <20190724083828.7496-1-linus.walleij@linaro.org>
On Wed 24 Jul 01:38 PDT 2019, Linus Walleij wrote:
> We need to convert all old gpio irqchips to pass the irqchip
> setup along when adding the gpio_chip.
Could you please elaborate on why we have this need?
>
> For chained irqchips this is a pretty straight-forward
> conversion.
>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> drivers/pinctrl/qcom/pinctrl-msm.c | 27 +++++++++++++--------------
> 1 file changed, 13 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 7f35c196bb3e..73062e329f6f 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -1002,6 +1002,7 @@ static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
> static int msm_gpio_init(struct msm_pinctrl *pctrl)
> {
> struct gpio_chip *chip;
> + struct gpio_irq_chip *girq;
> int ret;
> unsigned ngpio = pctrl->soc->ngpios;
>
> @@ -1027,6 +1028,18 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
> pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
> pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
>
> + girq = &chip->irq;
> + girq->chip = &pctrl->irq_chip;
> + girq->parent_handler = msm_gpio_irq_handler;
> + girq->num_parents = 1;
> + girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
> + GFP_KERNEL);
> + if (!girq->parents)
> + return -ENOMEM;
> + girq->default_type = IRQ_TYPE_NONE;
> + girq->handler = handle_bad_irq;
It's been a while since i poked at this, but I think it's fine to change
this from handle_edge_irq to handle_bad_irq.
So this change does looks like a nice cleanup to me, but adding Lina wrt
her PDC integration patch series.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> + girq->parents[0] = pctrl->irq;
> +
> ret = gpiochip_add_data(&pctrl->chip, pctrl);
> if (ret) {
> dev_err(pctrl->dev, "Failed register gpiochip\n");
> @@ -1053,20 +1066,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
> }
> }
>
> - ret = gpiochip_irqchip_add(chip,
> - &pctrl->irq_chip,
> - 0,
> - handle_edge_irq,
> - IRQ_TYPE_NONE);
> - if (ret) {
> - dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
> - gpiochip_remove(&pctrl->chip);
> - return -ENOSYS;
> - }
> -
> - gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
> - msm_gpio_irq_handler);
> -
> return 0;
> }
>
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH 01/18] ARM: bcm283x: Reduce register ranges for UART, SPI and I2C
From: Stefan Wahren @ 2019-07-24 20:01 UTC (permalink / raw)
To: Eric Anholt, Florian Fainelli, Ray Jui, Scott Branden,
Nicolas Saenz Julienne, Matthias Brugger, Rob Herring,
Mark Rutland, Linus Walleij, Michael Turquette, Stephen Boyd,
Ulf Hansson, Adrian Hunter
Cc: bcm-kernel-feedback-list, linux-arm-kernel, linux-rpi-kernel,
linux-gpio, linux-mmc
In-Reply-To: <1563774880-8061-2-git-send-email-wahrenst@gmx.net>
Am 22.07.19 um 07:54 schrieb Stefan Wahren:
> The assigned register ranges for UART, SPI and I2C were too wasteful.
> In order to avoid overlapping with the new functions on BCM2711
> reduce the ranges.
>
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Applied to bcm2835-dt-next including Eric's Ack
^ permalink raw reply
* Re: [PATCH 10/18] mmc: sdhci-iproc: Add support for emmc2 of the BCM2711
From: Ulf Hansson @ 2019-07-24 14:08 UTC (permalink / raw)
To: Stefan Wahren
Cc: Eric Anholt, Florian Fainelli, Ray Jui, Scott Branden,
Nicolas Saenz Julienne, Matthias Brugger, Rob Herring,
Mark Rutland, Linus Walleij, Michael Turquette, Stephen Boyd,
Adrian Hunter, BCM Kernel Feedback, Linux ARM, linux-rpi-kernel,
open list:GPIO SUBSYSTEM, linux-mmc@vger.kernel.org
In-Reply-To: <1563776607-8368-1-git-send-email-wahrenst@gmx.net>
On Mon, 22 Jul 2019 at 08:24, Stefan Wahren <wahrenst@gmx.net> wrote:
>
> The additional emmc2 interface of the BCM2711 is an improved version
> of the old emmc controller, which is able to provide DDR50 mode on the
> Raspberry Pi 4. Except 32 bit only register access no other quirks are
> known yet.
>
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-iproc.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-iproc.c b/drivers/mmc/host/sdhci-iproc.c
> index 2feb4ef..2b9cdcd 100644
> --- a/drivers/mmc/host/sdhci-iproc.c
> +++ b/drivers/mmc/host/sdhci-iproc.c
> @@ -261,8 +261,17 @@ static const struct sdhci_iproc_data bcm2835_data = {
> .mmc_caps = 0x00000000,
> };
>
> +static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
> + .ops = &sdhci_iproc_32only_ops,
> +};
> +
> +static const struct sdhci_iproc_data bcm2711_data = {
> + .pdata = &sdhci_bcm2711_pltfm_data,
> +};
> +
> static const struct of_device_id sdhci_iproc_of_match[] = {
> { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
> + { .compatible = "brcm,bcm2711-emmc2", .data = &bcm2711_data },
> { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
> { .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
> { }
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH 09/18] dt-bindings: sdhci-iproc: Add brcm,bcm2711-emmc2
From: Ulf Hansson @ 2019-07-24 14:08 UTC (permalink / raw)
To: Stefan Wahren
Cc: Eric Anholt, Florian Fainelli, Ray Jui, Scott Branden,
Nicolas Saenz Julienne, Matthias Brugger, Rob Herring,
Mark Rutland, Linus Walleij, Michael Turquette, Stephen Boyd,
Adrian Hunter, BCM Kernel Feedback, Linux ARM, linux-rpi-kernel,
open list:GPIO SUBSYSTEM, linux-mmc@vger.kernel.org
In-Reply-To: <1563774880-8061-10-git-send-email-wahrenst@gmx.net>
On Mon, 22 Jul 2019 at 07:56, Stefan Wahren <wahrenst@gmx.net> wrote:
>
> Add a new compatible for the additional emmc2 controller
> on BCM2711 and clearify usage.
>
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
> index fa90d25..09d87cc 100644
> --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
> +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
> @@ -6,10 +6,12 @@ by mmc.txt and the properties that represent the IPROC SDHCI controller.
> Required properties:
> - compatible : Should be one of the following
> "brcm,bcm2835-sdhci"
> + "brcm,bcm2711-emmc2"
> "brcm,sdhci-iproc-cygnus"
> "brcm,sdhci-iproc"
>
> -Use brcm2835-sdhci for Rasperry PI.
> +Use brcm2835-sdhci for the eMMC controller on the BCM2835 (Raspberry Pi) and
> +bcm2711-emmc2 for the additional eMMC2 controller on BCM2711.
>
> Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers
> restricted to 32bit host accesses to SDHCI registers.
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH 3/3] dt-bindings: aspeed: Remove mention of deprecated compatibles
From: Rob Herring @ 2019-07-24 13:40 UTC (permalink / raw)
To: Andrew Jeffery
Cc: linux-aspeed, Lee Jones, Mark Rutland, Joel Stanley,
Linus Walleij, devicetree,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel@vger.kernel.org, open list:GPIO SUBSYSTEM
In-Reply-To: <20190724081313.12934-4-andrew@aj.id.au>
On Wed, Jul 24, 2019 at 2:13 AM Andrew Jeffery <andrew@aj.id.au> wrote:
>
> Guide readers away from using the aspeed,g[45].* compatible patterns.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> Documentation/devicetree/bindings/mfd/aspeed-scu.txt | 2 --
> Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt | 2 --
> .../devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml | 5 +----
> .../devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml | 4 +---
> 4 files changed, 2 insertions(+), 11 deletions(-)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board
From: Icenowy Zheng @ 2019-07-24 13:09 UTC (permalink / raw)
To: Maxime Ripard
Cc: devicetree, Linus Walleij, linux-kernel, linux-gpio, linux-sunxi,
Rob Herring, Chen-Yu Tsai, linux-clk, linux-arm-kernel
In-Reply-To: <20190722192934.3jaf3r4rnyeslqyw@flea>
在 2019-07-23 03:29,Maxime Ripard 写道:
> On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard
>> <maxime.ripard@bootlin.com> 写到:
>> >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote:
>> >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
>> >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI
>> >Flash.
>> >> It has a gold finger connector for expansion, and UART is available
>> >from
>> >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or
>> >> Allwinner V3L SoCs.
>> >>
>> >> Add the device tree binding of the basic version of the core board --
>> >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
>> >>
>> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> >> ---
>> >> No changes since v3.
>> >>
>> >> Patch introduced in v2.
>> >>
>> >> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
>> >> 1 file changed, 5 insertions(+)
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml
>> >b/Documentation/devicetree/bindings/arm/sunxi.yaml
>> >> index 000a00d12d6a..48c126a7a848 100644
>> >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
>> >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
>> >> @@ -353,6 +353,11 @@ properties:
>> >> - const: licheepi,licheepi-zero
>> >> - const: allwinner,sun8i-v3s
>> >>
>> >> + - description: Lichee Zero Plus (with S3, without eMMC/SPI
>> >Flash)
>> >> + items:
>> >> + - const: sipeed,lichee-zero-plus
>> >> + - const: allwinner,sun8i-s3
>> >
>> >If the S3 is just a rebranded V3, then we should have the v3 compatile
>> >in that list too.
>>
>> S3 is V3 with copackaged DDR3 DRAM.
>>
>> It's pin incompatible w/ V3.
>
> Does it matter though?
>
> If the only thing that changes is the package, we're not manipulating
> that, and any software that deals with the v3 can deal with the
> s3. Which is what the compatible is about.
Okay. Should the S3 compatible be kept befoer the V3 one?
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] extcon: fsa9480: Support the FSA880 variant
From: Chanwoo Choi @ 2019-07-24 10:12 UTC (permalink / raw)
To: Linus Walleij, MyungJoo Ham
Cc: linux-kernel, linux-gpio, Mike Lockwood, devicetree,
cpgs (cpgs@samsung.com)
In-Reply-To: <20190723174301.31278-1-linus.walleij@linaro.org>
On 19. 7. 24. 오전 2:43, Linus Walleij wrote:
> The older compatible variant of this chip is called FSA880
> and works the same way, if we need some quirks in the future,
> it is good to let it have its own compatible string.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt | 4 +++-
> drivers/extcon/extcon-fsa9480.c | 1 +
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt b/Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt
> index d592c21245f2..624bd76f468e 100644
> --- a/Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt
> +++ b/Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt
> @@ -5,7 +5,9 @@ controlled using I2C and enables USB data, stereo and mono audio, video,
> microphone, and UART data to use a common connector port.
>
> Required properties:
> - - compatible : Must be "fcs,fsa9480"
> + - compatible : Must be one of
> + "fcs,fsa9480"
> + "fcs,fsa880"
> - reg : Specifies i2c slave address. Must be 0x25.
> - interrupts : Should contain one entry specifying interrupt signal of
> interrupt parent to which interrupt pin of the chip is connected.
> diff --git a/drivers/extcon/extcon-fsa9480.c b/drivers/extcon/extcon-fsa9480.c
> index 350fb34abfa0..8405512f5199 100644
> --- a/drivers/extcon/extcon-fsa9480.c
> +++ b/drivers/extcon/extcon-fsa9480.c
> @@ -363,6 +363,7 @@ MODULE_DEVICE_TABLE(i2c, fsa9480_id);
>
> static const struct of_device_id fsa9480_of_match[] = {
> { .compatible = "fcs,fsa9480", },
> + { .compatible = "fcs,fsa880", },
> { },
> };
> MODULE_DEVICE_TABLE(of, fsa9480_of_match);
>
Applied it. Thanks.
--
Best Regards,
Chanwoo Choi
Samsung Electronics
^ permalink raw reply
* Re: [PATCH V6 16/21] soc/tegra: pmc: Add pmc wake support for tegra210
From: Dmitry Osipenko @ 2019-07-24 9:31 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <6fefa6cc-f762-d473-a0ce-248d352a9a53@nvidia.com>
24.07.2019 2:39, Sowjanya Komatineni пишет:
>
> On 7/23/19 7:27 AM, Dmitry Osipenko wrote:
>> 23.07.2019 6:43, Dmitry Osipenko пишет:
>>> 23.07.2019 6:31, Sowjanya Komatineni пишет:
>>>> On 7/22/19 8:25 PM, Dmitry Osipenko wrote:
>>>>> 23.07.2019 6:09, Sowjanya Komatineni пишет:
>>>>>> On 7/22/19 8:03 PM, Dmitry Osipenko wrote:
>>>>>>> 23.07.2019 4:52, Sowjanya Komatineni пишет:
>>>>>>>> On 7/22/19 6:41 PM, Dmitry Osipenko wrote:
>>>>>>>>> 23.07.2019 4:08, Dmitry Osipenko пишет:
>>>>>>>>>> 23.07.2019 3:58, Dmitry Osipenko пишет:
>>>>>>>>>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>>>>>>>>>> This patch implements PMC wakeup sequence for Tegra210 and
>>>>>>>>>>>> defines
>>>>>>>>>>>> common used RTC alarm wake event.
>>>>>>>>>>>>
>>>>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>>>>> ---
>>>>>>>>>>>> drivers/soc/tegra/pmc.c | 111
>>>>>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>>>> 1 file changed, 111 insertions(+)
>>>>>>>>>>>>
>>>>>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>>>>>>> index 91c84d0e66ae..c556f38874e1 100644
>>>>>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>>>>>> @@ -57,6 +57,12 @@
>>>>>>>>>>>> #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock
>>>>>>>>>>>> enable */
>>>>>>>>>>>> #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk
>>>>>>>>>>>> polarity */
>>>>>>>>>>>> #define PMC_CNTRL_MAIN_RST BIT(4)
>>>>>>>>>>>> +#define PMC_CNTRL_LATCH_WAKEUPS BIT(5)
>>>>>>>>>> Please follow the TRM's bits naming.
>>>>>>>>>>
>>>>>>>>>> PMC_CNTRL_LATCHWAKE_EN
>>>>>>>>>>
>>>>>>>>>>>> +#define PMC_WAKE_MASK 0x0c
>>>>>>>>>>>> +#define PMC_WAKE_LEVEL 0x10
>>>>>>>>>>>> +#define PMC_WAKE_STATUS 0x14
>>>>>>>>>>>> +#define PMC_SW_WAKE_STATUS 0x18
>>>>>>>>>>>> #define DPD_SAMPLE 0x020
>>>>>>>>>>>> #define DPD_SAMPLE_ENABLE BIT(0)
>>>>>>>>>>>> @@ -87,6 +93,11 @@
>>>>>>>>>>>> #define PMC_SCRATCH41 0x140
>>>>>>>>>>>> +#define PMC_WAKE2_MASK 0x160
>>>>>>>>>>>> +#define PMC_WAKE2_LEVEL 0x164
>>>>>>>>>>>> +#define PMC_WAKE2_STATUS 0x168
>>>>>>>>>>>> +#define PMC_SW_WAKE2_STATUS 0x16c
>>>>>>>>>>>> +
>>>>>>>>>>>> #define PMC_SENSOR_CTRL 0x1b0
>>>>>>>>>>>> #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
>>>>>>>>>>>> #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
>>>>>>>>>>>> @@ -1922,6 +1933,55 @@ static const struct irq_domain_ops
>>>>>>>>>>>> tegra_pmc_irq_domain_ops = {
>>>>>>>>>>>> .alloc = tegra_pmc_irq_alloc,
>>>>>>>>>>>> };
>>>>>>>>>>>> +static int tegra210_pmc_irq_set_wake(struct irq_data
>>>>>>>>>>>> *data,
>>>>>>>>>>>> unsigned int on)
>>>>>>>>>>>> +{
>>>>>>>>>>>> + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
>>>>>>>>>>>> + unsigned int offset, bit;
>>>>>>>>>>>> + u32 value;
>>>>>>>>>>>> +
>>>>>>>>>>>> + if (data->hwirq == ULONG_MAX)
>>>>>>>>>>>> + return 0;
>>>>>>>>>>>> +
>>>>>>>>>>>> + offset = data->hwirq / 32;
>>>>>>>>>>>> + bit = data->hwirq % 32;
>>>>>>>>>>>> +
>>>>>>>>>>>> + /*
>>>>>>>>>>>> + * Latch wakeups to SW_WAKE_STATUS register to capture
>>>>>>>>>>>> events
>>>>>>>>>>>> + * that would not make it into wakeup event register
>>>>>>>>>>>> during
>>>>>>>>>>>> LP0 exit.
>>>>>>>>>>>> + */
>>>>>>>>>>>> + value = tegra_pmc_readl(pmc, PMC_CNTRL);
>>>>>>>>>>>> + value |= PMC_CNTRL_LATCH_WAKEUPS;
>>>>>>>>>>>> + tegra_pmc_writel(pmc, value, PMC_CNTRL);
>>>>>>>>>>>> + udelay(120);
>>>>>>>>>>> Why it takes so much time to latch the values? Shouldn't some
>>>>>>>>>>> status-bit
>>>>>>>>>>> be polled for the completion of latching?
>>>>>>>>>>>
>>>>>>>>>>> Is this register-write really getting buffered in the PMC?
>>>>>>>>>>>
>>>>>>>>>>>> + value &= ~PMC_CNTRL_LATCH_WAKEUPS;
>>>>>>>>>>>> + tegra_pmc_writel(pmc, value, PMC_CNTRL);
>>>>>>>>>>>> + udelay(120);
>>>>>>>>>>> 120 usecs to remove latching, really?
>>>>>>>>>>>
>>>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
>>>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
>>>>>>>>>>>> +
>>>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
>>>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
>>>>>>>>>>>> +
>>>>>>>>>>>> + /* enable PMC wake */
>>>>>>>>>>>> + if (data->hwirq >= 32)
>>>>>>>>>>>> + offset = PMC_WAKE2_MASK;
>>>>>>>>>>>> + else
>>>>>>>>>>>> + offset = PMC_WAKE_MASK;
>>>>>>>>>>>> +
>>>>>>>>>>>> + value = tegra_pmc_readl(pmc, offset);
>>>>>>>>>>>> +
>>>>>>>>>>>> + if (on)
>>>>>>>>>>>> + value |= 1 << bit;
>>>>>>>>>>>> + else
>>>>>>>>>>>> + value &= ~(1 << bit);
>>>>>>>>>>>> +
>>>>>>>>>>>> + tegra_pmc_writel(pmc, value, offset);
>>>>>>>>>>> Why the latching is done *before* writing into the WAKE
>>>>>>>>>>> registers?
>>>>>>>>>>> What
>>>>>>>>>>> it is latching then?
>>>>>>>>>> I'm looking at the TRM doc and it says that latching should be
>>>>>>>>>> done
>>>>>>>>>> *after* writing to the WAKE_MASK / LEVEL registers.
>>>>>>>>>>
>>>>>>>>>> Secondly it says that it's enough to do:
>>>>>>>>>>
>>>>>>>>>> value = tegra_pmc_readl(pmc, PMC_CNTRL);
>>>>>>>>>> value |= PMC_CNTRL_LATCH_WAKEUPS;
>>>>>>>>>> tegra_pmc_writel(pmc, value, PMC_CNTRL);
>>>>>>>>>>
>>>>>>>>>> in order to latch. There is no need for the delay and to
>>>>>>>>>> remove the
>>>>>>>>>> "LATCHWAKE_EN" bit, it should be a oneshot action.
>>>>>>>>> Although, no. TRM says "stops latching on transition from 1
>>>>>>>>> to 0 (sequence - set to 1,set to 0)", so it's not a oneshot
>>>>>>>>> action.
>>>>>>>>>
>>>>>>>>> Have you tested this code at all? I'm wondering how it happens to
>>>>>>>>> work
>>>>>>>>> without a proper latching.
>>>>>>>> Yes, ofcourse its tested and this sequence to do transition is
>>>>>>>> recommendation from Tegra designer.
>>>>>>>> Will check if TRM doesn't have update properly or will re-confirm
>>>>>>>> internally on delay time...
>>>>>>>>
>>>>>>>> On any of the wake event PMC wakeup happens and WAKE_STATUS
>>>>>>>> register
>>>>>>>> will have bits set for all events that triggered wake.
>>>>>>>> After wakeup PMC doesn't update SW_WAKE_STATUS register as per PMC
>>>>>>>> design.
>>>>>>>> SW latch register added in design helps to provide a way to capture
>>>>>>>> those events that happen right during wakeup time and didnt make
>>>>>>>> it to
>>>>>>>> SW_WAKE_STATUS register.
>>>>>>>> So before next suspend entry, latching all prior wake events
>>>>>>>> into SW
>>>>>>>> WAKE_STATUS and then clearing them.
>>>>>>> I'm now wondering whether the latching cold be turned ON permanently
>>>>>>> during of the PMC's probe, for simplicity.
>>>>>> latching should be done on suspend-resume cycle as wake events gets
>>>>>> generates on every suspend-resume cycle.
>>>>> You're saying that PMC "doesn't update SW_WAKE_STATUS" after wake-up,
>>>>> then I don't quite understand what's the point of disabling the
>>>>> latching
>>>>> at all.
>>>> When latch wake enable is set, events are latched and during 1 to 0
>>>> transition latching is disabled.
>>>>
>>>> This is to avoid sw_wake_status and wake_status showing diff events.
>>> Okay.
>>>
>>>> Currently driver is not relying on SW_WAKE_STATUS but its good to latch
>>>> and clear so even at some point for some reason when SW_WAKE_STATUS is
>>>> used, this wlil not cause mismatch with wake_status.
>>> Then the latching need to be enabled on suspend and disabled early on
>>> resume to get a proper WAKE status.
>> Actually, it will be better to simply not implement the latching until
>> it will become really needed. In general you shouldn't add into the
>> patchset anything that is unused.
>
> OK, will remove latch_wake for now.
>
> Will send next version once I get all the review feedback ..
>
That's not a bad idea. Wait for one-two weeks and if it will happen that
nobody is replying, then just issue a new version.
^ permalink raw reply
* [PATCH] pinctrl: qcom: Pass irqchip when adding gpiochip
From: Linus Walleij @ 2019-07-24 8:38 UTC (permalink / raw)
To: linux-gpio; +Cc: Linus Walleij, Bjorn Andersson, Thierry Reding
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip.
For chained irqchips this is a pretty straight-forward
conversion.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/qcom/pinctrl-msm.c | 27 +++++++++++++--------------
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 7f35c196bb3e..73062e329f6f 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -1002,6 +1002,7 @@ static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
static int msm_gpio_init(struct msm_pinctrl *pctrl)
{
struct gpio_chip *chip;
+ struct gpio_irq_chip *girq;
int ret;
unsigned ngpio = pctrl->soc->ngpios;
@@ -1027,6 +1028,18 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
+ girq = &chip->irq;
+ girq->chip = &pctrl->irq_chip;
+ girq->parent_handler = msm_gpio_irq_handler;
+ girq->num_parents = 1;
+ girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
+ GFP_KERNEL);
+ if (!girq->parents)
+ return -ENOMEM;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_bad_irq;
+ girq->parents[0] = pctrl->irq;
+
ret = gpiochip_add_data(&pctrl->chip, pctrl);
if (ret) {
dev_err(pctrl->dev, "Failed register gpiochip\n");
@@ -1053,20 +1066,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
}
}
- ret = gpiochip_irqchip_add(chip,
- &pctrl->irq_chip,
- 0,
- handle_edge_irq,
- IRQ_TYPE_NONE);
- if (ret) {
- dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
- gpiochip_remove(&pctrl->chip);
- return -ENOSYS;
- }
-
- gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
- msm_gpio_irq_handler);
-
return 0;
}
--
2.21.0
^ permalink raw reply related
* Re: [PATCH 00/18] ARM: Add minimal Raspberry Pi 4 support
From: Nicolas Saenz Julienne @ 2019-07-24 8:37 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Mark Rutland, Ulf Hansson, Florian Fainelli, Scott Branden,
open list:GPIO SUBSYSTEM, Stephen Boyd, Ray Jui, Linus Walleij,
linux-mmc, Adrian Hunter, Rob Herring, Eric Anholt,
Matthias Brugger, open list:BROADCOM BCM281XX..., Stefan Wahren,
Michael Turquette, Christoph Hellwig, linux-arm-kernel,
moderated list:BROADCOM BCM2835...
In-Reply-To: <CAGb2v66-o23CW5iH9Bn1aELymPSiKrA43eJd2q6EZ7iubcogaw@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 909 bytes --]
> > > Does it fix the wifi issue too?
> >
> > Well it works as long as I revert this: 901bb98918 ("nl80211: require and
> > validate vendor command policy"). Which has nothing to do with DMA anyways.
> >
> > Was this the issue you where seeing?
> >
> > [ 4.969679] WARNING: CPU: 2 PID: 21 at net/wireless/core.c:868
> > wiphy_register+0x8e8/0xbdc [cfg80211]
> > [...]
> > [ 4.969974] ieee80211 phy0: brcmf_cfg80211_attach: Could not register
> > wiphy device (-22)
>
> We're seeing this on different platforms (allwinner / rockchip / amlogic)
> with Broadcom WiFi chips. So it's unlikely to be related with anything in
> this series.
>
> I believe a fix for this has already been queued up:
>
>
https://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git/commit/?id=91046d6364afde646734c7ead1f649d253c386e9
Thanks for pointing it out, it fixes the issue alright.
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH 0/3] ARM: dts: aspeed: Deprecate g[45]-style compatibles
From: Andrew Jeffery @ 2019-07-24 8:13 UTC (permalink / raw)
To: linux-aspeed
Cc: Andrew Jeffery, lee.jones, robh+dt, mark.rutland, joel,
linus.walleij, devicetree, linux-arm-kernel, linux-kernel,
linux-gpio
Hello,
Joel and I decided that going forward we're not going to name compatibles along
the lines of SoC generations, so discourage any further attempts by removing
the remaining instances.
It's probably best if we push the three patches all through one tree rather
than fragmenting. Is everyone happy if Joel applies them to the aspeed tree?
Cheers,
Andrew
Andrew Jeffery (3):
dts: ARM: aspeed: Migrate away from aspeed,g[45].* compatibles
pinctrl: aspeed: Document existence of deprecated compatibles
dt-bindings: aspeed: Remove mention of deprecated compatibles
Documentation/devicetree/bindings/mfd/aspeed-scu.txt | 2 --
Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt | 2 --
.../devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml | 5 +----
.../devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml | 4 +---
arch/arm/boot/dts/aspeed-g4.dtsi | 2 +-
arch/arm/boot/dts/aspeed-g5.dtsi | 2 +-
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 4 ++++
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 4 ++++
8 files changed, 12 insertions(+), 13 deletions(-)
--
2.20.1
^ permalink raw reply
* [PATCH 1/3] dts: ARM: aspeed: Migrate away from aspeed,g[45].* compatibles
From: Andrew Jeffery @ 2019-07-24 8:13 UTC (permalink / raw)
To: linux-aspeed
Cc: Andrew Jeffery, lee.jones, robh+dt, mark.rutland, joel,
linus.walleij, devicetree, linux-arm-kernel, linux-kernel,
linux-gpio
In-Reply-To: <20190724081313.12934-1-andrew@aj.id.au>
Use the SoC-specific compatible strings instead.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 2 +-
arch/arm/boot/dts/aspeed-g5.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index dd4b0b15afcf..7f06dc21dc19 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -162,7 +162,7 @@
#reset-cells = <1>;
pinctrl: pinctrl {
- compatible = "aspeed,g4-pinctrl";
+ compatible = "aspeed,ast2400-pinctrl";
};
p2a: p2a-control {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 5b1ca265c2ce..04c97138e18b 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -215,7 +215,7 @@
#reset-cells = <1>;
pinctrl: pinctrl {
- compatible = "aspeed,g5-pinctrl";
+ compatible = "aspeed,ast2500-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
};
--
2.20.1
^ permalink raw reply related
* [PATCH 3/3] dt-bindings: aspeed: Remove mention of deprecated compatibles
From: Andrew Jeffery @ 2019-07-24 8:13 UTC (permalink / raw)
To: linux-aspeed
Cc: Andrew Jeffery, lee.jones, robh+dt, mark.rutland, joel,
linus.walleij, devicetree, linux-arm-kernel, linux-kernel,
linux-gpio
In-Reply-To: <20190724081313.12934-1-andrew@aj.id.au>
Guide readers away from using the aspeed,g[45].* compatible patterns.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
Documentation/devicetree/bindings/mfd/aspeed-scu.txt | 2 --
Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt | 2 --
.../devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml | 5 +----
.../devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml | 4 +---
4 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt
index ce8cf0ec6279..4d92c0bb6687 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt
+++ b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt
@@ -4,9 +4,7 @@ configuring elements such as clocks, pinmux, and reset.
Required properties:
- compatible: One of:
"aspeed,ast2400-scu", "syscon", "simple-mfd"
- "aspeed,g4-scu", "syscon", "simple-mfd"
"aspeed,ast2500-scu", "syscon", "simple-mfd"
- "aspeed,g5-scu", "syscon", "simple-mfd"
- reg: contains the offset and length of the SCU memory region
- #clock-cells: should be set to <1> - the system controller is also a
diff --git a/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt b/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt
index 854bd67ffec6..0e1fa5bc6a30 100644
--- a/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt
+++ b/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt
@@ -26,9 +26,7 @@ property:
- compatible : Should be one of the following:
"aspeed,ast2400-scu", "syscon", "simple-mfd"
- "aspeed,g4-scu", "syscon", "simple-mfd"
"aspeed,ast2500-scu", "syscon", "simple-mfd"
- "aspeed,g5-scu", "syscon", "simple-mfd"
Example
===================
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
index 125599a2dc5e..9368e4b6d4d0 100644
--- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
@@ -15,16 +15,13 @@ description: |+
- compatible: Should be one of the following:
"aspeed,ast2400-scu", "syscon", "simple-mfd"
- "aspeed,g4-scu", "syscon", "simple-mfd"
Refer to the the bindings described in
Documentation/devicetree/bindings/mfd/syscon.txt
properties:
compatible:
- enum:
- - aspeed,ast2400-pinctrl
- - aspeed,g4-pinctrl
+ const: aspeed,ast2400-pinctrl
patternProperties:
'^.*$':
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
index 3e6d85318577..939fb755a6db 100644
--- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
@@ -22,9 +22,7 @@ description: |+
properties:
compatible:
- enum:
- - aspeed,ast2500-pinctrl
- - aspeed,g5-pinctrl
+ const: aspeed,ast2500-pinctrl
aspeed,external-nodes:
minItems: 2
maxItems: 2
--
2.20.1
^ permalink raw reply related
* [PATCH 2/3] pinctrl: aspeed: Document existence of deprecated compatibles
From: Andrew Jeffery @ 2019-07-24 8:13 UTC (permalink / raw)
To: linux-aspeed
Cc: Andrew Jeffery, lee.jones, robh+dt, mark.rutland, joel,
linus.walleij, devicetree, linux-arm-kernel, linux-kernel,
linux-gpio
In-Reply-To: <20190724081313.12934-1-andrew@aj.id.au>
Otherwise they look odd in the face of not being listed in the bindings
documents.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 4 ++++
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
index 384396cbb22d..0e087fe759d2 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -2531,6 +2531,10 @@ static int aspeed_g4_pinctrl_probe(struct platform_device *pdev)
static const struct of_device_id aspeed_g4_pinctrl_of_match[] = {
{ .compatible = "aspeed,ast2400-pinctrl", },
+ /*
+ * The aspeed,g4-pinctrl compatible has been removed the from the
+ * bindings, but keep the match in case of old devicetrees.
+ */
{ .compatible = "aspeed,g4-pinctrl", },
{ },
};
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 053101f795a2..49255802735b 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -2676,6 +2676,10 @@ static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
static const struct of_device_id aspeed_g5_pinctrl_of_match[] = {
{ .compatible = "aspeed,ast2500-pinctrl", },
+ /*
+ * The aspeed,g5-pinctrl compatible has been removed the from the
+ * bindings, but keep the match in case of old devicetrees.
+ */
{ .compatible = "aspeed,g5-pinctrl", },
{ },
};
--
2.20.1
^ permalink raw reply related
* [PATCH] pinctrl: aspeed-g5: Delay acquisition of regmaps
From: Andrew Jeffery @ 2019-07-24 8:01 UTC (permalink / raw)
To: linux-gpio
Cc: Andrew Jeffery, linus.walleij, joel, linux-aspeed,
linux-arm-kernel, linux-kernel
While sorting out some devicetree issues I found that the pinctrl driver
was failing to acquire its GFX regmap even though the phandle was
present in the devicetree:
[ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail
Without access to the GFX regmap we fail to configure the mux for the
VPO function:
[ 1.548866] pinctrl core: add 1 pinctrl maps
[ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO
[ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display
[ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display
...
[ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display
[ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display
[ 1.563113] Muxing pin 144 for VPO
[ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000
[ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back
This turned out to be a simple problem of timing: The ASPEED pinctrl
driver is probed during arch_initcall(), while GFX is processed much
later. As such the GFX syscon is not yet registered during the pinctrl
probe() and we get an -EPROBE_DEFER when we try to look it up, however
we must not defer probing the pinctrl driver for the inability to mux
some GFX-related functions.
Switch to lazily grabbing the regmaps when they're first required by the
mux configuration. This generates a bit of noise in the patch as we have
to drop the `const` qualifier on arguments for several function
prototypes, but has the benefit of working.
I've smoke tested this for the ast2500-evb under qemu with a dummy
graphics device. We now succeed in our attempts to configure the SoC's
VPO pinmux function.
Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 2 +-
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 92 +++++++++++++++-------
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 12 ++-
drivers/pinctrl/aspeed/pinmux-aspeed.h | 5 +-
4 files changed, 74 insertions(+), 37 deletions(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
index 384396cbb22d..22256576b69a 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -2412,7 +2412,7 @@ static const struct aspeed_pin_config aspeed_g4_configs[] = {
{ PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 },
};
-static int aspeed_g4_sig_expr_set(const struct aspeed_pinmux_data *ctx,
+static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr,
bool enable)
{
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 053101f795a2..ba6438ac4d72 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -2507,6 +2507,61 @@ static struct aspeed_pin_config aspeed_g5_configs[] = {
{ PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 },
};
+static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
+ int ip)
+{
+ if (ip == ASPEED_IP_SCU) {
+ WARN(!ctx->maps[ip], "Missing SCU syscon!");
+ return ctx->maps[ip];
+ }
+
+ if (ip >= ASPEED_NR_PINMUX_IPS)
+ return ERR_PTR(-EINVAL);
+
+ if (likely(ctx->maps[ip]))
+ return ctx->maps[ip];
+
+ if (ip == ASPEED_IP_GFX) {
+ struct device_node *node;
+ struct regmap *map;
+
+ node = of_parse_phandle(ctx->dev->of_node,
+ "aspeed,external-nodes", 0);
+ if (node) {
+ map = syscon_node_to_regmap(node);
+ of_node_put(node);
+ if (IS_ERR(map))
+ return map;
+ } else
+ return ERR_PTR(-ENODEV);
+
+ ctx->maps[ASPEED_IP_GFX] = map;
+ dev_dbg(ctx->dev, "Acquired GFX regmap");
+ return map;
+ }
+
+ if (ip == ASPEED_IP_LPC) {
+ struct device_node *node;
+ struct regmap *map;
+
+ node = of_parse_phandle(ctx->dev->of_node,
+ "aspeed,external-nodes", 1);
+ if (node) {
+ map = syscon_node_to_regmap(node->parent);
+ of_node_put(node);
+ if (IS_ERR(map))
+ return map;
+ } else
+ map = ERR_PTR(-ENODEV);
+
+ ctx->maps[ASPEED_IP_LPC] = map;
+ dev_dbg(ctx->dev, "Acquired LPC regmap");
+ return map;
+ }
+
+ return ERR_PTR(-EINVAL);
+}
+
/**
* Configure a pin's signal by applying an expression's descriptor state for
* all descriptors in the expression.
@@ -2520,7 +2575,7 @@ static struct aspeed_pin_config aspeed_g5_configs[] = {
* Return: 0 if the expression is configured as requested and a negative error
* code otherwise
*/
-static int aspeed_g5_sig_expr_set(const struct aspeed_pinmux_data *ctx,
+static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr,
bool enable)
{
@@ -2531,9 +2586,15 @@ static int aspeed_g5_sig_expr_set(const struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_desc *desc = &expr->descs[i];
u32 pattern = enable ? desc->enable : desc->disable;
u32 val = (pattern << __ffs(desc->mask));
+ struct regmap *map;
- if (!ctx->maps[desc->ip])
- return -ENODEV;
+ map = aspeed_g5_acquire_regmap(ctx, desc->ip);
+ if (IS_ERR(map)) {
+ dev_err(ctx->dev,
+ "Failed to acquire regmap for IP block %d\n",
+ desc->ip);
+ return PTR_ERR(map);
+ }
/*
* Strap registers are configured in hardware or by early-boot
@@ -2641,34 +2702,11 @@ static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
{
int i;
- struct regmap *map;
- struct device_node *node;
for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
aspeed_g5_pins[i].number = i;
- node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 0);
- map = syscon_node_to_regmap(node);
- of_node_put(node);
- if (IS_ERR(map)) {
- dev_warn(&pdev->dev, "No GFX phandle found, some mux configurations may fail\n");
- map = NULL;
- }
- aspeed_g5_pinctrl_data.pinmux.maps[ASPEED_IP_GFX] = map;
-
- node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 1);
- if (node) {
- map = syscon_node_to_regmap(node->parent);
- if (IS_ERR(map)) {
- dev_warn(&pdev->dev, "LHC parent is not a syscon, some mux configurations may fail\n");
- map = NULL;
- }
- } else {
- dev_warn(&pdev->dev, "No LHC phandle found, some mux configurations may fail\n");
- map = NULL;
- }
- of_node_put(node);
- aspeed_g5_pinctrl_data.pinmux.maps[ASPEED_IP_LPC] = map;
+ aspeed_g5_pinctrl_data.pinmux.dev = &pdev->dev;
return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
&aspeed_g5_pinctrl_data);
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
index 535db3de490b..54933665b5f8 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
@@ -71,7 +71,7 @@ int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
return 0;
}
-static int aspeed_sig_expr_enable(const struct aspeed_pinmux_data *ctx,
+static int aspeed_sig_expr_enable(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr)
{
int ret;
@@ -86,7 +86,7 @@ static int aspeed_sig_expr_enable(const struct aspeed_pinmux_data *ctx,
return 0;
}
-static int aspeed_sig_expr_disable(const struct aspeed_pinmux_data *ctx,
+static int aspeed_sig_expr_disable(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr)
{
int ret;
@@ -109,7 +109,7 @@ static int aspeed_sig_expr_disable(const struct aspeed_pinmux_data *ctx,
*
* Return: 0 if all expressions are disabled, otherwise a negative error code
*/
-static int aspeed_disable_sig(const struct aspeed_pinmux_data *ctx,
+static int aspeed_disable_sig(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr **exprs)
{
int ret = 0;
@@ -217,8 +217,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
{
int i;
int ret;
- const struct aspeed_pinctrl_data *pdata =
- pinctrl_dev_get_drvdata(pctldev);
+ struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
const struct aspeed_pin_group *pgroup = &pdata->pinmux.groups[group];
const struct aspeed_pin_function *pfunc =
&pdata->pinmux.functions[function];
@@ -306,8 +305,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
unsigned int offset)
{
int ret;
- const struct aspeed_pinctrl_data *pdata =
- pinctrl_dev_get_drvdata(pctldev);
+ struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data;
const struct aspeed_sig_expr ***prios, **funcs, *expr;
diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h
index 329d54d48667..52d299b59ce2 100644
--- a/drivers/pinctrl/aspeed/pinmux-aspeed.h
+++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h
@@ -702,11 +702,12 @@ struct aspeed_pin_function {
struct aspeed_pinmux_data;
struct aspeed_pinmux_ops {
- int (*set)(const struct aspeed_pinmux_data *ctx,
+ int (*set)(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr, bool enabled);
};
struct aspeed_pinmux_data {
+ struct device *dev;
struct regmap *maps[ASPEED_NR_PINMUX_IPS];
const struct aspeed_pinmux_ops *ops;
@@ -725,7 +726,7 @@ int aspeed_sig_expr_eval(const struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr,
bool enabled);
-static inline int aspeed_sig_expr_set(const struct aspeed_pinmux_data *ctx,
+static inline int aspeed_sig_expr_set(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr,
bool enabled)
{
--
2.20.1
^ permalink raw reply related
* Re: [PATCH 00/18] ARM: Add minimal Raspberry Pi 4 support
From: Chen-Yu Tsai @ 2019-07-24 2:53 UTC (permalink / raw)
To: Nicolas Saenz Julienne
Cc: Stefan Wahren, Christoph Hellwig, Mark Rutland, Ulf Hansson,
Florian Fainelli, Scott Branden, Matthias Brugger, Stephen Boyd,
Ray Jui, Linus Walleij, linux-mmc, Adrian Hunter, Eric Anholt,
Rob Herring, open list:BROADCOM BCM281XX...,
moderated list:BROADCOM BCM2835..., open list:GPIO SUBSYSTEM,
Michael Turquette, linux-arm-kernel
In-Reply-To: <5f9b11f54c66fd0487837f7e58af3adf7f86635f.camel@suse.de>
On Wed, Jul 24, 2019 at 1:33 AM Nicolas Saenz Julienne
<nsaenzjulienne@suse.de> wrote:
>
> On Tue, 2019-07-23 at 18:26 +0200, Stefan Wahren wrote:
> > Hi Nicolas,
> >
> > thanks for your work, but i'm a little bit sceptical about these
> > changes. So here some thoughts.
> >
> > Am 23.07.19 um 15:32 schrieb Nicolas Saenz Julienne:
> > > On Tue, 2019-07-23 at 11:34 +0200, Christoph Hellwig wrote:
> > > > On Mon, Jul 22, 2019 at 08:10:17PM +0200, Stefan Wahren wrote:
> > > > > i rebased this series also and got this only on the RPi 4.
> > > > >
> > > > > After reverting the following:
> > > > >
> > > > > 79a986721de dma-mapping: remove dma_max_pfn
> > > > > 7559d612dff0 mmc: core: let the dma map ops handle bouncing
> > > > >
> > > > > This crash disappear, but wifi seems to be still broken.
> > > > >
> > > > > Would be nice, if you can investigate further.
> > > > That means dma addressing on this system doesn't just work for some
> > > > memory, and the mmc bounce buffering was papering over that just for
> > > > mmc. Do you have highmem on this system?
> > > >
> > > > You might want to try this series, which has been submitted upstream:
> > > >
> > > >
> http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/arm-swiotlb
> > > Hi Christoph,
> > > I tried your series on top of Stefan's, it has no effect. I guess it's no
> > > surprise as with mult_v7_defconfig, you get SWIOTLB=n & LPAE=n.
> > >
> > > FYI DMA addressing constraints for RPi4 are the following: devices can only
> > > access the first GB of ram even though the board might have up to 4GB of
> > > ram.
> > > The DMA addresses are aliased with a 0xc0000000 offset. So 0x00000000 phys
> > > is
> > > aliased to 0xc0000000 in DMA. This is the same as for an RFC you commented
> > > last
> > > week trying to fix similar issues for arm64.
> > >
> > > You state in "arm: use swiotlb for bounce buffer on LPAE configs" that "The
> > > DMA
> > > API requires that 32-bit DMA masks are always supported". If I understand it
> > > correctly this device breaks that assumption. Which implies we need a bounce
> > > buffer system in place for any straming DMA user.
> > >
> > > It seems we're unable to use dma-direct/swiotlb, so I enabled arm's
> > > dmabounce
> > > on all devices hooked into RPi's limited interconnect, which fixes this
> > > issue.
> > Does it fix the wifi issue too?
>
> Well it works as long as I revert this: 901bb98918 ("nl80211: require and
> validate vendor command policy"). Which has nothing to do with DMA anyways.
>
> Was this the issue you where seeing?
>
> [ 4.969679] WARNING: CPU: 2 PID: 21 at net/wireless/core.c:868 wiphy_register+0x8e8/0xbdc [cfg80211]
> [...]
> [ 4.969974] ieee80211 phy0: brcmf_cfg80211_attach: Could not register wiphy device (-22)
We're seeing this on different platforms (allwinner / rockchip / amlogic)
with Broadcom WiFi chips. So it's unlikely to be related with anything in
this series.
I believe a fix for this has already been queued up:
https://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git/commit/?id=91046d6364afde646734c7ead1f649d253c386e9
ChenYu
^ permalink raw reply
* Re: [PATCH V6 16/21] soc/tegra: pmc: Add pmc wake support for tegra210
From: Sowjanya Komatineni @ 2019-07-23 23:39 UTC (permalink / raw)
To: Dmitry Osipenko, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <a545cc66-45cd-504a-4390-8274b8b79540@gmail.com>
On 7/23/19 7:27 AM, Dmitry Osipenko wrote:
> 23.07.2019 6:43, Dmitry Osipenko пишет:
>> 23.07.2019 6:31, Sowjanya Komatineni пишет:
>>> On 7/22/19 8:25 PM, Dmitry Osipenko wrote:
>>>> 23.07.2019 6:09, Sowjanya Komatineni пишет:
>>>>> On 7/22/19 8:03 PM, Dmitry Osipenko wrote:
>>>>>> 23.07.2019 4:52, Sowjanya Komatineni пишет:
>>>>>>> On 7/22/19 6:41 PM, Dmitry Osipenko wrote:
>>>>>>>> 23.07.2019 4:08, Dmitry Osipenko пишет:
>>>>>>>>> 23.07.2019 3:58, Dmitry Osipenko пишет:
>>>>>>>>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>>>>>>>>> This patch implements PMC wakeup sequence for Tegra210 and defines
>>>>>>>>>>> common used RTC alarm wake event.
>>>>>>>>>>>
>>>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>>>> ---
>>>>>>>>>>> drivers/soc/tegra/pmc.c | 111
>>>>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>>> 1 file changed, 111 insertions(+)
>>>>>>>>>>>
>>>>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>>>>>> index 91c84d0e66ae..c556f38874e1 100644
>>>>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>>>>> @@ -57,6 +57,12 @@
>>>>>>>>>>> #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock
>>>>>>>>>>> enable */
>>>>>>>>>>> #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk
>>>>>>>>>>> polarity */
>>>>>>>>>>> #define PMC_CNTRL_MAIN_RST BIT(4)
>>>>>>>>>>> +#define PMC_CNTRL_LATCH_WAKEUPS BIT(5)
>>>>>>>>> Please follow the TRM's bits naming.
>>>>>>>>>
>>>>>>>>> PMC_CNTRL_LATCHWAKE_EN
>>>>>>>>>
>>>>>>>>>>> +#define PMC_WAKE_MASK 0x0c
>>>>>>>>>>> +#define PMC_WAKE_LEVEL 0x10
>>>>>>>>>>> +#define PMC_WAKE_STATUS 0x14
>>>>>>>>>>> +#define PMC_SW_WAKE_STATUS 0x18
>>>>>>>>>>> #define DPD_SAMPLE 0x020
>>>>>>>>>>> #define DPD_SAMPLE_ENABLE BIT(0)
>>>>>>>>>>> @@ -87,6 +93,11 @@
>>>>>>>>>>> #define PMC_SCRATCH41 0x140
>>>>>>>>>>> +#define PMC_WAKE2_MASK 0x160
>>>>>>>>>>> +#define PMC_WAKE2_LEVEL 0x164
>>>>>>>>>>> +#define PMC_WAKE2_STATUS 0x168
>>>>>>>>>>> +#define PMC_SW_WAKE2_STATUS 0x16c
>>>>>>>>>>> +
>>>>>>>>>>> #define PMC_SENSOR_CTRL 0x1b0
>>>>>>>>>>> #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
>>>>>>>>>>> #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
>>>>>>>>>>> @@ -1922,6 +1933,55 @@ static const struct irq_domain_ops
>>>>>>>>>>> tegra_pmc_irq_domain_ops = {
>>>>>>>>>>> .alloc = tegra_pmc_irq_alloc,
>>>>>>>>>>> };
>>>>>>>>>>> +static int tegra210_pmc_irq_set_wake(struct irq_data *data,
>>>>>>>>>>> unsigned int on)
>>>>>>>>>>> +{
>>>>>>>>>>> + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
>>>>>>>>>>> + unsigned int offset, bit;
>>>>>>>>>>> + u32 value;
>>>>>>>>>>> +
>>>>>>>>>>> + if (data->hwirq == ULONG_MAX)
>>>>>>>>>>> + return 0;
>>>>>>>>>>> +
>>>>>>>>>>> + offset = data->hwirq / 32;
>>>>>>>>>>> + bit = data->hwirq % 32;
>>>>>>>>>>> +
>>>>>>>>>>> + /*
>>>>>>>>>>> + * Latch wakeups to SW_WAKE_STATUS register to capture events
>>>>>>>>>>> + * that would not make it into wakeup event register during
>>>>>>>>>>> LP0 exit.
>>>>>>>>>>> + */
>>>>>>>>>>> + value = tegra_pmc_readl(pmc, PMC_CNTRL);
>>>>>>>>>>> + value |= PMC_CNTRL_LATCH_WAKEUPS;
>>>>>>>>>>> + tegra_pmc_writel(pmc, value, PMC_CNTRL);
>>>>>>>>>>> + udelay(120);
>>>>>>>>>> Why it takes so much time to latch the values? Shouldn't some
>>>>>>>>>> status-bit
>>>>>>>>>> be polled for the completion of latching?
>>>>>>>>>>
>>>>>>>>>> Is this register-write really getting buffered in the PMC?
>>>>>>>>>>
>>>>>>>>>>> + value &= ~PMC_CNTRL_LATCH_WAKEUPS;
>>>>>>>>>>> + tegra_pmc_writel(pmc, value, PMC_CNTRL);
>>>>>>>>>>> + udelay(120);
>>>>>>>>>> 120 usecs to remove latching, really?
>>>>>>>>>>
>>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
>>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
>>>>>>>>>>> +
>>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
>>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
>>>>>>>>>>> +
>>>>>>>>>>> + /* enable PMC wake */
>>>>>>>>>>> + if (data->hwirq >= 32)
>>>>>>>>>>> + offset = PMC_WAKE2_MASK;
>>>>>>>>>>> + else
>>>>>>>>>>> + offset = PMC_WAKE_MASK;
>>>>>>>>>>> +
>>>>>>>>>>> + value = tegra_pmc_readl(pmc, offset);
>>>>>>>>>>> +
>>>>>>>>>>> + if (on)
>>>>>>>>>>> + value |= 1 << bit;
>>>>>>>>>>> + else
>>>>>>>>>>> + value &= ~(1 << bit);
>>>>>>>>>>> +
>>>>>>>>>>> + tegra_pmc_writel(pmc, value, offset);
>>>>>>>>>> Why the latching is done *before* writing into the WAKE registers?
>>>>>>>>>> What
>>>>>>>>>> it is latching then?
>>>>>>>>> I'm looking at the TRM doc and it says that latching should be done
>>>>>>>>> *after* writing to the WAKE_MASK / LEVEL registers.
>>>>>>>>>
>>>>>>>>> Secondly it says that it's enough to do:
>>>>>>>>>
>>>>>>>>> value = tegra_pmc_readl(pmc, PMC_CNTRL);
>>>>>>>>> value |= PMC_CNTRL_LATCH_WAKEUPS;
>>>>>>>>> tegra_pmc_writel(pmc, value, PMC_CNTRL);
>>>>>>>>>
>>>>>>>>> in order to latch. There is no need for the delay and to remove the
>>>>>>>>> "LATCHWAKE_EN" bit, it should be a oneshot action.
>>>>>>>> Although, no. TRM says "stops latching on transition from 1
>>>>>>>> to 0 (sequence - set to 1,set to 0)", so it's not a oneshot action.
>>>>>>>>
>>>>>>>> Have you tested this code at all? I'm wondering how it happens to
>>>>>>>> work
>>>>>>>> without a proper latching.
>>>>>>> Yes, ofcourse its tested and this sequence to do transition is
>>>>>>> recommendation from Tegra designer.
>>>>>>> Will check if TRM doesn't have update properly or will re-confirm
>>>>>>> internally on delay time...
>>>>>>>
>>>>>>> On any of the wake event PMC wakeup happens and WAKE_STATUS register
>>>>>>> will have bits set for all events that triggered wake.
>>>>>>> After wakeup PMC doesn't update SW_WAKE_STATUS register as per PMC
>>>>>>> design.
>>>>>>> SW latch register added in design helps to provide a way to capture
>>>>>>> those events that happen right during wakeup time and didnt make it to
>>>>>>> SW_WAKE_STATUS register.
>>>>>>> So before next suspend entry, latching all prior wake events into SW
>>>>>>> WAKE_STATUS and then clearing them.
>>>>>> I'm now wondering whether the latching cold be turned ON permanently
>>>>>> during of the PMC's probe, for simplicity.
>>>>> latching should be done on suspend-resume cycle as wake events gets
>>>>> generates on every suspend-resume cycle.
>>>> You're saying that PMC "doesn't update SW_WAKE_STATUS" after wake-up,
>>>> then I don't quite understand what's the point of disabling the latching
>>>> at all.
>>> When latch wake enable is set, events are latched and during 1 to 0
>>> transition latching is disabled.
>>>
>>> This is to avoid sw_wake_status and wake_status showing diff events.
>> Okay.
>>
>>> Currently driver is not relying on SW_WAKE_STATUS but its good to latch
>>> and clear so even at some point for some reason when SW_WAKE_STATUS is
>>> used, this wlil not cause mismatch with wake_status.
>> Then the latching need to be enabled on suspend and disabled early on
>> resume to get a proper WAKE status.
> Actually, it will be better to simply not implement the latching until
> it will become really needed. In general you shouldn't add into the
> patchset anything that is unused.
OK, will remove latch_wake for now.
Will send next version once I get all the review feedback ..
^ permalink raw reply
* Re: [PATCH 00/18] ARM: Add minimal Raspberry Pi 4 support
From: Stefan Wahren @ 2019-07-23 21:30 UTC (permalink / raw)
To: Nicolas Saenz Julienne, Christoph Hellwig
Cc: Eric Anholt, Florian Fainelli, Ray Jui, Scott Branden,
Matthias Brugger, Rob Herring, Mark Rutland, Linus Walleij,
Michael Turquette, Stephen Boyd, Ulf Hansson, Adrian Hunter,
bcm-kernel-feedback-list, linux-arm-kernel, linux-rpi-kernel,
linux-gpio, linux-mmc
In-Reply-To: <5f9b11f54c66fd0487837f7e58af3adf7f86635f.camel@suse.de>
Hi Nicolas,
Am 23.07.19 um 19:33 schrieb Nicolas Saenz Julienne:
> On Tue, 2019-07-23 at 18:26 +0200, Stefan Wahren wrote:
>> Hi Nicolas,
>>
>> thanks for your work, but i'm a little bit sceptical about these
>> changes. So here some thoughts.
>>
>> Am 23.07.19 um 15:32 schrieb Nicolas Saenz Julienne:
>>> On Tue, 2019-07-23 at 11:34 +0200, Christoph Hellwig wrote:
>>>> On Mon, Jul 22, 2019 at 08:10:17PM +0200, Stefan Wahren wrote:
>>>>> i rebased this series also and got this only on the RPi 4.
>>>>>
>>>>> After reverting the following:
>>>>>
>>>>> 79a986721de dma-mapping: remove dma_max_pfn
>>>>> 7559d612dff0 mmc: core: let the dma map ops handle bouncing
>>>>>
>>>>> This crash disappear, but wifi seems to be still broken.
>>>>>
>>>>> Would be nice, if you can investigate further.
>>>> That means dma addressing on this system doesn't just work for some
>>>> memory, and the mmc bounce buffering was papering over that just for
>>>> mmc. Do you have highmem on this system?
>>>>
>>>> You might want to try this series, which has been submitted upstream:
>>>>
>>>>
> http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/arm-swiotlb
>>> Hi Christoph,
>>> I tried your series on top of Stefan's, it has no effect. I guess it's no
>>> surprise as with mult_v7_defconfig, you get SWIOTLB=n & LPAE=n.
>>>
>>> FYI DMA addressing constraints for RPi4 are the following: devices can only
>>> access the first GB of ram even though the board might have up to 4GB of
>>> ram.
>>> The DMA addresses are aliased with a 0xc0000000 offset. So 0x00000000 phys
>>> is
>>> aliased to 0xc0000000 in DMA. This is the same as for an RFC you commented
>>> last
>>> week trying to fix similar issues for arm64.
>>>
>>> You state in "arm: use swiotlb for bounce buffer on LPAE configs" that "The
>>> DMA
>>> API requires that 32-bit DMA masks are always supported". If I understand it
>>> correctly this device breaks that assumption. Which implies we need a bounce
>>> buffer system in place for any straming DMA user.
>>>
>>> It seems we're unable to use dma-direct/swiotlb, so I enabled arm's
>>> dmabounce
>>> on all devices hooked into RPi's limited interconnect, which fixes this
>>> issue.
>> Does it fix the wifi issue too?
> Well it works as long as I revert this: 901bb98918 ("nl80211: require and
> validate vendor command policy"). Which has nothing to do with DMA anyways.
>
> Was this the issue you where seeing?
Yes. So it's a regression? I will try to test it with a RPi 3B+
^ permalink raw reply
* [PATCH v1 2/2] pinctrl: qdf2xxx: Switch to use device_property_count_uXX()
From: Andy Shevchenko @ 2019-07-23 19:27 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross, linux-arm-msm, Linus Walleij,
linux-gpio
Cc: Andy Shevchenko
In-Reply-To: <20190723192738.68486-1-andriy.shevchenko@linux.intel.com>
Use use device_property_count_uXX() directly, that makes code neater.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index 5da5dd51542c..43bd15f16377 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -52,7 +52,7 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
}
/* The number of GPIOs in the approved list */
- ret = device_property_read_u8_array(&pdev->dev, "gpios", NULL, 0);
+ ret = device_property_count_u8(&pdev->dev, "gpios");
if (ret < 0) {
dev_err(&pdev->dev, "missing 'gpios' property\n");
return ret;
--
2.20.1
^ permalink raw reply related
* [PATCH v1 1/2] pinctrl: msm: Switch to use device_property_count_uXX()
From: Andy Shevchenko @ 2019-07-23 19:27 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross, linux-arm-msm, Linus Walleij,
linux-gpio
Cc: Andy Shevchenko
Use use device_property_count_uXX() directly, that makes code neater.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/qcom/pinctrl-msm.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 7f35c196bb3e..90bc667139e0 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -617,8 +617,7 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *chip)
}
/* The number of GPIOs in the ACPI tables */
- len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL,
- 0);
+ len = ret = device_property_count_u16(pctrl->dev, "gpios");
if (ret < 0)
return 0;
@@ -996,7 +995,7 @@ static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
if (pctrl->soc->reserved_gpios)
return true;
- return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0;
+ return device_property_count_u16(pctrl->dev, "gpios") > 0;
}
static int msm_gpio_init(struct msm_pinctrl *pctrl)
--
2.20.1
^ permalink raw reply related
* [PATCH] extcon: fsa9480: Support the FSA880 variant
From: Linus Walleij @ 2019-07-23 17:43 UTC (permalink / raw)
To: MyungJoo Ham, Chanwoo Choi
Cc: linux-kernel, linux-gpio, Mike Lockwood, Linus Walleij,
devicetree
The older compatible variant of this chip is called FSA880
and works the same way, if we need some quirks in the future,
it is good to let it have its own compatible string.
Cc: devicetree@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt | 4 +++-
drivers/extcon/extcon-fsa9480.c | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt b/Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt
index d592c21245f2..624bd76f468e 100644
--- a/Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt
+++ b/Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt
@@ -5,7 +5,9 @@ controlled using I2C and enables USB data, stereo and mono audio, video,
microphone, and UART data to use a common connector port.
Required properties:
- - compatible : Must be "fcs,fsa9480"
+ - compatible : Must be one of
+ "fcs,fsa9480"
+ "fcs,fsa880"
- reg : Specifies i2c slave address. Must be 0x25.
- interrupts : Should contain one entry specifying interrupt signal of
interrupt parent to which interrupt pin of the chip is connected.
diff --git a/drivers/extcon/extcon-fsa9480.c b/drivers/extcon/extcon-fsa9480.c
index 350fb34abfa0..8405512f5199 100644
--- a/drivers/extcon/extcon-fsa9480.c
+++ b/drivers/extcon/extcon-fsa9480.c
@@ -363,6 +363,7 @@ MODULE_DEVICE_TABLE(i2c, fsa9480_id);
static const struct of_device_id fsa9480_of_match[] = {
{ .compatible = "fcs,fsa9480", },
+ { .compatible = "fcs,fsa880", },
{ },
};
MODULE_DEVICE_TABLE(of, fsa9480_of_match);
--
2.21.0
^ permalink raw reply related
* Re: [PATCH 00/18] ARM: Add minimal Raspberry Pi 4 support
From: Nicolas Saenz Julienne @ 2019-07-23 17:33 UTC (permalink / raw)
To: Stefan Wahren, Christoph Hellwig
Cc: Eric Anholt, Florian Fainelli, Ray Jui, Scott Branden,
Matthias Brugger, Rob Herring, Mark Rutland, Linus Walleij,
Michael Turquette, Stephen Boyd, Ulf Hansson, Adrian Hunter,
bcm-kernel-feedback-list, linux-arm-kernel, linux-rpi-kernel,
linux-gpio, linux-mmc
In-Reply-To: <b15509d6-bc2e-3d06-0eea-943e6e456d62@gmx.net>
[-- Attachment #1: Type: text/plain, Size: 6204 bytes --]
On Tue, 2019-07-23 at 18:26 +0200, Stefan Wahren wrote:
> Hi Nicolas,
>
> thanks for your work, but i'm a little bit sceptical about these
> changes. So here some thoughts.
>
> Am 23.07.19 um 15:32 schrieb Nicolas Saenz Julienne:
> > On Tue, 2019-07-23 at 11:34 +0200, Christoph Hellwig wrote:
> > > On Mon, Jul 22, 2019 at 08:10:17PM +0200, Stefan Wahren wrote:
> > > > i rebased this series also and got this only on the RPi 4.
> > > >
> > > > After reverting the following:
> > > >
> > > > 79a986721de dma-mapping: remove dma_max_pfn
> > > > 7559d612dff0 mmc: core: let the dma map ops handle bouncing
> > > >
> > > > This crash disappear, but wifi seems to be still broken.
> > > >
> > > > Would be nice, if you can investigate further.
> > > That means dma addressing on this system doesn't just work for some
> > > memory, and the mmc bounce buffering was papering over that just for
> > > mmc. Do you have highmem on this system?
> > >
> > > You might want to try this series, which has been submitted upstream:
> > >
> > >
http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/arm-swiotlb
> > Hi Christoph,
> > I tried your series on top of Stefan's, it has no effect. I guess it's no
> > surprise as with mult_v7_defconfig, you get SWIOTLB=n & LPAE=n.
> >
> > FYI DMA addressing constraints for RPi4 are the following: devices can only
> > access the first GB of ram even though the board might have up to 4GB of
> > ram.
> > The DMA addresses are aliased with a 0xc0000000 offset. So 0x00000000 phys
> > is
> > aliased to 0xc0000000 in DMA. This is the same as for an RFC you commented
> > last
> > week trying to fix similar issues for arm64.
> >
> > You state in "arm: use swiotlb for bounce buffer on LPAE configs" that "The
> > DMA
> > API requires that 32-bit DMA masks are always supported". If I understand it
> > correctly this device breaks that assumption. Which implies we need a bounce
> > buffer system in place for any straming DMA user.
> >
> > It seems we're unable to use dma-direct/swiotlb, so I enabled arm's
> > dmabounce
> > on all devices hooked into RPi's limited interconnect, which fixes this
> > issue.
> Does it fix the wifi issue too?
Well it works as long as I revert this: 901bb98918 ("nl80211: require and
validate vendor command policy"). Which has nothing to do with DMA anyways.
Was this the issue you where seeing?
[ 4.969679] WARNING: CPU: 2 PID: 21 at net/wireless/core.c:868 wiphy_register+0x8e8/0xbdc [cfg80211]
[...]
[ 4.969974] ieee80211 phy0: brcmf_cfg80211_attach: Could not register wiphy device (-22)
> > Any thoughts on this?
> >
> > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> > index 5e5f1fabc3d4..3db8deed83a6 100644
> > --- a/arch/arm/mach-bcm/Kconfig
> > +++ b/arch/arm/mach-bcm/Kconfig
> > @@ -168,6 +168,7 @@ config ARCH_BCM2835
> > select PINCTRL
> > select PINCTRL_BCM2835
> > select MFD_CORE
> > + select DMABOUNCE
> > help
> > This enables support for the Broadcom BCM2835 and BCM2836 SoCs.
> > This SoC is used in the Raspberry Pi and Roku 2 devices.
> > diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-
> > bcm/board_bcm2835.c
> > index c09cf25596af..be788849c4bb 100644
> > --- a/arch/arm/mach-bcm/board_bcm2835.c
> > +++ b/arch/arm/mach-bcm/board_bcm2835.c
> > @@ -3,6 +3,8 @@
> > * Copyright (C) 2010 Broadcom
> > */
> >
> > +#include <linux/device.h>
> > +#include <linux/dma-mapping.h>
> > #include <linux/init.h>
> > #include <linux/irqchip.h>
> > #include <linux/of_address.h>
> > @@ -24,8 +26,37 @@ static const char * const bcm2835_compat[] = {
> > NULL
> > };
> >
> > +static int bcm2835_needs_bounce(struct device *dev, dma_addr_t dma_addr,
> > size_t size)
> > +{
> > + /*
> > + * The accepted dma addresses are [0xc0000000, 0xffffffff] which map
> > to
> > + * ram's [0x00000000, 0x3fffffff].
> > + */
> > + return dma_addr < 3ULL * SZ_1G;
> > +}
> > +
> > +/*
> > + * Setup DMA mask to 1GB on devices hanging from soc interconnect
> > + */
> > +static int bcm2835_platform_notify(struct device *dev)
> > +{
> > + if (dev->parent && !strcmp("soc", dev_name(dev->parent))) {
> > + dev->dma_mask = &dev->coherent_dma_mask;
> > + dev->coherent_dma_mask = DMA_BIT_MASK(30); /* 1GB */
> Shouldn't this come from the device tree?
Yes, actually I could use the 'dma-ranges' parsing code I suggested on the
arm64 RFC. The same goes with 'dma_zone_size = SZ_1G', it ideally should be
calculated based on the device-tree.
The way I see it I'm not sure it's worth the effort, in arm64 we have no choice
as there are no board files. But here we seem to be the only ones with this
specific DMA addressing constraint, so fixing it in arm/common doesn't seem
like it's going to benefit anyone else. Let's see how the arm arch maintainers
react though.
There is one catch though. I missed it earlier as I was excited to see the
board boot, but some devices are failing to set their DMA masks:
[ 1.989576] dwc2 fe980000.usb: can't set coherent DMA mask: -5
It seems that other users of dmabounce also implement their own
dma_supported(). I have to look into it.
> > + dmabounce_register_dev(dev, 2048, 4096,
> > bcm2835_needs_bounce);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +void __init bcm2835_init_early(void)
> > +{
> > + platform_notify = bcm2835_platform_notify;
> > +}
> > +
> > DT_MACHINE_START(BCM2835, "BCM2835")
> > .dma_zone_size = SZ_1G,
> > .dt_compat = bcm2835_compat,
> > .smp = smp_ops(bcm2836_smp_ops),
> > + .init_early = bcm2835_init_early,
>
> The sum of all these changes make me think, that we should start a new
> board for BCM2711 instead of extending BCM2835.
>
I agree, I did it locally but merged it into the current board file to make the
patch smaller.
> Best regards
> Stefan Wahren
>
> > MACHINE_END
> >
> > Regards,
> > Nicolas
> >
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH 00/18] ARM: Add minimal Raspberry Pi 4 support
From: Stefan Wahren @ 2019-07-23 16:26 UTC (permalink / raw)
To: Nicolas Saenz Julienne, Christoph Hellwig
Cc: Eric Anholt, Florian Fainelli, Ray Jui, Scott Branden,
Matthias Brugger, Rob Herring, Mark Rutland, Linus Walleij,
Michael Turquette, Stephen Boyd, Ulf Hansson, Adrian Hunter,
bcm-kernel-feedback-list, linux-arm-kernel, linux-rpi-kernel,
linux-gpio, linux-mmc
In-Reply-To: <04c5eaa03f3a124dbbce6186e11e19acc4539cc8.camel@suse.de>
Hi Nicolas,
thanks for your work, but i'm a little bit sceptical about these
changes. So here some thoughts.
Am 23.07.19 um 15:32 schrieb Nicolas Saenz Julienne:
> On Tue, 2019-07-23 at 11:34 +0200, Christoph Hellwig wrote:
>> On Mon, Jul 22, 2019 at 08:10:17PM +0200, Stefan Wahren wrote:
>>> i rebased this series also and got this only on the RPi 4.
>>>
>>> After reverting the following:
>>>
>>> 79a986721de dma-mapping: remove dma_max_pfn
>>> 7559d612dff0 mmc: core: let the dma map ops handle bouncing
>>>
>>> This crash disappear, but wifi seems to be still broken.
>>>
>>> Would be nice, if you can investigate further.
>> That means dma addressing on this system doesn't just work for some
>> memory, and the mmc bounce buffering was papering over that just for
>> mmc. Do you have highmem on this system?
>>
>> You might want to try this series, which has been submitted upstream:
>>
>> http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/arm-swiotlb
> Hi Christoph,
> I tried your series on top of Stefan's, it has no effect. I guess it's no
> surprise as with mult_v7_defconfig, you get SWIOTLB=n & LPAE=n.
>
> FYI DMA addressing constraints for RPi4 are the following: devices can only
> access the first GB of ram even though the board might have up to 4GB of ram.
> The DMA addresses are aliased with a 0xc0000000 offset. So 0x00000000 phys is
> aliased to 0xc0000000 in DMA. This is the same as for an RFC you commented last
> week trying to fix similar issues for arm64.
>
> You state in "arm: use swiotlb for bounce buffer on LPAE configs" that "The DMA
> API requires that 32-bit DMA masks are always supported". If I understand it
> correctly this device breaks that assumption. Which implies we need a bounce
> buffer system in place for any straming DMA user.
>
> It seems we're unable to use dma-direct/swiotlb, so I enabled arm's dmabounce
> on all devices hooked into RPi's limited interconnect, which fixes this issue.
Does it fix the wifi issue too?
> Any thoughts on this?
>
> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> index 5e5f1fabc3d4..3db8deed83a6 100644
> --- a/arch/arm/mach-bcm/Kconfig
> +++ b/arch/arm/mach-bcm/Kconfig
> @@ -168,6 +168,7 @@ config ARCH_BCM2835
> select PINCTRL
> select PINCTRL_BCM2835
> select MFD_CORE
> + select DMABOUNCE
> help
> This enables support for the Broadcom BCM2835 and BCM2836 SoCs.
> This SoC is used in the Raspberry Pi and Roku 2 devices.
> diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c
> index c09cf25596af..be788849c4bb 100644
> --- a/arch/arm/mach-bcm/board_bcm2835.c
> +++ b/arch/arm/mach-bcm/board_bcm2835.c
> @@ -3,6 +3,8 @@
> * Copyright (C) 2010 Broadcom
> */
>
> +#include <linux/device.h>
> +#include <linux/dma-mapping.h>
> #include <linux/init.h>
> #include <linux/irqchip.h>
> #include <linux/of_address.h>
> @@ -24,8 +26,37 @@ static const char * const bcm2835_compat[] = {
> NULL
> };
>
> +static int bcm2835_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
> +{
> + /*
> + * The accepted dma addresses are [0xc0000000, 0xffffffff] which map to
> + * ram's [0x00000000, 0x3fffffff].
> + */
> + return dma_addr < 3ULL * SZ_1G;
> +}
> +
> +/*
> + * Setup DMA mask to 1GB on devices hanging from soc interconnect
> + */
> +static int bcm2835_platform_notify(struct device *dev)
> +{
> + if (dev->parent && !strcmp("soc", dev_name(dev->parent))) {
> + dev->dma_mask = &dev->coherent_dma_mask;
> + dev->coherent_dma_mask = DMA_BIT_MASK(30); /* 1GB */
Shouldn't this come from the device tree?
> + dmabounce_register_dev(dev, 2048, 4096, bcm2835_needs_bounce);
> + }
> +
> + return 0;
> +}
> +
> +void __init bcm2835_init_early(void)
> +{
> + platform_notify = bcm2835_platform_notify;
> +}
> +
> DT_MACHINE_START(BCM2835, "BCM2835")
> .dma_zone_size = SZ_1G,
> .dt_compat = bcm2835_compat,
> .smp = smp_ops(bcm2836_smp_ops),
> + .init_early = bcm2835_init_early,
The sum of all these changes make me think, that we should start a new
board for BCM2711 instead of extending BCM2835.
Best regards
Stefan Wahren
> MACHINE_END
>
> Regards,
> Nicolas
>
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