* [PATCH v7 01/20] pinctrl: tegra: Add suspend and resume support
From: Sowjanya Komatineni @ 2019-07-31 0:20 UTC (permalink / raw)
To: thierry.reding, jonathanh, tglx, jason, marc.zyngier,
linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, skomatineni, linux-tegra, linux-kernel,
mperttunen, spatra, robh+dt, digetx, devicetree
In-Reply-To: <1564532424-10449-1-git-send-email-skomatineni@nvidia.com>
This patch adds support for Tegra pinctrl driver suspend and resume.
During suspend, context of all pinctrl registers are stored and
on resume they are all restored to have all the pinmux and pad
configuration for normal operation.
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/pinctrl/tegra/pinctrl-tegra.c | 59 +++++++++++++++++++++++++++++++++++
drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++
2 files changed, 62 insertions(+)
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 186ef98e7b2b..e3a237534281 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -631,6 +631,58 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
}
}
+static size_t tegra_pinctrl_get_bank_size(struct device *dev,
+ unsigned int bank_id)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
+
+ return resource_size(res) / 4;
+}
+
+static int tegra_pinctrl_suspend(struct device *dev)
+{
+ struct tegra_pmx *pmx = dev_get_drvdata(dev);
+ u32 *backup_regs = pmx->backup_regs;
+ u32 *regs;
+ size_t bank_size;
+ unsigned int i, k;
+
+ for (i = 0; i < pmx->nbanks; i++) {
+ bank_size = tegra_pinctrl_get_bank_size(dev, i);
+ regs = pmx->regs[i];
+ for (k = 0; k < bank_size; k++)
+ *backup_regs++ = readl_relaxed(regs++);
+ }
+
+ return pinctrl_force_sleep(pmx->pctl);
+}
+
+static int tegra_pinctrl_resume(struct device *dev)
+{
+ struct tegra_pmx *pmx = dev_get_drvdata(dev);
+ u32 *backup_regs = pmx->backup_regs;
+ u32 *regs;
+ size_t bank_size;
+ unsigned int i, k;
+
+ for (i = 0; i < pmx->nbanks; i++) {
+ bank_size = tegra_pinctrl_get_bank_size(dev, i);
+ regs = pmx->regs[i];
+ for (k = 0; k < bank_size; k++)
+ writel_relaxed(*backup_regs++, regs++);
+ }
+
+ return 0;
+}
+
+const struct dev_pm_ops tegra_pinctrl_pm = {
+ .suspend = &tegra_pinctrl_suspend,
+ .resume = &tegra_pinctrl_resume
+};
+
static bool gpio_node_has_range(const char *compatible)
{
struct device_node *np;
@@ -655,6 +707,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
int i;
const char **group_pins;
int fn, gn, gfn;
+ unsigned long backup_regs_size = 0;
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
if (!pmx)
@@ -707,6 +760,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
if (!res)
break;
+ backup_regs_size += resource_size(res);
}
pmx->nbanks = i;
@@ -715,6 +769,11 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
if (!pmx->regs)
return -ENOMEM;
+ pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
+ GFP_KERNEL);
+ if (!pmx->backup_regs)
+ return -ENOMEM;
+
for (i = 0; i < pmx->nbanks; i++) {
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index 105309774079..0fc82eea9cf1 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -17,6 +17,7 @@ struct tegra_pmx {
int nbanks;
void __iomem **regs;
+ u32 *backup_regs;
};
enum tegra_pinconf_param {
@@ -193,6 +194,8 @@ struct tegra_pinctrl_soc_data {
bool drvtype_in_mux;
};
+extern const struct dev_pm_ops tegra_pinctrl_pm;
+
int tegra_pinctrl_probe(struct platform_device *pdev,
const struct tegra_pinctrl_soc_data *soc_data);
#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v7 00/20] SC7 entry and exit support for Tegra210
From: Sowjanya Komatineni @ 2019-07-31 0:20 UTC (permalink / raw)
To: thierry.reding, jonathanh, tglx, jason, marc.zyngier,
linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, skomatineni, linux-tegra, linux-kernel,
mperttunen, spatra, robh+dt, digetx, devicetree
This patch series includes Tegra210 deepsleep (SC7) support with RTC alarm
wake event.
This series also includes save and restore of PLLs, clocks, OSC contexts
for deepsleep exit to normal operation.
This patch series doesn't support 100% suspend/resume to allow fully
functional state upon resume and we are working on some more drivers suspend
and resume implementations.
[V7]: Changes between V6 & V7 are
- V6 feedback fixes
- Removed patch-0001 from V6 which keeps COP IRQ enabled. Looking
more into ATF FW, it loads SC7 entry FW into IRAM and sets the
COP reset vector to SC7 FW load address and resets COP. So, COP
IRQ can be cleared during suspend.
Note:
Below patch is also needed for SC7 support as GPIO restore need
to happen prior to pinctrl.
https://patchwork.kernel.org/patch/11012077/
[V6]: Changes between V5 & V6 are
- V5 feedback fixes
- DFLL suspend and resume moved to DFLL clock driver
- Add suspend and resume support for CPUFreq driver to explicitly
switch source to safe source of PLLP and disable DFLL clock.
- Fix to super clock driver to enable PLLP branch to CPU before
source switch to PLLP.
- Added save and restore support for super clock driver.
[V5]: Changes between V4 & V5 are
- V4 feedback fixes
[V4]: Changes between V3 & V4 are
- V3 feedback fixes
- Removed park bits clear for EMMC pads in pinctrl-tegra driver
function tegra_pinctrl_clear_parked_bits as based on V3 feedback
parked_bit is updated to parked_bitmask to use with DRV_PINGROUP
as well and thierry posted patch series for this.
- Implemented all peripheral clocks save and restore through their
corresponding clk_ops save_context and restore_context and removed
all direct registers store and restore in clk-tegra210 driver.
- Created separate patch for fence_delay update during PLLU init based
on V3 feedback.
- Added more comments in tegra210_clk_resume regarding dfll restore
sequence and its dependency on peripheral clocks restore.
[V3]: Changes between V2 & V3 are
- V2 feedback fixes
- GPIO restore should happen prior to Pinctrl restore to prevent
glitch on GPIO lines. So using resume_noirq for gpio tegra to allow
gpio resume prior to pinctrl resume.
- Implemented save_context and restore_context callbacks for clock
plls, pll outs and dividers in corresponding drivers.
Note: Peripheral clocks and clock enable and reset need to be in
Tegra210 clock suspend/resume as they need to be in proper sequence
w.r.t DFLL resume for restoring CPU clock.
- Removed gpio-tegra changes for hierarchical support to have PMC as
parent to GPIOs for GPIO wake event support. Thierry is working on
gpiolib for some cleanup before adding hierarchical support. So
holding on to GPIO wake support for now.
[V2] : V1 feedback fixes
Patch 0002: This version still using syscore. Thierry suggest not to
use syscore and waiting on suggestion from Linux Walleij for any better
way of storing current state of pins before suspend entry and restoring
them on resume at very early stage. So left this the same way as V1 and
will address once I get more feedback on this.
Also need to findout and implement proper way of forcing resume order
between pinctrl and gpio driver.
[V1]: Tegra210 SC7 entry and exit thru RTC wake and Power button GPIO wake
using hierarchical IRQ with PMC as parent to GPIO.
Sowjanya Komatineni (20):
pinctrl: tegra: Add suspend and resume support
pinctrl: tegra210: Add Tegra210 pinctrl pm ops
clk: tegra: divider: Save and restore divider rate
clk: tegra: pllout: Save and restore pllout context
clk: tegra: pll: Save and restore pll context
clk: tegra: Support for OSC context save and restore
clk: tegra: clk-periph: Add save and restore support
clk: tegra: clk-super: Fix to enable PLLP branches to CPU
clk: tegra: clk-super: Add save and restore support
clk: tegra: clk-dfll: Add suspend and resume support
cpufreq: tegra124: Add suspend and resume support
clk: tegra210: Use fence_udelay during PLLU init
clk: tegra210: Add suspend and resume support
soc/tegra: pmc: Allow to support more tegras wake
soc/tegra: pmc: Add pmc wake support for tegra210
arm64: tegra: Enable wake from deep sleep on RTC alarm
soc/tegra: pmc: Configure core power request polarity
soc/tegra: pmc: Configure deep sleep control settings
arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings
arm64: dts: tegra210-p3450: Jetson Nano SC7 timings
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 7 ++
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 7 ++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +-
drivers/clk/tegra/clk-dfll.c | 56 +++++++++
drivers/clk/tegra/clk-dfll.h | 2 +
drivers/clk/tegra/clk-divider.c | 11 ++
drivers/clk/tegra/clk-periph-fixed.c | 33 ++++++
drivers/clk/tegra/clk-periph-gate.c | 34 ++++++
drivers/clk/tegra/clk-periph.c | 37 ++++++
drivers/clk/tegra/clk-pll-out.c | 26 +++++
drivers/clk/tegra/clk-pll.c | 112 +++++++++++++-----
drivers/clk/tegra/clk-sdmmc-mux.c | 28 +++++
drivers/clk/tegra/clk-super.c | 53 +++++++++
drivers/clk/tegra/clk-tegra-fixed.c | 15 +++
drivers/clk/tegra/clk-tegra-super-gen4.c | 2 +-
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 1 +
drivers/clk/tegra/clk-tegra210.c | 86 ++++++++++++--
drivers/clk/tegra/clk.c | 14 +++
drivers/clk/tegra/clk.h | 26 +++++
drivers/cpufreq/tegra124-cpufreq.c | 60 ++++++++++
drivers/pinctrl/tegra/pinctrl-tegra.c | 59 ++++++++++
drivers/pinctrl/tegra/pinctrl-tegra.h | 3 +
drivers/pinctrl/tegra/pinctrl-tegra210.c | 1 +
drivers/soc/tegra/pmc.c | 129 ++++++++++++++++++++-
24 files changed, 759 insertions(+), 48 deletions(-)
--
2.7.4
^ permalink raw reply
* linusw/devel build: 6 builds: 0 failed, 6 passed, 13 warnings (v5.3-rc1-8-g2838bf941b12)
From: kernelci.org bot @ 2019-07-31 0:23 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/devel build: 6 builds: 0 failed, 6 passed, 13 warnings (v5.3-rc1-8-g2838bf941b12)
Full Build Summary: https://kernelci.org/build/linusw/branch/devel/kernel/v5.3-rc1-8-g2838bf941b12/
Tree: linusw
Branch: devel
Git Describe: v5.3-rc1-8-g2838bf941b12
Git Commit: 2838bf941b120ec846a3903db13e319368d51b08
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
Built: 6 unique architectures
Warnings Detected:
arc:
nsim_hs_defconfig (gcc-8): 2 warnings
arm64:
arm:
multi_v7_defconfig (gcc-8): 6 warnings
mips:
32r2el_defconfig (gcc-8): 3 warnings
riscv:
defconfig (gcc-8): 2 warnings
x86_64:
Warnings summary:
7 <stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dts:129.4-18: Warning (reg_format): /mdio-bus-mux/mdio@200:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #size-cells value
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #address-cells value
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
================================================================================
Detailed per-defconfig build reports:
--------------------------------------------------------------------------------
32r2el_defconfig (mips, gcc-8) — PASS, 0 errors, 3 warnings, 0 section mismatches
Warnings:
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
--------------------------------------------------------------------------------
defconfig (riscv, gcc-8) — PASS, 0 errors, 2 warnings, 0 section mismatches
Warnings:
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
--------------------------------------------------------------------------------
defconfig (arm64, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
multi_v7_defconfig (arm, gcc-8) — PASS, 0 errors, 6 warnings, 0 section mismatches
Warnings:
arch/arm/boot/dts/bcm47094-linksys-panamera.dts:129.4-18: Warning (reg_format): /mdio-bus-mux/mdio@200:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #address-cells value
arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #size-cells value
--------------------------------------------------------------------------------
nsim_hs_defconfig (arc, gcc-8) — PASS, 0 errors, 2 warnings, 0 section mismatches
Warnings:
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
--------------------------------------------------------------------------------
x86_64_defconfig (x86_64, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
---
For more info write to <info@kernelci.org>
^ permalink raw reply
* linusw/for-next build: 6 builds: 0 failed, 6 passed, 13 warnings (v5.3-rc1-13-gfb9152b494a9)
From: kernelci.org bot @ 2019-07-31 0:23 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/for-next build: 6 builds: 0 failed, 6 passed, 13 warnings (v5.3-rc1-13-gfb9152b494a9)
Full Build Summary: https://kernelci.org/build/linusw/branch/for-next/kernel/v5.3-rc1-13-gfb9152b494a9/
Tree: linusw
Branch: for-next
Git Describe: v5.3-rc1-13-gfb9152b494a9
Git Commit: fb9152b494a9bf9beec11a64b1f796d4e8755d07
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
Built: 6 unique architectures
Warnings Detected:
arc:
nsim_hs_defconfig (gcc-8): 2 warnings
arm64:
arm:
multi_v7_defconfig (gcc-8): 6 warnings
mips:
32r2el_defconfig (gcc-8): 3 warnings
riscv:
defconfig (gcc-8): 2 warnings
x86_64:
Warnings summary:
7 <stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dts:129.4-18: Warning (reg_format): /mdio-bus-mux/mdio@200:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #size-cells value
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #address-cells value
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
1 arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
================================================================================
Detailed per-defconfig build reports:
--------------------------------------------------------------------------------
32r2el_defconfig (mips, gcc-8) — PASS, 0 errors, 3 warnings, 0 section mismatches
Warnings:
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
--------------------------------------------------------------------------------
defconfig (riscv, gcc-8) — PASS, 0 errors, 2 warnings, 0 section mismatches
Warnings:
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
--------------------------------------------------------------------------------
defconfig (arm64, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
multi_v7_defconfig (arm, gcc-8) — PASS, 0 errors, 6 warnings, 0 section mismatches
Warnings:
arch/arm/boot/dts/bcm47094-linksys-panamera.dts:129.4-18: Warning (reg_format): /mdio-bus-mux/mdio@200:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #address-cells value
arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #size-cells value
--------------------------------------------------------------------------------
nsim_hs_defconfig (arc, gcc-8) — PASS, 0 errors, 2 warnings, 0 section mismatches
Warnings:
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
<stdin>:1511:2: warning: #warning syscall clone3 not implemented [-Wcpp]
--------------------------------------------------------------------------------
x86_64_defconfig (x86_64, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
---
For more info write to <info@kernelci.org>
^ permalink raw reply
* linusw/for-next boot: 42 boots: 1 failed, 41 passed (v5.3-rc1-13-gfb9152b494a9)
From: kernelci.org bot @ 2019-07-31 1:08 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/for-next boot: 42 boots: 1 failed, 41 passed (v5.3-rc1-13-gfb9152b494a9)
Full Boot Summary: https://kernelci.org/boot/all/job/linusw/branch/for-next/kernel/v5.3-rc1-13-gfb9152b494a9/
Full Build Summary: https://kernelci.org/build/linusw/branch/for-next/kernel/v5.3-rc1-13-gfb9152b494a9/
Tree: linusw
Branch: for-next
Git Describe: v5.3-rc1-13-gfb9152b494a9
Git Commit: fb9152b494a9bf9beec11a64b1f796d4e8755d07
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
Tested: 31 unique boards, 14 SoC families, 3 builds out of 6
Boot Regressions Detected:
arm64:
defconfig:
gcc-8:
apq8016-sbc:
lab-mhart: failing since 1 day (last pass: v5.2-10813-g88785b7fa74a - first fail: v5.3-rc1-10-gd2a561ae1961)
Boot Failure Detected:
arm64:
defconfig:
gcc-8:
apq8016-sbc: 1 failed lab
---
For more info write to <info@kernelci.org>
^ permalink raw reply
* linusw/devel boot: 48 boots: 1 failed, 47 passed (v5.3-rc1-8-g2838bf941b12)
From: kernelci.org bot @ 2019-07-31 1:08 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/devel boot: 48 boots: 1 failed, 47 passed (v5.3-rc1-8-g2838bf941b12)
Full Boot Summary: https://kernelci.org/boot/all/job/linusw/branch/devel/kernel/v5.3-rc1-8-g2838bf941b12/
Full Build Summary: https://kernelci.org/build/linusw/branch/devel/kernel/v5.3-rc1-8-g2838bf941b12/
Tree: linusw
Branch: devel
Git Describe: v5.3-rc1-8-g2838bf941b12
Git Commit: 2838bf941b120ec846a3903db13e319368d51b08
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
Tested: 34 unique boards, 15 SoC families, 3 builds out of 6
Boot Regressions Detected:
arm64:
defconfig:
gcc-8:
apq8016-sbc:
lab-mhart: failing since 1 day (last pass: v5.2-10808-g9637d517347e - first fail: v5.3-rc1-5-ga299726da44f)
Boot Failure Detected:
arm64:
defconfig:
gcc-8:
apq8016-sbc: 1 failed lab
---
For more info write to <info@kernelci.org>
^ permalink raw reply
* Re: [PATCH v6 15/57] gpio: Remove dev_err() usage after platform_get_irq()
From: Bartosz Golaszewski @ 2019-07-31 7:28 UTC (permalink / raw)
To: Stephen Boyd; +Cc: LKML, Linus Walleij, linux-gpio, Greg Kroah-Hartman
In-Reply-To: <20190730181557.90391-16-swboyd@chromium.org>
wt., 30 lip 2019 o 20:16 Stephen Boyd <swboyd@chromium.org> napisał(a):
>
> We don't need dev_err() messages when platform_get_irq() fails now that
> platform_get_irq() prints an error message itself when something goes
> wrong. Let's remove these prints with a simple semantic patch.
>
> // <smpl>
> @@
> expression ret;
> struct platform_device *E;
> @@
>
> ret =
> (
> platform_get_irq(E, ...)
> |
> platform_get_irq_byname(E, ...)
> );
>
> if ( \( ret < 0 \| ret <= 0 \) )
> {
> (
> -if (ret != -EPROBE_DEFER)
> -{ ...
> -dev_err(...);
> -... }
> |
> ...
> -dev_err(...);
> )
> ...
> }
> // </smpl>
>
> While we're here, remove braces on if statements that only have one
> statement (manually).
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> Cc: linux-gpio@vger.kernel.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
> ---
>
> Please apply directly to subsystem trees
>
> drivers/gpio/gpio-brcmstb.c | 4 +---
> drivers/gpio/gpio-eic-sprd.c | 4 +---
> drivers/gpio/gpio-grgpio.c | 2 --
> drivers/gpio/gpio-max77620.c | 4 +---
> drivers/gpio/gpio-pmic-eic-sprd.c | 4 +---
> drivers/gpio/gpio-sprd.c | 4 +---
> drivers/gpio/gpio-tb10x.c | 4 +---
> drivers/gpio/gpio-tegra.c | 4 +---
> drivers/gpio/gpio-zx.c | 1 -
> drivers/gpio/gpio-zynq.c | 4 +---
> 10 files changed, 8 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c
> index af936dcca659..05e3f99ae59c 100644
> --- a/drivers/gpio/gpio-brcmstb.c
> +++ b/drivers/gpio/gpio-brcmstb.c
> @@ -636,10 +636,8 @@ static int brcmstb_gpio_probe(struct platform_device *pdev)
>
> if (of_property_read_bool(np, "interrupt-controller")) {
> priv->parent_irq = platform_get_irq(pdev, 0);
> - if (priv->parent_irq <= 0) {
> - dev_err(dev, "Couldn't get IRQ");
> + if (priv->parent_irq <= 0)
> return -ENOENT;
> - }
> } else {
> priv->parent_irq = -ENOENT;
> }
> diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c
> index 7b9ac4a12c20..fe7a73f52329 100644
> --- a/drivers/gpio/gpio-eic-sprd.c
> +++ b/drivers/gpio/gpio-eic-sprd.c
> @@ -584,10 +584,8 @@ static int sprd_eic_probe(struct platform_device *pdev)
> sprd_eic->type = pdata->type;
>
> sprd_eic->irq = platform_get_irq(pdev, 0);
> - if (sprd_eic->irq < 0) {
> - dev_err(&pdev->dev, "Failed to get EIC interrupt.\n");
> + if (sprd_eic->irq < 0)
> return sprd_eic->irq;
> - }
>
> for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
> /*
> diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c
> index 0937b605e134..08234e64993a 100644
> --- a/drivers/gpio/gpio-grgpio.c
> +++ b/drivers/gpio/gpio-grgpio.c
> @@ -408,8 +408,6 @@ static int grgpio_probe(struct platform_device *ofdev)
> * Continue without irq functionality for that
> * gpio line
> */
> - dev_err(priv->dev,
> - "Failed to get irq for offset %d\n", i);
> continue;
> }
> priv->uirqs[lirq->index].uirq = ret;
> diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
> index b7d89e30131e..47d05e357e61 100644
> --- a/drivers/gpio/gpio-max77620.c
> +++ b/drivers/gpio/gpio-max77620.c
> @@ -270,10 +270,8 @@ static int max77620_gpio_probe(struct platform_device *pdev)
> int ret;
>
> gpio_irq = platform_get_irq(pdev, 0);
> - if (gpio_irq <= 0) {
> - dev_err(&pdev->dev, "GPIO irq not available %d\n", gpio_irq);
> + if (gpio_irq <= 0)
> return -ENODEV;
> - }
>
> mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
> if (!mgpio)
> diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
> index 24228cf79afc..05000cace9b2 100644
> --- a/drivers/gpio/gpio-pmic-eic-sprd.c
> +++ b/drivers/gpio/gpio-pmic-eic-sprd.c
> @@ -305,10 +305,8 @@ static int sprd_pmic_eic_probe(struct platform_device *pdev)
> mutex_init(&pmic_eic->buslock);
>
> pmic_eic->irq = platform_get_irq(pdev, 0);
> - if (pmic_eic->irq < 0) {
> - dev_err(&pdev->dev, "Failed to get PMIC EIC interrupt.\n");
> + if (pmic_eic->irq < 0)
> return pmic_eic->irq;
> - }
>
> pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL);
> if (!pmic_eic->map)
> diff --git a/drivers/gpio/gpio-sprd.c b/drivers/gpio/gpio-sprd.c
> index f5c8b3a351d5..d7314d39ab65 100644
> --- a/drivers/gpio/gpio-sprd.c
> +++ b/drivers/gpio/gpio-sprd.c
> @@ -226,10 +226,8 @@ static int sprd_gpio_probe(struct platform_device *pdev)
> return -ENOMEM;
>
> sprd_gpio->irq = platform_get_irq(pdev, 0);
> - if (sprd_gpio->irq < 0) {
> - dev_err(&pdev->dev, "Failed to get GPIO interrupt.\n");
> + if (sprd_gpio->irq < 0)
> return sprd_gpio->irq;
> - }
>
> sprd_gpio->base = devm_platform_ioremap_resource(pdev, 0);
> if (IS_ERR(sprd_gpio->base))
> diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c
> index bd1f3f775ce9..5e375186f90e 100644
> --- a/drivers/gpio/gpio-tb10x.c
> +++ b/drivers/gpio/gpio-tb10x.c
> @@ -171,10 +171,8 @@ static int tb10x_gpio_probe(struct platform_device *pdev)
> struct irq_chip_generic *gc;
>
> ret = platform_get_irq(pdev, 0);
> - if (ret < 0) {
> - dev_err(dev, "No interrupt specified.\n");
> + if (ret < 0)
> return ret;
> - }
>
> tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq;
> tb10x_gpio->irq = ret;
> diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
> index 0f59161a4701..8a01d3694b28 100644
> --- a/drivers/gpio/gpio-tegra.c
> +++ b/drivers/gpio/gpio-tegra.c
> @@ -624,10 +624,8 @@ static int tegra_gpio_probe(struct platform_device *pdev)
>
> for (i = 0; i < tgi->bank_count; i++) {
> ret = platform_get_irq(pdev, i);
> - if (ret < 0) {
> - dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret);
> + if (ret < 0)
> return ret;
> - }
>
> bank = &tgi->bank_info[i];
> bank->bank = i;
> diff --git a/drivers/gpio/gpio-zx.c b/drivers/gpio/gpio-zx.c
> index 8637adb6bc20..8d9b9bf8510a 100644
> --- a/drivers/gpio/gpio-zx.c
> +++ b/drivers/gpio/gpio-zx.c
> @@ -253,7 +253,6 @@ static int zx_gpio_probe(struct platform_device *pdev)
> writew_relaxed(0, chip->base + ZX_GPIO_IE);
> irq = platform_get_irq(pdev, 0);
> if (irq < 0) {
> - dev_err(dev, "invalid IRQ\n");
> gpiochip_remove(&chip->gc);
> return -ENODEV;
> }
> diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c
> index f241b6c13dbe..86b0bd256c13 100644
> --- a/drivers/gpio/gpio-zynq.c
> +++ b/drivers/gpio/gpio-zynq.c
> @@ -849,10 +849,8 @@ static int zynq_gpio_probe(struct platform_device *pdev)
> return PTR_ERR(gpio->base_addr);
>
> gpio->irq = platform_get_irq(pdev, 0);
> - if (gpio->irq < 0) {
> - dev_err(&pdev->dev, "invalid IRQ\n");
> + if (gpio->irq < 0)
> return gpio->irq;
> - }
>
> /* configure the gpio chip */
> chip = &gpio->chip;
> --
> Sent by a computer through tubes
>
Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
^ permalink raw reply
* Re: [libgpiod] [PATCH] gpioinfo: mark kernel claimed lines as used
From: Bartosz Golaszewski @ 2019-07-31 7:44 UTC (permalink / raw)
To: Ramon Fried; +Cc: Linus Walleij, linux-gpio
In-Reply-To: <20190730190410.24786-1-rfried.dev@gmail.com>
wt., 30 lip 2019 o 21:04 Ramon Fried <rfried.dev@gmail.com> napisał(a):
>
> In case where the GPIOLINE_FLAG_KERNEL flag was set because of muxing,
> The used column was still showing the pin as "unused"
> Fix that by writing "used".
>
> Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
> ---
> tools/gpioinfo.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/tools/gpioinfo.c b/tools/gpioinfo.c
> index bb17262..85f8758 100644
> --- a/tools/gpioinfo.c
> +++ b/tools/gpioinfo.c
> @@ -119,8 +119,11 @@ static void list_lines(struct gpiod_chip *chip)
> : prinfo(&of, 12, "unnamed");
> printf(" ");
>
> - consumer ? prinfo(&of, 12, "\"%s\"", consumer)
> - : prinfo(&of, 12, "unused");
> + if (gpiod_line_is_used(line) && !consumer)
> + prinfo(&of, 12, "used");
> + else
> + consumer ? prinfo(&of, 12, "\"%s\"", consumer)
> + : prinfo(&of, 12, "unused");
> printf(" ");
>
> prinfo(&of, 8, "%s ", direction == GPIOD_LINE_DIRECTION_INPUT
> --
> 2.22.0
>
Good catch! I think we can make it even more readable by first calling
gpiod_line_is_used() and printing 'unused' if it returns false and
then checking the consumer string.
Bart
^ permalink raw reply
* Re: [libgpiod] [PATCH] gpioinfo: mark kernel claimed lines as used
From: Ramon Fried @ 2019-07-31 7:48 UTC (permalink / raw)
To: Bartosz Golaszewski; +Cc: Linus Walleij, linux-gpio
In-Reply-To: <CAMpxmJUXbxjGqaw+qTiwvAKicjC-MC58BOr6_hw-L76JHWOg0g@mail.gmail.com>
On Wed, Jul 31, 2019 at 10:44 AM Bartosz Golaszewski
<bgolaszewski@baylibre.com> wrote:
>
> wt., 30 lip 2019 o 21:04 Ramon Fried <rfried.dev@gmail.com> napisał(a):
> >
> > In case where the GPIOLINE_FLAG_KERNEL flag was set because of muxing,
> > The used column was still showing the pin as "unused"
> > Fix that by writing "used".
> >
> > Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
> > ---
> > tools/gpioinfo.c | 7 +++++--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/tools/gpioinfo.c b/tools/gpioinfo.c
> > index bb17262..85f8758 100644
> > --- a/tools/gpioinfo.c
> > +++ b/tools/gpioinfo.c
> > @@ -119,8 +119,11 @@ static void list_lines(struct gpiod_chip *chip)
> > : prinfo(&of, 12, "unnamed");
> > printf(" ");
> >
> > - consumer ? prinfo(&of, 12, "\"%s\"", consumer)
> > - : prinfo(&of, 12, "unused");
> > + if (gpiod_line_is_used(line) && !consumer)
> > + prinfo(&of, 12, "used");
> > + else
> > + consumer ? prinfo(&of, 12, "\"%s\"", consumer)
> > + : prinfo(&of, 12, "unused");
> > printf(" ");
> >
> > prinfo(&of, 8, "%s ", direction == GPIOD_LINE_DIRECTION_INPUT
> > --
> > 2.22.0
> >
>
> Good catch! I think we can make it even more readable by first calling
> gpiod_line_is_used() and printing 'unused' if it returns false and
> then checking the consumer string.
OK, I'll send v2.
Thanks,
Ramon.
>
> Bart
^ permalink raw reply
* Re: [libgpiod] [PATCH] gpioinfo: mark kernel claimed lines as used
From: Bartosz Golaszewski @ 2019-07-31 7:50 UTC (permalink / raw)
To: Ramon Fried; +Cc: Linus Walleij, linux-gpio
In-Reply-To: <CAGi-RUJ7FHt5LbGD22rcO-=vjaeAWdjGWt+TO6HUACvEkpBHAg@mail.gmail.com>
śr., 31 lip 2019 o 09:48 Ramon Fried <rfried.dev@gmail.com> napisał(a):
>
> On Wed, Jul 31, 2019 at 10:44 AM Bartosz Golaszewski
> <bgolaszewski@baylibre.com> wrote:
> >
> > wt., 30 lip 2019 o 21:04 Ramon Fried <rfried.dev@gmail.com> napisał(a):
> > >
> > > In case where the GPIOLINE_FLAG_KERNEL flag was set because of muxing,
> > > The used column was still showing the pin as "unused"
> > > Fix that by writing "used".
> > >
> > > Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
> > > ---
> > > tools/gpioinfo.c | 7 +++++--
> > > 1 file changed, 5 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/tools/gpioinfo.c b/tools/gpioinfo.c
> > > index bb17262..85f8758 100644
> > > --- a/tools/gpioinfo.c
> > > +++ b/tools/gpioinfo.c
> > > @@ -119,8 +119,11 @@ static void list_lines(struct gpiod_chip *chip)
> > > : prinfo(&of, 12, "unnamed");
> > > printf(" ");
> > >
> > > - consumer ? prinfo(&of, 12, "\"%s\"", consumer)
> > > - : prinfo(&of, 12, "unused");
> > > + if (gpiod_line_is_used(line) && !consumer)
> > > + prinfo(&of, 12, "used");
> > > + else
> > > + consumer ? prinfo(&of, 12, "\"%s\"", consumer)
> > > + : prinfo(&of, 12, "unused");
> > > printf(" ");
> > >
> > > prinfo(&of, 8, "%s ", direction == GPIOD_LINE_DIRECTION_INPUT
> > > --
> > > 2.22.0
> > >
> >
> > Good catch! I think we can make it even more readable by first calling
> > gpiod_line_is_used() and printing 'unused' if it returns false and
> > then checking the consumer string.
> OK, I'll send v2.
> Thanks,
> Ramon.
> >
> > Bart
Cool, I'm also thinking that we need to distinguish somehow regular
consumer strings from lines used by kernel. Maybe a string like
'[kernel]' instead of 'used' would be nice?
Bart
^ permalink raw reply
* Re: [PATCH v7 07/20] clk: tegra: clk-periph: Add save and restore support
From: Dmitry Osipenko @ 2019-07-31 9:50 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1564532424-10449-8-git-send-email-skomatineni@nvidia.com>
31.07.2019 3:20, Sowjanya Komatineni пишет:
> This patch implements save and restore context for peripheral fixed
> clock ops, peripheral gate clock ops, sdmmc mux clock ops, and
> peripheral clock ops.
>
> During system suspend, core power goes off and looses the settings
> of the Tegra CAR controller registers.
>
> So during suspend entry clock and reset state of peripherals is saved
> and on resume they are restored to have clocks back to same rate and
> state as before suspend.
>
> Acked-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-periph-fixed.c | 33 ++++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk-periph-gate.c | 34 +++++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk-periph.c | 37 ++++++++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk-sdmmc-mux.c | 28 +++++++++++++++++++++++++++
> drivers/clk/tegra/clk.h | 6 ++++++
> 5 files changed, 138 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-periph-fixed.c b/drivers/clk/tegra/clk-periph-fixed.c
> index c088e7a280df..21b24530fa00 100644
> --- a/drivers/clk/tegra/clk-periph-fixed.c
> +++ b/drivers/clk/tegra/clk-periph-fixed.c
> @@ -60,11 +60,44 @@ tegra_clk_periph_fixed_recalc_rate(struct clk_hw *hw,
> return (unsigned long)rate;
> }
>
> +static int tegra_clk_periph_fixed_save_context(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
> + u32 mask = 1 << (fixed->num % 32);
> +
> + fixed->enb_ctx = readl_relaxed(fixed->base + fixed->regs->enb_reg) &
> + mask;
> + fixed->rst_ctx = readl_relaxed(fixed->base + fixed->regs->rst_reg) &
> + mask;
> +
> + return 0;
> +}
> +
> +static void tegra_clk_periph_fixed_restore_context(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
> + u32 mask = 1 << (fixed->num % 32);
> +
> + if (fixed->enb_ctx)
> + writel_relaxed(mask, fixed->base + fixed->regs->enb_set_reg);
> + else
> + writel_relaxed(mask, fixed->base + fixed->regs->enb_clr_reg);
> +
> + udelay(2);
> +
> + if (!fixed->rst_ctx) {
> + udelay(5); /* reset propogation delay */
> + writel_relaxed(mask, fixed->base + fixed->regs->rst_reg);
> + }
> +}
> +
> static const struct clk_ops tegra_clk_periph_fixed_ops = {
> .is_enabled = tegra_clk_periph_fixed_is_enabled,
> .enable = tegra_clk_periph_fixed_enable,
> .disable = tegra_clk_periph_fixed_disable,
> .recalc_rate = tegra_clk_periph_fixed_recalc_rate,
> + .save_context = tegra_clk_periph_fixed_save_context,
> + .restore_context = tegra_clk_periph_fixed_restore_context,
> };
>
> struct clk *tegra_clk_register_periph_fixed(const char *name,
> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
> index 4b31beefc9fc..6ba5b08e0787 100644
> --- a/drivers/clk/tegra/clk-periph-gate.c
> +++ b/drivers/clk/tegra/clk-periph-gate.c
> @@ -25,6 +25,8 @@ static DEFINE_SPINLOCK(periph_ref_lock);
>
> #define read_rst(gate) \
> readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
> +#define write_rst_set(val, gate) \
> + writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
> #define write_rst_clr(val, gate) \
> writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
>
> @@ -110,10 +112,42 @@ static void clk_periph_disable(struct clk_hw *hw)
> spin_unlock_irqrestore(&periph_ref_lock, flags);
> }
>
> +static int clk_periph_gate_save_context(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
> +
> + gate->clk_state_ctx = read_enb(gate) & periph_clk_to_bit(gate);
> + gate->rst_state_ctx = read_rst(gate) & periph_clk_to_bit(gate);
> +
> + return 0;
> +}
> +
> +static void clk_periph_gate_restore_context(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
> +
> + if (gate->clk_state_ctx)
> + write_enb_set(periph_clk_to_bit(gate), gate);
> + else
> + write_enb_clr(periph_clk_to_bit(gate), gate);
> +
> + udelay(5);
> +
> + if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
> + !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
> + if (gate->rst_state_ctx)
> + write_rst_set(periph_clk_to_bit(gate), gate);
> + else
> + write_rst_clr(periph_clk_to_bit(gate), gate);
> + }
> +}
> +
> const struct clk_ops tegra_clk_periph_gate_ops = {
> .is_enabled = clk_periph_is_enabled,
> .enable = clk_periph_enable,
> .disable = clk_periph_disable,
> + .save_context = clk_periph_gate_save_context,
> + .restore_context = clk_periph_gate_restore_context,
> };
>
> struct clk *tegra_clk_register_periph_gate(const char *name,
> diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
> index 58437da25156..06fb62955768 100644
> --- a/drivers/clk/tegra/clk-periph.c
> +++ b/drivers/clk/tegra/clk-periph.c
> @@ -99,6 +99,37 @@ static void clk_periph_disable(struct clk_hw *hw)
> gate_ops->disable(gate_hw);
> }
>
> +static int clk_periph_save_context(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *gate_ops = periph->gate_ops;
> + struct clk_hw *gate_hw = &periph->gate.hw;
> +
> + if (!(periph->gate.flags & TEGRA_PERIPH_NO_GATE))
> + gate_ops->save_context(gate_hw);
> +
> + periph->parent_ctx = clk_periph_get_parent(hw);
> +
> + return 0;
> +}
> +
> +static void clk_periph_restore_context(struct clk_hw *hw)
> +{
> + struct tegra_clk_periph *periph = to_clk_periph(hw);
> + const struct clk_ops *gate_ops = periph->gate_ops;
> + struct clk_hw *gate_hw = &periph->gate.hw;
> + const struct clk_ops *div_ops = periph->div_ops;
> + struct clk_hw *div_hw = &periph->divider.hw;
> +
> + clk_periph_set_parent(hw, periph->parent_ctx);
> +
> + if (!(periph->gate.flags & TEGRA_PERIPH_NO_DIV))
> + div_ops->restore_context(div_hw);
Could you please point to where the divider's save_context() happens?
Because I can't see it.
> + if (!(periph->gate.flags & TEGRA_PERIPH_NO_GATE))
> + gate_ops->restore_context(gate_hw);
> +}
> +
> const struct clk_ops tegra_clk_periph_ops = {
> .get_parent = clk_periph_get_parent,
> .set_parent = clk_periph_set_parent,
> @@ -108,6 +139,8 @@ const struct clk_ops tegra_clk_periph_ops = {
> .is_enabled = clk_periph_is_enabled,
> .enable = clk_periph_enable,
> .disable = clk_periph_disable,
> + .save_context = clk_periph_save_context,
> + .restore_context = clk_periph_restore_context,
> };
>
> static const struct clk_ops tegra_clk_periph_nodiv_ops = {
> @@ -116,6 +149,8 @@ static const struct clk_ops tegra_clk_periph_nodiv_ops = {
> .is_enabled = clk_periph_is_enabled,
> .enable = clk_periph_enable,
> .disable = clk_periph_disable,
> + .save_context = clk_periph_save_context,
> + .restore_context = clk_periph_restore_context,
> };
>
> static const struct clk_ops tegra_clk_periph_no_gate_ops = {
> @@ -124,6 +159,8 @@ static const struct clk_ops tegra_clk_periph_no_gate_ops = {
> .recalc_rate = clk_periph_recalc_rate,
> .round_rate = clk_periph_round_rate,
> .set_rate = clk_periph_set_rate,
> + .save_context = clk_periph_save_context,
> + .restore_context = clk_periph_restore_context,
> };
>
> static struct clk *_tegra_clk_register_periph(const char *name,
> diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c b/drivers/clk/tegra/clk-sdmmc-mux.c
> index a5cd3e31dbae..48da9d7fea80 100644
> --- a/drivers/clk/tegra/clk-sdmmc-mux.c
> +++ b/drivers/clk/tegra/clk-sdmmc-mux.c
> @@ -194,6 +194,32 @@ static void clk_sdmmc_mux_disable(struct clk_hw *hw)
> gate_ops->disable(gate_hw);
> }
>
> +static int clk_sdmmc_mux_save_context(struct clk_hw *hw)
> +{
> + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
> + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
> + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
> +
> + sdmmc_mux->parent_ctx = clk_sdmmc_mux_get_parent(hw);
> + gate_ops->save_context(gate_hw);
> +
> + return 0;
> +}
> +
> +static void clk_sdmmc_mux_restore_context(struct clk_hw *hw)
> +{
> + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
> + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
> + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
> + struct clk_hw *parent = clk_hw_get_parent(hw);
> + unsigned long parent_rate = clk_hw_get_rate(parent);
> + unsigned long rate = clk_hw_get_rate(hw);
> +
> + clk_sdmmc_mux_set_parent(hw, sdmmc_mux->parent_ctx);
> + clk_sdmmc_mux_set_rate(hw, rate, parent_rate);
> + gate_ops->restore_context(gate_hw);
> +}
> +
> static const struct clk_ops tegra_clk_sdmmc_mux_ops = {
> .get_parent = clk_sdmmc_mux_get_parent,
> .set_parent = clk_sdmmc_mux_set_parent,
> @@ -203,6 +229,8 @@ static const struct clk_ops tegra_clk_sdmmc_mux_ops = {
> .is_enabled = clk_sdmmc_mux_is_enabled,
> .enable = clk_sdmmc_mux_enable,
> .disable = clk_sdmmc_mux_disable,
> + .save_context = clk_sdmmc_mux_save_context,
> + .restore_context = clk_sdmmc_mux_restore_context,
> };
>
> struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index abba6d8a04cd..d61e61eebf4a 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -517,6 +517,8 @@ struct tegra_clk_periph_gate {
> int clk_num;
> int *enable_refcnt;
> const struct tegra_clk_periph_regs *regs;
> + bool clk_state_ctx;
> + bool rst_state_ctx;
> };
>
> #define to_clk_periph_gate(_hw) \
> @@ -543,6 +545,8 @@ struct tegra_clk_periph_fixed {
> unsigned int mul;
> unsigned int div;
> unsigned int num;
> + bool enb_ctx;
> + bool rst_ctx;
> };
>
> struct clk *tegra_clk_register_periph_fixed(const char *name,
> @@ -575,6 +579,7 @@ struct tegra_clk_periph {
> const struct clk_ops *mux_ops;
> const struct clk_ops *div_ops;
> const struct clk_ops *gate_ops;
> + u8 parent_ctx;
> };
>
> #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
> @@ -726,6 +731,7 @@ struct tegra_sdmmc_mux {
> const struct clk_ops *gate_ops;
> struct tegra_clk_periph_gate gate;
> u8 div_flags;
> + u8 parent_ctx;
> };
>
> #define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw)
>
^ permalink raw reply
* [PATCH] gpio: ixp4xx: remove redundant dev_err message
From: Ding Xiang @ 2019-07-31 9:47 UTC (permalink / raw)
To: linus.walleij, bgolaszewski; +Cc: linux-gpio, linux-kernel
devm_ioremap_resource already contains error message, so remove
the redundant dev_err message
Signed-off-by: Ding Xiang <dingxiang@cmss.chinamobile.com>
---
drivers/gpio/gpio-ixp4xx.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c
index 670c2a8..2b2b89b 100644
--- a/drivers/gpio/gpio-ixp4xx.c
+++ b/drivers/gpio/gpio-ixp4xx.c
@@ -321,10 +321,8 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
g->base = devm_ioremap_resource(dev, res);
- if (IS_ERR(g->base)) {
- dev_err(dev, "ioremap error\n");
+ if (IS_ERR(g->base))
return PTR_ERR(g->base);
- }
/*
* Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on
--
1.9.1
^ permalink raw reply related
* [PATCH] gpio: remove duplicated function definition
From: YueHaibing @ 2019-07-31 10:00 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, yamada.masahiro
Cc: linux-kernel, linux-gpio, YueHaibing
when building without CONFIG_PINCTRL:
In file included from drivers/hwmon/pmbus/ucd9000.c:19:0:
./include/linux/gpio/driver.h:576:1: error: redefinition of gpiochip_add_pin_range
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
^~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/hwmon/pmbus/ucd9000.c:18:0:
./include/linux/gpio.h:245:1: note: previous definition of gpiochip_add_pin_range was here
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
^~~~~~~~~~~~~~~~~~~~~~
Reported-by: Hulk Robot <hulkci@huawei.com>
Fixes: 964cb341882f ("gpio: move pincontrol calls to <linux/gpio/driver.h>")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
---
include/linux/gpio/driver.h | 35 +----------------------------------
1 file changed, 1 insertion(+), 34 deletions(-)
diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
index f28f534..09f96ec 100644
--- a/include/linux/gpio/driver.h
+++ b/include/linux/gpio/driver.h
@@ -10,6 +10,7 @@
#include <linux/lockdep.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/gpio.h>
struct gpio_desc;
struct of_phandle_args;
@@ -560,40 +561,6 @@ struct gpio_pin_range {
struct pinctrl_gpio_range range;
};
-#ifdef CONFIG_PINCTRL
-
-int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
- unsigned int gpio_offset, unsigned int pin_offset,
- unsigned int npins);
-int gpiochip_add_pingroup_range(struct gpio_chip *chip,
- struct pinctrl_dev *pctldev,
- unsigned int gpio_offset, const char *pin_group);
-void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
-
-#else /* ! CONFIG_PINCTRL */
-
-static inline int
-gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
- unsigned int gpio_offset, unsigned int pin_offset,
- unsigned int npins)
-{
- return 0;
-}
-static inline int
-gpiochip_add_pingroup_range(struct gpio_chip *chip,
- struct pinctrl_dev *pctldev,
- unsigned int gpio_offset, const char *pin_group)
-{
- return 0;
-}
-
-static inline void
-gpiochip_remove_pin_ranges(struct gpio_chip *chip)
-{
-}
-
-#endif /* CONFIG_PINCTRL */
-
struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
const char *label,
enum gpio_lookup_flags lflags,
--
2.7.4
^ permalink raw reply related
* Re: [PATCH] gpio: ixp4xx: remove redundant dev_err message
From: Bartosz Golaszewski @ 2019-07-31 10:05 UTC (permalink / raw)
To: Ding Xiang; +Cc: Linus Walleij, linux-gpio, LKML
In-Reply-To: <1564566474-18294-1-git-send-email-dingxiang@cmss.chinamobile.com>
śr., 31 lip 2019 o 11:48 Ding Xiang <dingxiang@cmss.chinamobile.com> napisał(a):
>
> devm_ioremap_resource already contains error message, so remove
> the redundant dev_err message
>
> Signed-off-by: Ding Xiang <dingxiang@cmss.chinamobile.com>
> ---
> drivers/gpio/gpio-ixp4xx.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c
> index 670c2a8..2b2b89b 100644
> --- a/drivers/gpio/gpio-ixp4xx.c
> +++ b/drivers/gpio/gpio-ixp4xx.c
> @@ -321,10 +321,8 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev)
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> g->base = devm_ioremap_resource(dev, res);
> - if (IS_ERR(g->base)) {
> - dev_err(dev, "ioremap error\n");
> + if (IS_ERR(g->base))
> return PTR_ERR(g->base);
> - }
>
> /*
> * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on
> --
> 1.9.1
>
>
>
Patch applied, thanks!
Bart
^ permalink raw reply
* Re: [PATCH v7 10/20] clk: tegra: clk-dfll: Add suspend and resume support
From: Dmitry Osipenko @ 2019-07-31 10:12 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1564532424-10449-11-git-send-email-skomatineni@nvidia.com>
31.07.2019 3:20, Sowjanya Komatineni пишет:
> This patch implements DFLL suspend and resume operation.
>
> During system suspend entry, CPU clock will switch CPU to safe
> clock source of PLLP and disables DFLL clock output.
>
> DFLL driver suspend confirms DFLL disable state and errors out on
> being active.
>
> DFLL is re-initialized during the DFLL driver resume as it goes
> through complete reset during suspend entry.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-dfll.c | 56 ++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk-dfll.h | 2 ++
> drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 1 +
> 3 files changed, 59 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
> index f8688c2ddf1a..9900097ec2aa 100644
> --- a/drivers/clk/tegra/clk-dfll.c
> +++ b/drivers/clk/tegra/clk-dfll.c
> @@ -1513,6 +1513,62 @@ static int dfll_init(struct tegra_dfll *td)
> return ret;
> }
>
> +/**
> + * tegra_dfll_suspend - check DFLL is disabled
> + * @dev: DFLL device *
> + *
> + * DFLL clock should be disabled by the CPUFreq driver. So, make
> + * sure it is disabled and disable all clocks needed by the DFLL.
> + */
> +int tegra_dfll_suspend(struct device *dev)
> +{
> + struct tegra_dfll *td = dev_get_drvdata(dev);
> +
> + if (dfll_is_running(td)) {
> + dev_err(td->dev, "dfll is enabled while shouldn't be\n");
> + return -EBUSY;
> + }
> +
> + reset_control_assert(td->dvco_rst);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(tegra_dfll_suspend);
> +
> +/**
> + * tegra_dfll_resume - reinitialize DFLL on resume
> + * @dev: DFLL instance
> + *
> + * DFLL is disabled and reset during suspend and resume.
> + * So, reinitialize the DFLL IP block back for use.
> + * DFLL clock is enabled later in closed loop mode by CPUFreq
> + * driver before switching its clock source to DFLL output.
> + */
> +int tegra_dfll_resume(struct device *dev)
> +{
> + struct tegra_dfll *td = dev_get_drvdata(dev);
> +
> + reset_control_deassert(td->dvco_rst);
> +
> + pm_runtime_irq_safe(td->dev);
1. Interrupts are allowed here.
2. It's enough to invoke that function once during probe.
3. That function bumps runtime-enable count of the parent, which
immediately should raise some questions.
Corollary: you should remove pm_runtime_irq_safe() because it is not needed.
> + pm_runtime_get_sync(td->dev);
> +
> + dfll_set_mode(td, DFLL_DISABLED);
> + dfll_set_default_params(td);
> +
> + if (td->soc->init_clock_trimmers)
> + td->soc->init_clock_trimmers();
> +
> + dfll_set_open_loop_config(td);
> +
> + dfll_init_out_if(td);
> +
> + pm_runtime_put_sync(td->dev);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(tegra_dfll_resume);
> +
> /*
> * DT data fetch
> */
> diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h
> index 1b14ebe7268b..fb209eb5f365 100644
> --- a/drivers/clk/tegra/clk-dfll.h
> +++ b/drivers/clk/tegra/clk-dfll.h
> @@ -42,5 +42,7 @@ int tegra_dfll_register(struct platform_device *pdev,
> struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);
> int tegra_dfll_runtime_suspend(struct device *dev);
> int tegra_dfll_runtime_resume(struct device *dev);
> +int tegra_dfll_suspend(struct device *dev);
> +int tegra_dfll_resume(struct device *dev);
>
> #endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */
> diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> index e84b6d52cbbd..2ac2679d696d 100644
> --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> @@ -631,6 +631,7 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev)
> static const struct dev_pm_ops tegra124_dfll_pm_ops = {
> SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
> tegra_dfll_runtime_resume, NULL)
> + SET_SYSTEM_SLEEP_PM_OPS(tegra_dfll_suspend, tegra_dfll_resume)
> };
>
> static struct platform_driver tegra124_dfll_fcpu_driver = {
>
^ permalink raw reply
* Re: [PATCH v7 08/20] clk: tegra: clk-super: Fix to enable PLLP branches to CPU
From: Dmitry Osipenko @ 2019-07-31 10:14 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1564532424-10449-9-git-send-email-skomatineni@nvidia.com>
31.07.2019 3:20, Sowjanya Komatineni пишет:
> This patch has a fix to enable PLLP branches to CPU before changing
> the CPU clusters clock source to PLLP for Gen5 Super clock and
> disables PLLP branches to CPU when not in use.
>
> During system suspend entry and exit, CPU source will be switched
> to PLLP and this needs PLLP branches to be enabled to CPU prior to
> the switch.
>
> On system resume, warmboot code enables PLLP branches to CPU and
> powers up the CPU with PLLP clock source.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-super.c | 14 ++++++++++++++
> drivers/clk/tegra/clk-tegra-super-gen4.c | 2 +-
> drivers/clk/tegra/clk.c | 14 ++++++++++++++
> drivers/clk/tegra/clk.h | 5 +++++
> 4 files changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
> index 39ef31b46df5..e2a1e95a8db7 100644
> --- a/drivers/clk/tegra/clk-super.c
> +++ b/drivers/clk/tegra/clk-super.c
> @@ -28,6 +28,9 @@
> #define super_state_to_src_shift(m, s) ((m->width * s))
> #define super_state_to_src_mask(m) (((1 << m->width) - 1))
>
> +#define CCLK_SRC_PLLP_OUT0 4
> +#define CCLK_SRC_PLLP_OUT4 5
> +
> static u8 clk_super_get_parent(struct clk_hw *hw)
> {
> struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
> @@ -97,12 +100,23 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
> if (index == mux->div2_index)
> index = mux->pllx_index;
> }
> +
> + /* enable PLLP branches to CPU before selecting PLLP source */
> + if ((mux->flags & TEGRA210_CPU_CLK) &&
> + (index == CCLK_SRC_PLLP_OUT0 || index == CCLK_SRC_PLLP_OUT4))
> + tegra_clk_set_pllp_out_cpu(true);
> +
> val &= ~((super_state_to_src_mask(mux)) << shift);
> val |= (index & (super_state_to_src_mask(mux))) << shift;
>
> writel_relaxed(val, mux->reg);
> udelay(2);
>
> + /* disable PLLP branches to CPU if not used */
> + if ((mux->flags & TEGRA210_CPU_CLK) &&
> + index != CCLK_SRC_PLLP_OUT0 && index != CCLK_SRC_PLLP_OUT4)
> + tegra_clk_set_pllp_out_cpu(false);
> +
> out:
> if (mux->lock)
> spin_unlock_irqrestore(mux->lock, flags);
> diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
> index cdfe7c9697e1..888d76b01c75 100644
> --- a/drivers/clk/tegra/clk-tegra-super-gen4.c
> +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
> @@ -180,7 +180,7 @@ static void __init tegra_super_clk_init(void __iomem *clk_base,
> gen_info->num_cclk_g_parents,
> CLK_SET_RATE_PARENT,
> clk_base + CCLKG_BURST_POLICY,
> - 0, 4, 8, 0, NULL);
> + TEGRA210_CPU_CLK, 4, 8, 0, NULL);
Don't we want a clarifying comment for cclk_lp telling why it doesn't
have the TEGRA210_CPU_CLK flag?
> } else {
> clk = tegra_clk_register_super_mux("cclk_g",
> gen_info->cclk_g_parents,
> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> index 573e3c967ae1..eb08047fd02f 100644
> --- a/drivers/clk/tegra/clk.c
> +++ b/drivers/clk/tegra/clk.c
> @@ -23,6 +23,7 @@
> #define CLK_OUT_ENB_W 0x364
> #define CLK_OUT_ENB_X 0x280
> #define CLK_OUT_ENB_Y 0x298
> +#define CLK_ENB_PLLP_OUT_CPU BIT(31)
> #define CLK_OUT_ENB_SET_L 0x320
> #define CLK_OUT_ENB_CLR_L 0x324
> #define CLK_OUT_ENB_SET_H 0x328
> @@ -199,6 +200,19 @@ const struct tegra_clk_periph_regs *get_reg_bank(int clkid)
> }
> }
>
> +void tegra_clk_set_pllp_out_cpu(bool enable)
> +{
> + u32 val;
> +
> + val = readl_relaxed(clk_base + CLK_OUT_ENB_Y);
> + if (enable)
> + val |= CLK_ENB_PLLP_OUT_CPU;
> + else
> + val &= ~CLK_ENB_PLLP_OUT_CPU;
> +
> + writel_relaxed(val, clk_base + CLK_OUT_ENB_Y);
> +}
> +
> struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
> {
> clk_base = regs;
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index d61e61eebf4a..f8de447f505b 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -687,6 +687,9 @@ struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
> * Flags:
> * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
> * that this is LP cluster clock.
> + * TEGRA210_CPU_CLK - This flag indicates this is CPU cluster clock. To use
> + * PLLP for CPU clock source, need to enable PLLP branches to CPU by setting
> + * additional bit PLLP_OUT_CPU for gen5 super clock.
> */
> struct tegra_clk_super_mux {
> struct clk_hw hw;
> @@ -703,6 +706,7 @@ struct tegra_clk_super_mux {
> #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
>
> #define TEGRA_DIVIDER_2 BIT(0)
> +#define TEGRA210_CPU_CLK BIT(1)
>
> extern const struct clk_ops tegra_clk_super_ops;
> struct clk *tegra_clk_register_super_mux(const char *name,
> @@ -849,6 +853,7 @@ int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
> int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
> u8 frac_width, u8 flags);
> void tegra_clk_osc_resume(void __iomem *clk_base);
> +void tegra_clk_set_pllp_out_cpu(bool enable);
>
>
> /* Combined read fence with delay */
>
^ permalink raw reply
* Re: [PATCH v7 11/20] cpufreq: tegra124: Add suspend and resume support
From: Dmitry Osipenko @ 2019-07-31 10:23 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1564532424-10449-12-git-send-email-skomatineni@nvidia.com>
31.07.2019 3:20, Sowjanya Komatineni пишет:
> This patch adds suspend and resume pm ops for cpufreq driver.
>
> PLLP is the safe clock source for CPU during system suspend and
> resume as PLLP rate is below the CPU Fmax at Vmin.
>
> CPUFreq driver suspend switches the CPU clock source to PLLP and
> disables the DFLL clock.
>
> During system resume, warmboot code powers up the CPU with PLLP
> clock source. So CPUFreq driver resume enabled DFLL clock and
> switches CPU back to DFLL clock source.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/cpufreq/tegra124-cpufreq.c | 60 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c
> index 4f0c637b3b49..e979a3370988 100644
> --- a/drivers/cpufreq/tegra124-cpufreq.c
> +++ b/drivers/cpufreq/tegra124-cpufreq.c
> @@ -6,6 +6,7 @@
> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>
> #include <linux/clk.h>
> +#include <linux/cpufreq.h>
> #include <linux/err.h>
> #include <linux/init.h>
> #include <linux/kernel.h>
> @@ -128,8 +129,67 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
> return ret;
> }
>
> +static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev)
> +{
> + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
> + int err;
> +
> + /*
> + * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to
> + * use during suspend and resume. So, switch the CPU clock source
> + * to PLLP and disable DFLL.
> + */
> + err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);
> + if (err < 0) {
> + dev_err(dev, "failed to reparent to PLLP: %d\n", err);
> + return err;
> + }
> +
> + /* disable DFLL clock */
> + clk_disable_unprepare(priv->dfll_clk);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused tegra124_cpufreq_resume(struct device *dev)
> +{
> + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
> + int err;
> +
> + /*
> + * Warmboot code powers up the CPU with PLLP clock source.
> + * Enable DFLL clock and switch CPU clock source back to DFLL.
> + */
> + err = clk_prepare_enable(priv->dfll_clk);
> + if (err < 0) {
> + dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err);
> + goto disable_cpufreq;
> + }
> +
> + err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);
> + if (err < 0) {
> + dev_err(dev, "failed to reparent to DFLL clock: %d\n", err);
> + goto disable_dfll;
> + }
> +
> + return 0;
> +
> +disable_dfll:
> + clk_disable_unprepare(priv->dfll_clk);
> +disable_cpufreq:
> + disable_cpufreq();
> +
> + return err;
> +}
> +
> +static const struct dev_pm_ops tegra124_cpufreq_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
> + tegra124_cpufreq_resume)
> +};
> +
> static struct platform_driver tegra124_cpufreq_platdrv = {
> .driver.name = "cpufreq-tegra124",
> + .driver.pm = &tegra124_cpufreq_pm_ops,
> .probe = tegra124_cpufreq_probe,
> };
>
>
Looks good,
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
^ permalink raw reply
* Re: [PATCH v7 07/20] clk: tegra: clk-periph: Add save and restore support
From: Dmitry Osipenko @ 2019-07-31 10:44 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <f90cf34d-c294-b23d-38e3-6de9a8fca7d6@gmail.com>
31.07.2019 12:50, Dmitry Osipenko пишет:
> 31.07.2019 3:20, Sowjanya Komatineni пишет:
>> This patch implements save and restore context for peripheral fixed
>> clock ops, peripheral gate clock ops, sdmmc mux clock ops, and
>> peripheral clock ops.
>>
>> During system suspend, core power goes off and looses the settings
>> of the Tegra CAR controller registers.
>>
>> So during suspend entry clock and reset state of peripherals is saved
>> and on resume they are restored to have clocks back to same rate and
>> state as before suspend.
>>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> drivers/clk/tegra/clk-periph-fixed.c | 33 ++++++++++++++++++++++++++++++++
>> drivers/clk/tegra/clk-periph-gate.c | 34 +++++++++++++++++++++++++++++++++
>> drivers/clk/tegra/clk-periph.c | 37 ++++++++++++++++++++++++++++++++++++
>> drivers/clk/tegra/clk-sdmmc-mux.c | 28 +++++++++++++++++++++++++++
>> drivers/clk/tegra/clk.h | 6 ++++++
>> 5 files changed, 138 insertions(+)
>>
>> diff --git a/drivers/clk/tegra/clk-periph-fixed.c b/drivers/clk/tegra/clk-periph-fixed.c
>> index c088e7a280df..21b24530fa00 100644
>> --- a/drivers/clk/tegra/clk-periph-fixed.c
>> +++ b/drivers/clk/tegra/clk-periph-fixed.c
>> @@ -60,11 +60,44 @@ tegra_clk_periph_fixed_recalc_rate(struct clk_hw *hw,
>> return (unsigned long)rate;
>> }
>>
>> +static int tegra_clk_periph_fixed_save_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
>> + u32 mask = 1 << (fixed->num % 32);
>> +
>> + fixed->enb_ctx = readl_relaxed(fixed->base + fixed->regs->enb_reg) &
>> + mask;
>> + fixed->rst_ctx = readl_relaxed(fixed->base + fixed->regs->rst_reg) &
>> + mask;
>> +
>> + return 0;
>> +}
>> +
>> +static void tegra_clk_periph_fixed_restore_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
>> + u32 mask = 1 << (fixed->num % 32);
>> +
>> + if (fixed->enb_ctx)
>> + writel_relaxed(mask, fixed->base + fixed->regs->enb_set_reg);
>> + else
>> + writel_relaxed(mask, fixed->base + fixed->regs->enb_clr_reg);
>> +
>> + udelay(2);
>> +
>> + if (!fixed->rst_ctx) {
>> + udelay(5); /* reset propogation delay */
>> + writel_relaxed(mask, fixed->base + fixed->regs->rst_reg);
>> + }
>> +}
>> +
>> static const struct clk_ops tegra_clk_periph_fixed_ops = {
>> .is_enabled = tegra_clk_periph_fixed_is_enabled,
>> .enable = tegra_clk_periph_fixed_enable,
>> .disable = tegra_clk_periph_fixed_disable,
>> .recalc_rate = tegra_clk_periph_fixed_recalc_rate,
>> + .save_context = tegra_clk_periph_fixed_save_context,
>> + .restore_context = tegra_clk_periph_fixed_restore_context,
>> };
>>
>> struct clk *tegra_clk_register_periph_fixed(const char *name,
>> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
>> index 4b31beefc9fc..6ba5b08e0787 100644
>> --- a/drivers/clk/tegra/clk-periph-gate.c
>> +++ b/drivers/clk/tegra/clk-periph-gate.c
>> @@ -25,6 +25,8 @@ static DEFINE_SPINLOCK(periph_ref_lock);
>>
>> #define read_rst(gate) \
>> readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
>> +#define write_rst_set(val, gate) \
>> + writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
>> #define write_rst_clr(val, gate) \
>> writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
>>
>> @@ -110,10 +112,42 @@ static void clk_periph_disable(struct clk_hw *hw)
>> spin_unlock_irqrestore(&periph_ref_lock, flags);
>> }
>>
>> +static int clk_periph_gate_save_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
>> +
>> + gate->clk_state_ctx = read_enb(gate) & periph_clk_to_bit(gate);
>> + gate->rst_state_ctx = read_rst(gate) & periph_clk_to_bit(gate);
>> +
>> + return 0;
>> +}
>> +
>> +static void clk_periph_gate_restore_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
>> +
>> + if (gate->clk_state_ctx)
>> + write_enb_set(periph_clk_to_bit(gate), gate);
>> + else
>> + write_enb_clr(periph_clk_to_bit(gate), gate);
>> +
>> + udelay(5);
>> +
>> + if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
>> + !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
>> + if (gate->rst_state_ctx)
>> + write_rst_set(periph_clk_to_bit(gate), gate);
>> + else
>> + write_rst_clr(periph_clk_to_bit(gate), gate);
>> + }
>> +}
>> +
>> const struct clk_ops tegra_clk_periph_gate_ops = {
>> .is_enabled = clk_periph_is_enabled,
>> .enable = clk_periph_enable,
>> .disable = clk_periph_disable,
>> + .save_context = clk_periph_gate_save_context,
>> + .restore_context = clk_periph_gate_restore_context,
>> };
>>
>> struct clk *tegra_clk_register_periph_gate(const char *name,
>> diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
>> index 58437da25156..06fb62955768 100644
>> --- a/drivers/clk/tegra/clk-periph.c
>> +++ b/drivers/clk/tegra/clk-periph.c
>> @@ -99,6 +99,37 @@ static void clk_periph_disable(struct clk_hw *hw)
>> gate_ops->disable(gate_hw);
>> }
>>
>> +static int clk_periph_save_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_periph *periph = to_clk_periph(hw);
>> + const struct clk_ops *gate_ops = periph->gate_ops;
>> + struct clk_hw *gate_hw = &periph->gate.hw;
>> +
>> + if (!(periph->gate.flags & TEGRA_PERIPH_NO_GATE))
>> + gate_ops->save_context(gate_hw);
>> +
>> + periph->parent_ctx = clk_periph_get_parent(hw);
>> +
>> + return 0;
>> +}
>> +
>> +static void clk_periph_restore_context(struct clk_hw *hw)
>> +{
>> + struct tegra_clk_periph *periph = to_clk_periph(hw);
>> + const struct clk_ops *gate_ops = periph->gate_ops;
>> + struct clk_hw *gate_hw = &periph->gate.hw;
>> + const struct clk_ops *div_ops = periph->div_ops;
>> + struct clk_hw *div_hw = &periph->divider.hw;
>> +
>> + clk_periph_set_parent(hw, periph->parent_ctx);
>> +
>> + if (!(periph->gate.flags & TEGRA_PERIPH_NO_DIV))
>> + div_ops->restore_context(div_hw);
>
> Could you please point to where the divider's save_context() happens?
> Because I can't see it.
Ah, I now see that there is no need to save the dividers context because
clk itself has enough info that is needed for the context's restoring
(like I pointed in the review to v6).
Looks like you could also implement a new clk_hw_get_parent_index()
generic helper to get the index instead of storing it manually.
^ permalink raw reply
* Re: [PATCH v7 03/20] clk: tegra: divider: Save and restore divider rate
From: Dmitry Osipenko @ 2019-07-31 10:49 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1564532424-10449-4-git-send-email-skomatineni@nvidia.com>
31.07.2019 3:20, Sowjanya Komatineni пишет:
> This patch implements context restore for clock divider.
>
> During system suspend, core power goes off and looses the settings
> of the Tegra CAR controller registers.
>
> So on resume, clock dividers are restored back for normal operation.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-divider.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
> index e76731fb7d69..ca0de5f11f84 100644
> --- a/drivers/clk/tegra/clk-divider.c
> +++ b/drivers/clk/tegra/clk-divider.c
> @@ -109,10 +109,21 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
> return 0;
> }
>
> +static void clk_divider_restore_context(struct clk_hw *hw)
> +{
> + struct clk_hw *parent = clk_hw_get_parent(hw);
> + unsigned long parent_rate = clk_hw_get_rate(parent);
> + unsigned long rate = clk_hw_get_rate(hw);
> +
> + if (clk_frac_div_set_rate(hw, rate, parent_rate) < 0)
> + WARN_ON(1);
> +}
> +
> const struct clk_ops tegra_clk_frac_div_ops = {
> .recalc_rate = clk_frac_div_recalc_rate,
> .set_rate = clk_frac_div_set_rate,
> .round_rate = clk_frac_div_round_rate,
> + .restore_context = clk_divider_restore_context,
> };
>
> struct clk *tegra_clk_register_divider(const char *name,
>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
^ permalink raw reply
* Re: [PATCH v7 16/20] arm64: tegra: Enable wake from deep sleep on RTC alarm
From: Dmitry Osipenko @ 2019-07-31 11:04 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1564532424-10449-17-git-send-email-skomatineni@nvidia.com>
31.07.2019 3:20, Sowjanya Komatineni пишет:
> This patch updates device tree for RTC and PMC to allow system wake
> from deep sleep on RTC alarm.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> index 659753118e96..30a7c48385a2 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> @@ -768,7 +768,8 @@
> rtc@7000e000 {
> compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
> reg = <0x0 0x7000e000 0x0 0x100>;
> - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pmc>;
> clocks = <&tegra_car TEGRA210_CLK_RTC>;
> clock-names = "rtc";
> };
> @@ -778,6 +779,8 @@
> reg = <0x0 0x7000e400 0x0 0x400>;
> clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
> clock-names = "pclk", "clk32k_in";
> + #interrupt-cells = <2>;
> + interrupt-controller;
>
> powergates {
> pd_audio: aud {
>
Is this a backwards-compatible change? Or it's not really worth to care
about the compatibility with older kernel versions, I'm not sure about
overall state of T210 in the upstream kernel.
^ permalink raw reply
* Re: [PATCH v7 06/20] clk: tegra: Support for OSC context save and restore
From: Dmitry Osipenko @ 2019-07-31 11:11 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1564532424-10449-7-git-send-email-skomatineni@nvidia.com>
31.07.2019 3:20, Sowjanya Komatineni пишет:
> This patch adds support for saving OSC clock frequency and the
> drive-strength during OSC clock init and creates an API to restore
> OSC control register value from the saved context.
>
> This API is invoked by Tegra210 clock driver during system resume
> to restore the OSC clock settings.
>
> Acked-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra-fixed.c | 15 +++++++++++++++
> drivers/clk/tegra/clk.h | 1 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
> index 8d91b2b191cf..7c6c8abfcde6 100644
> --- a/drivers/clk/tegra/clk-tegra-fixed.c
> +++ b/drivers/clk/tegra/clk-tegra-fixed.c
> @@ -17,6 +17,10 @@
> #define OSC_CTRL 0x50
> #define OSC_CTRL_OSC_FREQ_SHIFT 28
> #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
> +#define OSC_CTRL_MASK (0x3f2 | \
> + (0xf << OSC_CTRL_OSC_FREQ_SHIFT))
> +
> +static u32 osc_ctrl_ctx;
>
> int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
> unsigned long *input_freqs, unsigned int num,
> @@ -29,6 +33,7 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
> unsigned osc_idx;
>
> val = readl_relaxed(clk_base + OSC_CTRL);
> + osc_ctrl_ctx = val & OSC_CTRL_MASK;
> osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
>
> if (osc_idx < num)
> @@ -96,3 +101,13 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
> *dt_clk = clk;
> }
> }
> +
> +void tegra_clk_osc_resume(void __iomem *clk_base)
> +{
> + u32 val;
> +
> + val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
> + val |= osc_ctrl_ctx;
> + writel_relaxed(val, clk_base + OSC_CTRL);
Why a full raw u32 OSC_CTRL value couldn't be simply saved and restored?
> + fence_udelay(2, clk_base);
> +}
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index f1ef6ae8c979..abba6d8a04cd 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -842,6 +842,7 @@ u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
> int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
> int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
> u8 frac_width, u8 flags);
> +void tegra_clk_osc_resume(void __iomem *clk_base);
>
>
> /* Combined read fence with delay */
>
^ permalink raw reply
* Re: [PATCH v7 11/20] cpufreq: tegra124: Add suspend and resume support
From: Dmitry Osipenko @ 2019-07-31 11:14 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <98aae4b7-d95a-90ba-0d55-7512b3712f54@gmail.com>
31.07.2019 13:23, Dmitry Osipenko пишет:
> 31.07.2019 3:20, Sowjanya Komatineni пишет:
>> This patch adds suspend and resume pm ops for cpufreq driver.
>>
>> PLLP is the safe clock source for CPU during system suspend and
>> resume as PLLP rate is below the CPU Fmax at Vmin.
>>
>> CPUFreq driver suspend switches the CPU clock source to PLLP and
>> disables the DFLL clock.
>>
>> During system resume, warmboot code powers up the CPU with PLLP
>> clock source. So CPUFreq driver resume enabled DFLL clock and
>> switches CPU back to DFLL clock source.
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> drivers/cpufreq/tegra124-cpufreq.c | 60 ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 60 insertions(+)
>>
>> diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c
>> index 4f0c637b3b49..e979a3370988 100644
>> --- a/drivers/cpufreq/tegra124-cpufreq.c
>> +++ b/drivers/cpufreq/tegra124-cpufreq.c
>> @@ -6,6 +6,7 @@
>> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>>
>> #include <linux/clk.h>
>> +#include <linux/cpufreq.h>
>> #include <linux/err.h>
>> #include <linux/init.h>
>> #include <linux/kernel.h>
>> @@ -128,8 +129,67 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
>> return ret;
>> }
>>
>> +static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev)
>> +{
>> + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
>> + int err;
>> +
>> + /*
>> + * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to
>> + * use during suspend and resume. So, switch the CPU clock source
>> + * to PLLP and disable DFLL.
>> + */
>> + err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);
>> + if (err < 0) {
>> + dev_err(dev, "failed to reparent to PLLP: %d\n", err);
>> + return err;
>> + }
>> +
>> + /* disable DFLL clock */
>> + clk_disable_unprepare(priv->dfll_clk);
>> +
>> + return 0;
>> +}
>> +
>> +static int __maybe_unused tegra124_cpufreq_resume(struct device *dev)
>> +{
>> + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
>> + int err;
>> +
>> + /*
>> + * Warmboot code powers up the CPU with PLLP clock source.
>> + * Enable DFLL clock and switch CPU clock source back to DFLL.
>> + */
>> + err = clk_prepare_enable(priv->dfll_clk);
>> + if (err < 0) {
>> + dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err);
>> + goto disable_cpufreq;
>> + }
>> +
>> + err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);
>> + if (err < 0) {
>> + dev_err(dev, "failed to reparent to DFLL clock: %d\n", err);
>> + goto disable_dfll;
>> + }
>> +
>> + return 0;
>> +
>> +disable_dfll:
>> + clk_disable_unprepare(priv->dfll_clk);
>> +disable_cpufreq:
>> + disable_cpufreq();
>> +
>> + return err;
>> +}
>> +
>> +static const struct dev_pm_ops tegra124_cpufreq_pm_ops = {
>> + SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
>> + tegra124_cpufreq_resume)
>> +};
>> +
>> static struct platform_driver tegra124_cpufreq_platdrv = {
>> .driver.name = "cpufreq-tegra124",
>> + .driver.pm = &tegra124_cpufreq_pm_ops,
>> .probe = tegra124_cpufreq_probe,
>> };
>>
>>
>
> Looks good,
>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
>
BTW, you should also CC the CPUFreq maintainers because this patch can't
be applied without theirs ACK.
^ permalink raw reply
* Re: [PATCH] gpio: remove duplicated function definition
From: Yuehaibing @ 2019-07-31 12:09 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, yamada.masahiro; +Cc: linux-kernel, linux-gpio
In-Reply-To: <20190731100028.48884-1-yuehaibing@huawei.com>
Pls drop this
On 2019/7/31 18:00, YueHaibing wrote:
> when building without CONFIG_PINCTRL:
>
> In file included from drivers/hwmon/pmbus/ucd9000.c:19:0:
> ./include/linux/gpio/driver.h:576:1: error: redefinition of gpiochip_add_pin_range
> gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
> ^~~~~~~~~~~~~~~~~~~~~~
> In file included from drivers/hwmon/pmbus/ucd9000.c:18:0:
> ./include/linux/gpio.h:245:1: note: previous definition of gpiochip_add_pin_range was here
> gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
> ^~~~~~~~~~~~~~~~~~~~~~
>
> Reported-by: Hulk Robot <hulkci@huawei.com>
> Fixes: 964cb341882f ("gpio: move pincontrol calls to <linux/gpio/driver.h>")
> Signed-off-by: YueHaibing <yuehaibing@huawei.com>
> ---
> include/linux/gpio/driver.h | 35 +----------------------------------
> 1 file changed, 1 insertion(+), 34 deletions(-)
>
> diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
> index f28f534..09f96ec 100644
> --- a/include/linux/gpio/driver.h
> +++ b/include/linux/gpio/driver.h
> @@ -10,6 +10,7 @@
> #include <linux/lockdep.h>
> #include <linux/pinctrl/pinctrl.h>
> #include <linux/pinctrl/pinconf-generic.h>
> +#include <linux/gpio.h>
>
> struct gpio_desc;
> struct of_phandle_args;
> @@ -560,40 +561,6 @@ struct gpio_pin_range {
> struct pinctrl_gpio_range range;
> };
>
> -#ifdef CONFIG_PINCTRL
> -
> -int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
> - unsigned int gpio_offset, unsigned int pin_offset,
> - unsigned int npins);
> -int gpiochip_add_pingroup_range(struct gpio_chip *chip,
> - struct pinctrl_dev *pctldev,
> - unsigned int gpio_offset, const char *pin_group);
> -void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
> -
> -#else /* ! CONFIG_PINCTRL */
> -
> -static inline int
> -gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
> - unsigned int gpio_offset, unsigned int pin_offset,
> - unsigned int npins)
> -{
> - return 0;
> -}
> -static inline int
> -gpiochip_add_pingroup_range(struct gpio_chip *chip,
> - struct pinctrl_dev *pctldev,
> - unsigned int gpio_offset, const char *pin_group)
> -{
> - return 0;
> -}
> -
> -static inline void
> -gpiochip_remove_pin_ranges(struct gpio_chip *chip)
> -{
> -}
> -
> -#endif /* CONFIG_PINCTRL */
> -
> struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
> const char *label,
> enum gpio_lookup_flags lflags,
>
^ permalink raw reply
* [PATCH] gpio: Fix build error of function redefinition
From: YueHaibing @ 2019-07-31 12:38 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, yamada.masahiro
Cc: linux-kernel, linux-gpio, YueHaibing
when do randbuilding, I got this error:
In file included from drivers/hwmon/pmbus/ucd9000.c:19:0:
./include/linux/gpio/driver.h:576:1: error: redefinition of gpiochip_add_pin_range
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
^~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/hwmon/pmbus/ucd9000.c:18:0:
./include/linux/gpio.h:245:1: note: previous definition of gpiochip_add_pin_range was here
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
^~~~~~~~~~~~~~~~~~~~~~
Reported-by: Hulk Robot <hulkci@huawei.com>
Fixes: 964cb341882f ("gpio: move pincontrol calls to <linux/gpio/driver.h>")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
---
include/linux/gpio.h | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/include/linux/gpio.h b/include/linux/gpio.h
index 40915b4..f757a58 100644
--- a/include/linux/gpio.h
+++ b/include/linux/gpio.h
@@ -241,30 +241,6 @@ static inline int irq_to_gpio(unsigned irq)
return -EINVAL;
}
-static inline int
-gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
- unsigned int gpio_offset, unsigned int pin_offset,
- unsigned int npins)
-{
- WARN_ON(1);
- return -EINVAL;
-}
-
-static inline int
-gpiochip_add_pingroup_range(struct gpio_chip *chip,
- struct pinctrl_dev *pctldev,
- unsigned int gpio_offset, const char *pin_group)
-{
- WARN_ON(1);
- return -EINVAL;
-}
-
-static inline void
-gpiochip_remove_pin_ranges(struct gpio_chip *chip)
-{
- WARN_ON(1);
-}
-
static inline int devm_gpio_request(struct device *dev, unsigned gpio,
const char *label)
{
--
2.7.4
^ permalink raw reply related
* [PATCH] pinctrl: sh-pfc: Use dev_notice_once() instead of open-coding
From: Geert Uytterhoeven @ 2019-07-31 13:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-renesas-soc, linux-gpio, Geert Uytterhoeven
At the time of commit 9a643c9a11259955 ("sh-pfc: Convert message
printing from pr_* to dev_*"), the dev_*_once() variants didn't exist
yet, so the once behavior was open-coded.
Since commit e135303bd5bebcd2 ("device: Add dev_<level>_once variants")
they do, so "revert" to the good practice of using a helper.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in sh-pfc-for-v5.4.
drivers/pinctrl/sh-pfc/gpio.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 97c1332c1045739a..64c09aa374ae011f 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -255,18 +255,13 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
{
- static bool __print_once;
struct sh_pfc *pfc = gpio_to_pfc(gc);
unsigned int mark = pfc->info->func_gpios[offset].enum_id;
unsigned long flags;
int ret;
- if (!__print_once) {
- dev_notice(pfc->dev,
- "Use of GPIO API for function requests is deprecated."
- " Convert to pinctrl\n");
- __print_once = true;
- }
+ dev_notice_once(pfc->dev,
+ "Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
if (mark == 0)
return -EINVAL;
--
2.17.1
^ permalink raw reply related
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