* [linusw-pinctrl:devel] BUILD SUCCESS 8b2c4f88c6ee86efdbc81bed1684e13e2efebd53
From: kernel test robot @ 2026-06-16 3:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
branch HEAD: 8b2c4f88c6ee86efdbc81bed1684e13e2efebd53 pinctrl: Export pinctrl_get_group_selector()
elapsed time: 836m
configs tested: 197
configs skipped: 3
The following configs have been built successfully.
More configs may be tested in the coming days.
tested configs:
alpha allnoconfig gcc-16.1.0
alpha allyesconfig gcc-16.1.0
alpha defconfig gcc-16.1.0
arc allmodconfig clang-23
arc allmodconfig gcc-16.1.0
arc allnoconfig gcc-16.1.0
arc allyesconfig clang-23
arc allyesconfig gcc-16.1.0
arc defconfig gcc-16.1.0
arc nsimosci_hs_smp_defconfig gcc-16.1.0
arc randconfig-001-20260616 gcc-9.5.0
arc randconfig-002-20260616 gcc-9.5.0
arm allnoconfig gcc-16.1.0
arm allyesconfig clang-23
arm allyesconfig gcc-16.1.0
arm defconfig gcc-16.1.0
arm imx_v4_v5_defconfig clang-23
arm randconfig-001-20260616 gcc-9.5.0
arm randconfig-002-20260616 gcc-9.5.0
arm randconfig-003-20260616 gcc-9.5.0
arm randconfig-004-20260616 gcc-9.5.0
arm64 allmodconfig clang-23
arm64 allnoconfig gcc-16.1.0
arm64 defconfig gcc-16.1.0
arm64 randconfig-001-20260616 gcc-13.4.0
arm64 randconfig-002-20260616 gcc-13.4.0
arm64 randconfig-003-20260616 gcc-13.4.0
arm64 randconfig-004-20260616 gcc-13.4.0
csky allmodconfig gcc-16.1.0
csky allnoconfig gcc-16.1.0
csky defconfig gcc-16.1.0
csky randconfig-001-20260616 gcc-13.4.0
csky randconfig-002-20260616 gcc-13.4.0
hexagon allmodconfig clang-23
hexagon allmodconfig gcc-16.1.0
hexagon allnoconfig gcc-16.1.0
hexagon defconfig gcc-16.1.0
hexagon randconfig-001-20260616 clang-23
hexagon randconfig-002-20260616 clang-23
i386 allmodconfig clang-22
i386 allnoconfig gcc-16.1.0
i386 allyesconfig clang-22
i386 allyesconfig gcc-14
i386 buildonly-randconfig-001-20260616 clang-22
i386 buildonly-randconfig-002-20260616 clang-22
i386 buildonly-randconfig-003-20260616 clang-22
i386 buildonly-randconfig-004-20260616 clang-22
i386 buildonly-randconfig-005-20260616 clang-22
i386 buildonly-randconfig-006-20260616 clang-22
i386 defconfig gcc-16.1.0
i386 randconfig-001-20260616 gcc-14
i386 randconfig-002-20260616 gcc-14
i386 randconfig-003-20260616 gcc-14
i386 randconfig-004-20260616 gcc-14
i386 randconfig-005-20260616 gcc-14
i386 randconfig-006-20260616 gcc-14
i386 randconfig-007-20260616 gcc-14
i386 randconfig-011-20260616 clang-22
i386 randconfig-012-20260616 clang-22
i386 randconfig-013-20260616 clang-22
i386 randconfig-014-20260616 clang-22
i386 randconfig-015-20260616 clang-22
i386 randconfig-016-20260616 clang-22
i386 randconfig-017-20260616 clang-22
loongarch allmodconfig clang-19
loongarch allmodconfig clang-23
loongarch allnoconfig gcc-16.1.0
loongarch defconfig clang-23
loongarch randconfig-001-20260616 clang-23
loongarch randconfig-002-20260616 clang-23
m68k allmodconfig gcc-16.1.0
m68k allnoconfig gcc-16.1.0
m68k allyesconfig clang-23
m68k allyesconfig gcc-16.1.0
m68k defconfig clang-23
microblaze allnoconfig gcc-16.1.0
microblaze allyesconfig gcc-16.1.0
microblaze defconfig clang-23
mips allmodconfig gcc-16.1.0
mips allnoconfig gcc-16.1.0
mips allyesconfig gcc-16.1.0
nios2 allmodconfig clang-20
nios2 allmodconfig gcc-11.5.0
nios2 allnoconfig clang-23
nios2 defconfig clang-23
nios2 randconfig-001-20260616 clang-23
nios2 randconfig-002-20260616 clang-23
openrisc allmodconfig clang-20
openrisc allmodconfig gcc-16.1.0
openrisc allnoconfig clang-23
openrisc defconfig gcc-16.1.0
parisc allmodconfig gcc-16.1.0
parisc allnoconfig clang-23
parisc allyesconfig clang-17
parisc allyesconfig gcc-16.1.0
parisc defconfig gcc-16.1.0
parisc randconfig-001-20260616 gcc-8.5.0
parisc randconfig-002-20260616 gcc-8.5.0
parisc64 defconfig clang-23
powerpc allmodconfig gcc-16.1.0
powerpc allnoconfig clang-23
powerpc ep88xc_defconfig gcc-16.1.0
powerpc pmac32_defconfig clang-23
powerpc randconfig-001-20260616 gcc-8.5.0
powerpc randconfig-002-20260616 gcc-8.5.0
powerpc64 randconfig-001-20260616 gcc-8.5.0
powerpc64 randconfig-002-20260616 gcc-8.5.0
riscv allmodconfig clang-23
riscv allnoconfig clang-23
riscv allyesconfig clang-23
riscv defconfig gcc-16.1.0
riscv randconfig-001 gcc-13.4.0
riscv randconfig-001-20260615 clang-19
riscv randconfig-001-20260616 gcc-16.1.0
riscv randconfig-002 clang-23
riscv randconfig-002-20260615 gcc-16.1.0
riscv randconfig-002-20260616 gcc-16.1.0
s390 allmodconfig clang-17
s390 allmodconfig clang-23
s390 allnoconfig clang-23
s390 allyesconfig gcc-16.1.0
s390 defconfig gcc-16.1.0
s390 randconfig-001 gcc-15.2.0
s390 randconfig-001-20260615 gcc-11.5.0
s390 randconfig-001-20260616 gcc-16.1.0
s390 randconfig-002 clang-18
s390 randconfig-002-20260615 clang-23
s390 randconfig-002-20260616 gcc-16.1.0
sh allmodconfig gcc-16.1.0
sh allnoconfig clang-23
sh allyesconfig clang-17
sh allyesconfig gcc-16.1.0
sh defconfig gcc-14
sh randconfig-001 gcc-14.3.0
sh randconfig-001-20260615 gcc-16.1.0
sh randconfig-001-20260616 gcc-16.1.0
sh randconfig-002 gcc-9.5.0
sh randconfig-002-20260615 gcc-10.5.0
sh randconfig-002-20260616 gcc-16.1.0
sparc allnoconfig clang-23
sparc defconfig gcc-16.1.0
sparc randconfig-001-20260616 gcc-8.5.0
sparc randconfig-002-20260616 gcc-8.5.0
sparc64 allmodconfig clang-20
sparc64 defconfig gcc-14
sparc64 randconfig-001-20260616 gcc-8.5.0
sparc64 randconfig-002-20260616 gcc-8.5.0
um allmodconfig clang-17
um allmodconfig clang-23
um allnoconfig clang-23
um allyesconfig gcc-14
um allyesconfig gcc-16.1.0
um defconfig gcc-14
um i386_defconfig gcc-14
um randconfig-001-20260616 gcc-8.5.0
um randconfig-002-20260616 gcc-8.5.0
um x86_64_defconfig gcc-14
x86_64 allmodconfig clang-22
x86_64 allnoconfig clang-23
x86_64 allyesconfig clang-22
x86_64 buildonly-randconfig-001-20260616 gcc-14
x86_64 buildonly-randconfig-002-20260616 gcc-14
x86_64 buildonly-randconfig-003-20260616 gcc-14
x86_64 buildonly-randconfig-004-20260616 gcc-14
x86_64 buildonly-randconfig-005-20260616 gcc-14
x86_64 buildonly-randconfig-006-20260616 gcc-14
x86_64 defconfig gcc-14
x86_64 kexec clang-22
x86_64 randconfig-001-20260616 clang-22
x86_64 randconfig-002-20260616 clang-22
x86_64 randconfig-003-20260616 clang-22
x86_64 randconfig-004-20260616 clang-22
x86_64 randconfig-005-20260616 clang-22
x86_64 randconfig-006-20260616 clang-22
x86_64 randconfig-011-20260616 clang-22
x86_64 randconfig-012-20260616 clang-22
x86_64 randconfig-013-20260616 clang-22
x86_64 randconfig-014-20260616 clang-22
x86_64 randconfig-015-20260616 clang-22
x86_64 randconfig-016-20260616 clang-22
x86_64 randconfig-071-20260616 gcc-14
x86_64 randconfig-072-20260616 gcc-14
x86_64 randconfig-073-20260616 gcc-14
x86_64 randconfig-074-20260616 gcc-14
x86_64 randconfig-075-20260616 gcc-14
x86_64 randconfig-076-20260616 gcc-14
x86_64 rhel-9.4 clang-22
x86_64 rhel-9.4-bpf gcc-14
x86_64 rhel-9.4-func clang-22
x86_64 rhel-9.4-kselftests clang-22
x86_64 rhel-9.4-kunit gcc-14
x86_64 rhel-9.4-ltp gcc-14
x86_64 rhel-9.4-rust clang-22
xtensa allnoconfig clang-23
xtensa allyesconfig clang-20
xtensa randconfig-001-20260616 gcc-8.5.0
xtensa randconfig-002-20260616 gcc-8.5.0
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* [linusw-pinctrl:for-next] BUILD SUCCESS 3bd25818aebd8dc6cdc44cb9356a539e98a76c6c
From: kernel test robot @ 2026-06-16 3:20 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
branch HEAD: 3bd25818aebd8dc6cdc44cb9356a539e98a76c6c Merge branch 'devel' into for-next
elapsed time: 832m
configs tested: 206
configs skipped: 3
The following configs have been built successfully.
More configs may be tested in the coming days.
tested configs:
alpha allnoconfig gcc-16.1.0
alpha allyesconfig gcc-16.1.0
alpha defconfig gcc-16.1.0
arc allmodconfig clang-23
arc allmodconfig gcc-16.1.0
arc allnoconfig gcc-16.1.0
arc allyesconfig clang-23
arc allyesconfig gcc-16.1.0
arc defconfig gcc-16.1.0
arc nsimosci_hs_smp_defconfig gcc-16.1.0
arc randconfig-001-20260616 gcc-9.5.0
arc randconfig-002-20260616 gcc-9.5.0
arm allnoconfig gcc-16.1.0
arm allyesconfig clang-23
arm allyesconfig gcc-16.1.0
arm defconfig gcc-16.1.0
arm imx_v4_v5_defconfig clang-23
arm randconfig-001-20260616 gcc-9.5.0
arm randconfig-002-20260616 gcc-9.5.0
arm randconfig-003-20260616 gcc-9.5.0
arm randconfig-004-20260616 gcc-9.5.0
arm64 allmodconfig clang-23
arm64 allnoconfig gcc-16.1.0
arm64 defconfig gcc-16.1.0
arm64 randconfig-001-20260616 gcc-13.4.0
arm64 randconfig-001-20260616 gcc-8.5.0
arm64 randconfig-002-20260616 gcc-13.4.0
arm64 randconfig-002-20260616 gcc-15.2.0
arm64 randconfig-003-20260616 gcc-13.4.0
arm64 randconfig-004-20260616 gcc-11.5.0
arm64 randconfig-004-20260616 gcc-13.4.0
csky allmodconfig gcc-16.1.0
csky allnoconfig gcc-16.1.0
csky defconfig gcc-16.1.0
csky randconfig-001-20260616 gcc-13.4.0
csky randconfig-001-20260616 gcc-15.2.0
csky randconfig-002-20260616 gcc-13.4.0
hexagon allmodconfig clang-23
hexagon allmodconfig gcc-16.1.0
hexagon allnoconfig gcc-16.1.0
hexagon defconfig gcc-16.1.0
hexagon randconfig-001-20260616 clang-23
hexagon randconfig-002-20260616 clang-23
i386 allmodconfig clang-22
i386 allmodconfig gcc-14
i386 allnoconfig gcc-16.1.0
i386 allyesconfig clang-22
i386 allyesconfig gcc-14
i386 buildonly-randconfig-001-20260616 clang-22
i386 buildonly-randconfig-002-20260616 clang-22
i386 buildonly-randconfig-003-20260616 clang-22
i386 buildonly-randconfig-004-20260616 clang-22
i386 buildonly-randconfig-005-20260616 clang-22
i386 buildonly-randconfig-006-20260616 clang-22
i386 defconfig gcc-16.1.0
i386 randconfig-001-20260616 gcc-14
i386 randconfig-002-20260616 gcc-14
i386 randconfig-003-20260616 gcc-14
i386 randconfig-004-20260616 gcc-14
i386 randconfig-005-20260616 gcc-14
i386 randconfig-006-20260616 gcc-14
i386 randconfig-007-20260616 gcc-14
i386 randconfig-011-20260616 clang-22
i386 randconfig-012-20260616 clang-22
i386 randconfig-013-20260616 clang-22
i386 randconfig-014-20260616 clang-22
i386 randconfig-015-20260616 clang-22
i386 randconfig-016-20260616 clang-22
i386 randconfig-017-20260616 clang-22
loongarch allmodconfig clang-19
loongarch allmodconfig clang-23
loongarch allnoconfig gcc-16.1.0
loongarch defconfig clang-23
loongarch randconfig-001-20260616 clang-23
loongarch randconfig-002-20260616 clang-23
m68k allmodconfig gcc-16.1.0
m68k allnoconfig gcc-16.1.0
m68k allyesconfig clang-23
m68k allyesconfig gcc-16.1.0
m68k defconfig clang-23
microblaze allnoconfig gcc-16.1.0
microblaze allyesconfig gcc-16.1.0
microblaze defconfig clang-23
mips allmodconfig gcc-16.1.0
mips allnoconfig gcc-16.1.0
mips allyesconfig gcc-16.1.0
nios2 allmodconfig clang-20
nios2 allmodconfig gcc-11.5.0
nios2 allnoconfig clang-23
nios2 allnoconfig gcc-11.5.0
nios2 defconfig clang-23
nios2 randconfig-001-20260616 clang-23
nios2 randconfig-002-20260616 clang-23
openrisc allmodconfig clang-20
openrisc allmodconfig gcc-16.1.0
openrisc allnoconfig clang-23
openrisc allnoconfig gcc-16.1.0
openrisc defconfig gcc-16.1.0
parisc allmodconfig gcc-16.1.0
parisc allnoconfig clang-23
parisc allnoconfig gcc-16.1.0
parisc allyesconfig clang-17
parisc allyesconfig gcc-16.1.0
parisc defconfig gcc-16.1.0
parisc randconfig-001-20260616 gcc-8.5.0
parisc randconfig-002-20260616 gcc-8.5.0
parisc64 defconfig clang-23
powerpc allmodconfig gcc-16.1.0
powerpc allnoconfig clang-23
powerpc allnoconfig gcc-16.1.0
powerpc ep88xc_defconfig gcc-16.1.0
powerpc pmac32_defconfig clang-23
powerpc randconfig-001-20260616 gcc-8.5.0
powerpc randconfig-002-20260616 gcc-8.5.0
powerpc64 randconfig-001-20260616 gcc-8.5.0
powerpc64 randconfig-002-20260616 gcc-8.5.0
riscv allmodconfig clang-23
riscv allnoconfig clang-23
riscv allnoconfig gcc-16.1.0
riscv allyesconfig clang-23
riscv defconfig gcc-16.1.0
riscv randconfig-001-20260615 clang-19
riscv randconfig-001-20260616 gcc-16.1.0
riscv randconfig-002-20260615 gcc-16.1.0
riscv randconfig-002-20260616 gcc-16.1.0
s390 allmodconfig clang-17
s390 allmodconfig clang-23
s390 allnoconfig clang-23
s390 allyesconfig gcc-16.1.0
s390 defconfig gcc-16.1.0
s390 randconfig-001-20260615 gcc-11.5.0
s390 randconfig-001-20260616 gcc-16.1.0
s390 randconfig-002-20260615 clang-23
s390 randconfig-002-20260616 gcc-16.1.0
sh allmodconfig gcc-16.1.0
sh allnoconfig clang-23
sh allnoconfig gcc-16.1.0
sh allyesconfig clang-17
sh allyesconfig gcc-16.1.0
sh defconfig gcc-14
sh randconfig-001-20260615 gcc-16.1.0
sh randconfig-001-20260616 gcc-16.1.0
sh randconfig-002-20260615 gcc-10.5.0
sh randconfig-002-20260616 gcc-16.1.0
sparc allnoconfig clang-23
sparc allnoconfig gcc-16.1.0
sparc defconfig gcc-16.1.0
sparc randconfig-001-20260616 gcc-8.5.0
sparc randconfig-002-20260616 gcc-8.5.0
sparc64 allmodconfig clang-20
sparc64 defconfig gcc-14
sparc64 randconfig-001-20260616 gcc-8.5.0
sparc64 randconfig-002-20260616 gcc-8.5.0
um allmodconfig clang-17
um allmodconfig clang-23
um allnoconfig clang-16
um allnoconfig clang-23
um allyesconfig gcc-14
um allyesconfig gcc-16.1.0
um defconfig gcc-14
um i386_defconfig gcc-14
um randconfig-001-20260616 gcc-8.5.0
um randconfig-002-20260616 gcc-8.5.0
um x86_64_defconfig gcc-14
x86_64 allmodconfig clang-22
x86_64 allnoconfig clang-22
x86_64 allnoconfig clang-23
x86_64 allyesconfig clang-22
x86_64 buildonly-randconfig-001-20260616 gcc-14
x86_64 buildonly-randconfig-002-20260616 gcc-14
x86_64 buildonly-randconfig-003-20260616 gcc-14
x86_64 buildonly-randconfig-004-20260616 gcc-14
x86_64 buildonly-randconfig-005-20260616 gcc-14
x86_64 buildonly-randconfig-006-20260616 gcc-14
x86_64 defconfig gcc-14
x86_64 kexec clang-22
x86_64 randconfig-001-20260616 clang-22
x86_64 randconfig-002-20260616 clang-22
x86_64 randconfig-003-20260616 clang-22
x86_64 randconfig-004-20260616 clang-22
x86_64 randconfig-005-20260616 clang-22
x86_64 randconfig-006-20260616 clang-22
x86_64 randconfig-011-20260616 clang-22
x86_64 randconfig-012-20260616 clang-22
x86_64 randconfig-013-20260616 clang-22
x86_64 randconfig-014-20260616 clang-22
x86_64 randconfig-015-20260616 clang-22
x86_64 randconfig-016-20260616 clang-22
x86_64 randconfig-071-20260616 gcc-14
x86_64 randconfig-072-20260616 gcc-14
x86_64 randconfig-073-20260616 gcc-14
x86_64 randconfig-074-20260616 gcc-14
x86_64 randconfig-075-20260616 gcc-14
x86_64 randconfig-076-20260616 gcc-14
x86_64 rhel-9.4 clang-22
x86_64 rhel-9.4-bpf gcc-14
x86_64 rhel-9.4-func clang-22
x86_64 rhel-9.4-kselftests clang-22
x86_64 rhel-9.4-kunit gcc-14
x86_64 rhel-9.4-ltp gcc-14
x86_64 rhel-9.4-rust clang-22
xtensa allnoconfig clang-23
xtensa allnoconfig gcc-16.1.0
xtensa allyesconfig clang-20
xtensa randconfig-001-20260616 gcc-8.5.0
xtensa randconfig-002-20260616 gcc-8.5.0
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH RFC 1/2] dt-bindings: pinctl: amlogic,pinctrl-a4: Add gpio irq property
From: Xianwei Zhao @ 2026-06-16 2:56 UTC (permalink / raw)
To: Conor Dooley
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
linux-amlogic, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260615-ultra-pagan-84de490070e1@spud>
Hi Conor,
Thanks for your detailed review. I will drop this patch.
On 2026/6/16 00:52, Conor Dooley wrote:
> Subject:
> Re: [PATCH RFC 1/2] dt-bindings: pinctl: amlogic,pinctrl-a4: Add gpio
> irq property
> From:
> Conor Dooley <conor@kernel.org>
> Date:
> 2026/6/16 00:52
>
> To:
> xianwei.zhao@amlogic.com
> CC:
> Linus Walleij <linusw@kernel.org>, Rob Herring <robh@kernel.org>,
> Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley
> <conor+dt@kernel.org>, Neil Armstrong <neil.armstrong@linaro.org>, Kevin
> Hilman <khilman@baylibre.com>, Jerome Brunet <jbrunet@baylibre.com>,
> Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
> linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org,
> devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
> linux-arm-kernel@lists.infradead.org
>
>
> Given Linus' comments on the cover letter,
> pw-bot: changes-requested
>
> Thanks,
> Conor.
^ permalink raw reply
* Re: [PATCH RFC 1/2] dt-bindings: pinctl: amlogic,pinctrl-a4: Add gpio irq property
From: Xianwei Zhao @ 2026-06-16 2:54 UTC (permalink / raw)
To: Krzysztof Kozlowski, Conor Dooley
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
linux-amlogic, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <542ec217-1187-4fb2-8fd3-b90a6143b84d@kernel.org>
Hi Krzysztof,
Thanks for your detailed review. After considering the feedback, I
think this approach is not suitable, so I will drop this patch.
On 2026/6/15 13:32, Krzysztof Kozlowski wrote:
> On 15/06/2026 04:47, Xianwei Zhao wrote:
>> Hi Conor,
>> Thanks for your review.
>>
>> On 2026/6/12 01:39, Conor Dooley wrote:
>>> Subject:
>>> Re: [PATCH RFC 1/2] dt-bindings: pinctl: amlogic,pinctrl-a4: Add gpio
>>> irq property
>>> From:
>>> Conor Dooley<conor@kernel.org>
>>> Date:
>>> 2026/6/12 01:39
>>>
>>> To:
>>> xianwei.zhao@amlogic.com
>>> CC:
>>> Linus Walleij<linusw@kernel.org>, Rob Herring<robh@kernel.org>,
>>> Krzysztof Kozlowski<krzk+dt@kernel.org>, Conor Dooley
>>> <conor+dt@kernel.org>, Neil Armstrong<neil.armstrong@linaro.org>, Kevin
>>> Hilman<khilman@baylibre.com>, Jerome Brunet<jbrunet@baylibre.com>,
>>> Martin Blumenstingl<martin.blumenstingl@googlemail.com>,
>>> linux-amlogic@lists.infradead.org,linux-gpio@vger.kernel.org,
>>> devicetree@vger.kernel.org,linux-kernel@vger.kernel.org,
>>> linux-arm-kernel@lists.infradead.org
>>>
>>>
>>>
>>> On Thu, Jun 11, 2026 at 07:54:33AM +0000, Xianwei Zhao via B4 Relay wrote:
>>>> From: Xianwei Zhao<xianwei.zhao@amlogic.com>
>>>>
>>>> Add the hw-irq property for each GPIO bank and enable interrupt-parent
>>>> for pinctrl so that gpiod_to_irq() can translate GPIO lines to IRQs.
>>> Uhhhhh, what? Why can't you just use the normal interrupts property?
>>>
>> The interrupt cannot be used directly because the GPIO bank only
>> provides an IRQ base, which does not have a one-to-one mapping with the
>> actual hardware interrupts.
>>
>> On Amlogic SoCs, GPIO interrupts are handled through a mux. Multiple
>> GPIO pins are mapped to a limited number of real interrupt sources. The
>> implementation can be found here:
>>
>> https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-meson-gpio.c
>>
>> To use a GPIO interrupt, an unused hardware interrupt must first be
>> allocated, and then the corresponding mux register must be configured.
>> This allocation and mapping are already implemented in the existing driver.
>>
>> In that driver, the mapping is performed dynamically rather than simply
>> calculating:
>>
>> irq = irq_start + gpio_offset
>>
>> If the interrupt is used directly, only the GPIO index can be obtained.
>
> If it is performed dynamically, then it is not suitable for DT.
>
> You still did not explain what hardware aspect exactly is described by
> "hw-irq".
>
>
>
>> The real interrupt number cannot be derived by simply adding an offset,
>> because the hardware interrupt must be allocated first. Pre-allocating
>> all interrupts during initialization would prevent later GPIOs from
>> obtaining available interrupt sources.
>>
>> Perhaps other names would be more appropriate here, such as "irq_start".
>>
>>>> Signed-off-by: Xianwei Zhao<xianwei.zhao@amlogic.com>
>>>> ---
> Best regards,
> Krzysztof
^ permalink raw reply
* Re: [PATCH RFC 0/2] pinctrl: Add support gpiod_to_irq
From: Xianwei Zhao @ 2026-06-16 2:45 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-amlogic,
linux-gpio, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <CAD++jLm9+8RSbBCi-k=8S98XvVJ7taYrK=kuBp3_RqxE_bcxbg@mail.gmail.com>
Hi Linus,
Understood. Thank you for your detailed explanation. I will drop
this patch.
On 2026/6/15 20:59, Linus Walleij wrote:
>>> Hi Xianwei,
>>>
>>> thanks for your patches!
>>>
>>> On Thu, Jun 11, 2026 at 9:54 AM Xianwei Zhao via B4 Relay
>>> <devnull+xianwei.zhao.amlogic.com@kernel.org> wrote:
>>>
>>>> Some users need to obtain an IRQ directly from a GPIO descriptor through gpiod_to_irq().
>>>> Add the required DT binding and implementation to support this use case.
>>>> Since this introduces a new DT property, the property is kept optional to
>>>> maintain compatibility with existing SoCs and DTS files.
>>> To me it looks like you have just re-implemented hierarchical
>>> irqs.
>>>
>>> Look into the section "Infrastructure helpers for GPIO irqchips"
>>> in Documentation/driver-api/gpio/driver.rst, especially towards
>>> the end.
>>>
>>> Solve this by using GPIOLIB_IRQCHIP and a custom
>>> child_to_parent_hwirq() callback to translate the GPIO into
>>> an IRQ.
>>>
>>> To just implement gpiod_to_irq() without any irqchip abstraction
>>> is also broken: you can't force all users to just use this way
>>> to get an IRQ it's excessively restricting.
>>>
>>> Add
>>>
>>> interrupt-controller: true
>>>
>>> "#interrupt-cells":
>>> const: 2
>>>
>>> to the pinctrl node as well so that DT users can simply request
>>> the IRQ from the irqchip inside of the pin controller. It will
>>> be hierarchical and lightweight but an irqchip nevertheless.
>>>
>>> The GPIOLIB_IRQCHIP approach will help you to get this
>>> right.
>>>
>> I read the document (Documentation/driver-api/gpio/driver.rst) you
>> pointed me to and found that the corresponding implementation has
>> already been added in this file:
>>
>> https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-meson-gpio.c
> That is the parent interrupt controller to the pinctrl+gpio isn't it.
>
> It will be even clearer once you use interrupts = <>; instead of
> the hwirq = <>; hack.
>
>> However, it is implemented as a standalone irqchip and is not integrated
>> with the GPIO controller.
> Right, so it is the parent. Of course it it stand alone.
>
>> In this patch, I implemented the GPIO-to-IRQ conversion through
>> gpiod_to_irq(). Users can still obtain the interrupt directly through
>> the interrupt property, for example:
>>
>> interrupts-extended = <&gpio_intc 16 1>;
>>
>> The purpose of this change is to make GPIO-to-IRQ conversion easier for
>> users who do not want to know the actual interrupt number. The interrupt
>> mapping is not fixed and varies between different SoCs, so users should
>> not need to handle the hardware interrupt allocation details.
> This is not why gpiod_to_irq() exists. It is not a convenience function
> that is voluntary to implement.
>
> If you implement gpiod_to_irq() you implement an entire
> irqchip otherwise it is a bug.
>
> If the pin control + GPIO driver should serve IRQ numbers in any
> shape or form, you need to go the whole way and provide a
> hierarchical irqchip.
>
> It doesn't matter if you don't need to set a single bit in the
> pinctrl + GPIO hardware for these IRQs, the fact that they are
> routed internally on the SoC out through the pin control and
> GPIO block by definition makes it hierarchical.
>
> Yours,
> Linus Walleij
^ permalink raw reply
* Re: [GIT PULL] gpio updates for v7.2-rc1
From: pr-tracker-bot @ 2026-06-16 2:11 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Linus Torvalds, Linus Walleij, linux-gpio, linux-kernel, brgl,
Bartosz Golaszewski
In-Reply-To: <20260615082923.38764-1-bartosz.golaszewski@oss.qualcomm.com>
The pull request you sent on Mon, 15 Jun 2026 10:29:22 +0200:
> git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git tags/gpio-updates-for-v7.2-rc1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/77d084d66b7694e2a912abdd8b9e5a0e7a32d28e
Thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/prtracker.html
^ permalink raw reply
* Re: [PATCH v2 2/2] pinctrl: qcom: Add the tlmm driver for Maili platform
From: Dmitry Baryshkov @ 2026-06-16 0:55 UTC (permalink / raw)
To: Jingyi Wang, g
Cc: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
linux-arm-msm, linux-gpio, devicetree, linux-kernel
In-Reply-To: <20260614-maili-pinctrl-v2-2-0db5bfc23d64@oss.qualcomm.com>
On Sun, Jun 14, 2026 at 11:55:04PM -0700, Jingyi Wang wrote:
> Add support for Maili TLMM configuration and control via the pinctrl
> framework.
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> drivers/pinctrl/qcom/Kconfig.msm | 10 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-maili.c | 1630 ++++++++++++++++++++++++++++++++++
> 3 files changed, 1641 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH] gpio: htc-egpio: use managed gpiochip registration
From: Pengpeng Hou @ 2026-06-16 0:39 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, linux-gpio, linux-kernel; +Cc: Pengpeng Hou
egpio_probe() registers each configured gpiochip in a loop but ignores
registration failures. If one registration fails, probe can continue with
only part of the provider registered.
Use devm_gpiochip_add_data() and propagate the error. The managed helper
also removes any earlier chips automatically if probe later fails.
Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn>
---
drivers/gpio/gpio-htc-egpio.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-htc-egpio.c b/drivers/gpio/gpio-htc-egpio.c
index d15423c718d0..1f7d7ac5603f 100644
--- a/drivers/gpio/gpio-htc-egpio.c
+++ b/drivers/gpio/gpio-htc-egpio.c
@@ -268,6 +268,7 @@ static int __init egpio_probe(struct platform_device *pdev)
struct gpio_chip *chip;
unsigned int irq, irq_end;
int i;
+ int ret;
/* Initialize ei data structure. */
ei = devm_kzalloc(&pdev->dev, struct_size(ei, chip, pdata->num_chips), GFP_KERNEL);
@@ -326,7 +327,9 @@ static int __init egpio_probe(struct platform_device *pdev)
chip->base = pdata->chip[i].gpio_base;
chip->ngpio = pdata->chip[i].num_gpios;
- gpiochip_add_data(chip, &ei->chip[i]);
+ ret = devm_gpiochip_add_data(&pdev->dev, chip, &ei->chip[i]);
+ if (ret)
+ return ret;
}
/* Set initial pin values */
--
2.50.1 (Apple Git-155)
^ permalink raw reply related
* Re: [06/11] pinctrl: airoha: an7583: fix incorrect led mapping in phy4_led1 pin function
From: Wayen Yan @ 2026-06-16 0:07 UTC (permalink / raw)
To: Mikhail Kshevetskiy; +Cc: linux-gpio, Lorenzo Bianconi
In-Reply-To: <6477a7b8-f8e9-4db1-a5bf-921b10965c8f@iopsys.eu>
On 6/15/26 19:19, Mikhail Kshevetskiy wrote:
> This is a previous patch in a series, isn't it?
Right, PATCH 05/11 already covers the EN7581 phy4_led1 fix. Sorry for
the noise, I missed that when reviewing the series.
Regards,
Wayen
^ permalink raw reply
* Re: [PATCH v6 1/2] pinctrl: qcom: lpass-lpi: Enable runtime PM hooks on LPASS LPI SoCs
From: Dmitry Baryshkov @ 2026-06-15 23:50 UTC (permalink / raw)
To: Ajay Kumar Nandam
Cc: Bjorn Andersson, Linus Walleij, linux-arm-msm, linux-gpio,
linux-kernel, mohammad.rafi.shaik, Konrad Dybcio
In-Reply-To: <20260522204644.4101640-2-ajay.nandam@oss.qualcomm.com>
On Sat, May 23, 2026 at 02:16:43AM +0530, Ajay Kumar Nandam wrote:
> The LPASS LPI core conversion to PM clock framework relies on variant
> drivers wiring runtime PM callbacks.
>
> Hook up runtime PM callbacks for the LPASS LPI variant drivers touched
> in this patch so they are prepared for the shared core conversion.
>
> This commit is a preparatory NOP on its own, as runtime PM is still
> disabled on these devices until the following core conversion patch.
>
> This is a mechanical per-variant driver update that relies on the
> same generic PM clock flow (of_pm_clk_add_clks() + pm_clk_suspend/
> pm_clk_resume()) and DT-provided clocks.
>
> Runtime behavior was validated on Kodiak (sc7280).
>
> Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
> ---
> .../pinctrl/qcom/pinctrl-milos-lpass-lpi.c | 7 +++++++
> .../pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 19 +++++++++++++------
> .../pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 15 +++++++++++----
> .../pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 7 +++++++
> .../pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c | 7 +++++++
> .../pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 7 +++++++
> .../pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 7 +++++++
> .../pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c | 7 +++++++
> .../pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 15 +++++++++++----
> .../pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 15 +++++++++++----
> .../pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 15 +++++++++++----
> .../pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 15 +++++++++++----
> 12 files changed, 110 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c
> index 3bf6fe0cf1bb..72b8ffd97860 100644
> --- a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c
> @@ -7,6 +7,8 @@
> #include <linux/gpio/driver.h>
> #include <linux/module.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_clock.h>
> +#include <linux/pm_runtime.h>
>
> #include "pinctrl-lpass-lpi.h"
>
> @@ -203,10 +205,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = {
> };
> MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
>
> +static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
> + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
> +};
> +
> static struct platform_driver lpi_pinctrl_driver = {
> .driver = {
> .name = "qcom-milos-lpass-lpi-pinctrl",
> .of_match_table = lpi_pinctrl_of_match,
> + .pm = pm_ptr(&lpi_pinctrl_pm_ops),
> },
> .probe = lpi_pinctrl_probe,
> .remove = lpi_pinctrl_remove,
> diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> index 750f410311a8..a61df10d46cb 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> @@ -7,6 +7,8 @@
> #include <linux/gpio/driver.h>
> #include <linux/module.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_clock.h>
> +#include <linux/pm_runtime.h>
>
> #include "pinctrl-lpass-lpi.h"
>
> @@ -129,20 +131,25 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
>
> static const struct of_device_id lpi_pinctrl_of_match[] = {
> {
> - .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
> - .data = &sc7280_lpi_data,
> + .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
> + .data = &sc7280_lpi_data,
Split whitespace changes to a separate patch. Never mix cleanups (like
the whitespace or formatting) and the sensible changes in a single
patch.
> }, {
> - .compatible = "qcom,sm8350-lpass-lpi-pinctrl",
> - .data = &sc7280_lpi_data,
> + .compatible = "qcom,sm8350-lpass-lpi-pinctrl",
> + .data = &sc7280_lpi_data,
> },
> { }
> };
> MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
>
--
With best wishes
Dmitry
^ permalink raw reply
* [linusw-pinctrl:b4/export-get-group-selector] BUILD SUCCESS cb6af574d673458fa0210f18a9b3bf2ae4694f92
From: kernel test robot @ 2026-06-15 23:38 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git b4/export-get-group-selector
branch HEAD: cb6af574d673458fa0210f18a9b3bf2ae4694f92 pinctrl: Export pinctrl_get_group_selector()
elapsed time: 822m
configs tested: 311
configs skipped: 11
The following configs have been built successfully.
More configs may be tested in the coming days.
tested configs:
alpha allnoconfig gcc-16.1.0
alpha allyesconfig gcc-16.1.0
alpha defconfig gcc-16.1.0
arc allmodconfig clang-23
arc allmodconfig gcc-16.1.0
arc allnoconfig gcc-16.1.0
arc allyesconfig clang-23
arc allyesconfig gcc-16.1.0
arc defconfig gcc-16.1.0
arc randconfig-001 gcc-10.5.0
arc randconfig-001-20260615 gcc-10.5.0
arc randconfig-001-20260616 gcc-9.5.0
arc randconfig-002 gcc-10.5.0
arc randconfig-002-20260615 gcc-10.5.0
arc randconfig-002-20260616 gcc-9.5.0
arm allnoconfig gcc-16.1.0
arm allyesconfig clang-23
arm allyesconfig gcc-16.1.0
arm defconfig gcc-16.1.0
arm imx_v4_v5_defconfig clang-23
arm randconfig-001 gcc-10.5.0
arm randconfig-001-20260615 gcc-10.5.0
arm randconfig-001-20260616 gcc-9.5.0
arm randconfig-002 gcc-10.5.0
arm randconfig-002-20260615 gcc-10.5.0
arm randconfig-002-20260616 gcc-9.5.0
arm randconfig-003 gcc-10.5.0
arm randconfig-003-20260615 gcc-10.5.0
arm randconfig-003-20260616 gcc-9.5.0
arm randconfig-004 gcc-10.5.0
arm randconfig-004-20260615 gcc-10.5.0
arm randconfig-004-20260616 gcc-9.5.0
arm64 allmodconfig clang-23
arm64 allnoconfig gcc-16.1.0
arm64 defconfig gcc-16.1.0
arm64 randconfig-001 clang-23
arm64 randconfig-001-20260615 clang-23
arm64 randconfig-001-20260616 gcc-13.4.0
arm64 randconfig-002 clang-23
arm64 randconfig-002-20260615 clang-23
arm64 randconfig-002-20260616 gcc-13.4.0
arm64 randconfig-003 clang-23
arm64 randconfig-003-20260615 clang-23
arm64 randconfig-003-20260616 gcc-13.4.0
arm64 randconfig-004 clang-23
arm64 randconfig-004-20260615 clang-23
arm64 randconfig-004-20260616 gcc-13.4.0
csky allmodconfig gcc-16.1.0
csky allnoconfig gcc-16.1.0
csky defconfig gcc-16.1.0
csky randconfig-001 clang-23
csky randconfig-001-20260615 clang-23
csky randconfig-001-20260616 gcc-13.4.0
csky randconfig-002 clang-23
csky randconfig-002-20260615 clang-23
csky randconfig-002-20260616 gcc-13.4.0
hexagon allmodconfig gcc-16.1.0
hexagon allnoconfig gcc-16.1.0
hexagon defconfig gcc-16.1.0
hexagon randconfig-001-20260615 clang-18
hexagon randconfig-001-20260616 clang-23
hexagon randconfig-002-20260615 clang-18
hexagon randconfig-002-20260616 clang-23
i386 allmodconfig clang-22
i386 allnoconfig gcc-16.1.0
i386 allyesconfig clang-22
i386 buildonly-randconfig-001-20260615 clang-22
i386 buildonly-randconfig-001-20260616 clang-22
i386 buildonly-randconfig-002-20260615 clang-22
i386 buildonly-randconfig-002-20260616 clang-22
i386 buildonly-randconfig-003-20260615 clang-22
i386 buildonly-randconfig-003-20260616 clang-22
i386 buildonly-randconfig-004-20260615 clang-22
i386 buildonly-randconfig-004-20260616 clang-22
i386 buildonly-randconfig-005-20260615 clang-22
i386 buildonly-randconfig-005-20260616 clang-22
i386 buildonly-randconfig-006-20260615 clang-22
i386 buildonly-randconfig-006-20260616 clang-22
i386 defconfig gcc-16.1.0
i386 randconfig-001-20260615 clang-22
i386 randconfig-001-20260616 gcc-14
i386 randconfig-002-20260615 clang-22
i386 randconfig-002-20260616 gcc-14
i386 randconfig-003-20260615 clang-22
i386 randconfig-003-20260616 gcc-14
i386 randconfig-004-20260615 clang-22
i386 randconfig-004-20260616 gcc-14
i386 randconfig-005-20260615 clang-22
i386 randconfig-005-20260616 gcc-14
i386 randconfig-006-20260615 clang-22
i386 randconfig-006-20260616 gcc-14
i386 randconfig-007-20260615 clang-22
i386 randconfig-007-20260616 gcc-14
i386 randconfig-011-20260615 gcc-14
i386 randconfig-011-20260616 clang-22
i386 randconfig-012-20260615 gcc-14
i386 randconfig-012-20260616 clang-22
i386 randconfig-013-20260615 gcc-14
i386 randconfig-013-20260616 clang-22
i386 randconfig-014-20260615 gcc-14
i386 randconfig-014-20260616 clang-22
i386 randconfig-015-20260615 gcc-14
i386 randconfig-015-20260616 clang-22
i386 randconfig-016-20260615 gcc-14
i386 randconfig-016-20260616 clang-22
i386 randconfig-017-20260615 gcc-14
i386 randconfig-017-20260616 clang-22
loongarch allmodconfig clang-19
loongarch allmodconfig clang-23
loongarch allnoconfig gcc-16.1.0
loongarch defconfig clang-23
loongarch randconfig-001-20260615 clang-18
loongarch randconfig-001-20260616 clang-23
loongarch randconfig-002-20260615 clang-18
loongarch randconfig-002-20260616 clang-23
m68k allmodconfig gcc-16.1.0
m68k allnoconfig gcc-16.1.0
m68k allyesconfig clang-23
m68k allyesconfig gcc-16.1.0
m68k defconfig clang-23
m68k defconfig gcc-16.1.0
microblaze allnoconfig gcc-16.1.0
microblaze allyesconfig gcc-16.1.0
microblaze defconfig clang-23
microblaze defconfig gcc-16.1.0
mips allmodconfig gcc-16.1.0
mips allnoconfig gcc-16.1.0
mips allyesconfig gcc-16.1.0
mips maltaup_xpa_defconfig gcc-16.1.0
nios2 allmodconfig clang-20
nios2 allnoconfig clang-23
nios2 defconfig clang-23
nios2 defconfig gcc-11.5.0
nios2 randconfig-001-20260615 clang-18
nios2 randconfig-001-20260616 clang-23
nios2 randconfig-002-20260615 clang-18
nios2 randconfig-002-20260616 clang-23
openrisc allmodconfig clang-20
openrisc allnoconfig clang-23
openrisc defconfig gcc-16.1.0
parisc allmodconfig gcc-16.1.0
parisc allnoconfig clang-23
parisc allyesconfig clang-17
parisc allyesconfig clang-23
parisc defconfig gcc-16.1.0
parisc randconfig-001-20260615 gcc-8.5.0
parisc randconfig-001-20260616 gcc-8.5.0
parisc randconfig-002-20260615 gcc-13.4.0
parisc randconfig-002-20260616 gcc-8.5.0
parisc64 defconfig clang-23
parisc64 defconfig gcc-16.1.0
powerpc allmodconfig gcc-16.1.0
powerpc allnoconfig clang-23
powerpc randconfig-001-20260615 gcc-8.5.0
powerpc randconfig-001-20260616 gcc-8.5.0
powerpc randconfig-002-20260615 clang-23
powerpc randconfig-002-20260616 gcc-8.5.0
powerpc64 randconfig-001-20260615 clang-23
powerpc64 randconfig-001-20260616 gcc-8.5.0
powerpc64 randconfig-002-20260615 gcc-8.5.0
powerpc64 randconfig-002-20260616 gcc-8.5.0
riscv allmodconfig clang-23
riscv allnoconfig clang-23
riscv allyesconfig clang-23
riscv defconfig gcc-16.1.0
riscv randconfig-001-20260615 gcc-16.1.0
riscv randconfig-001-20260616 gcc-16.1.0
riscv randconfig-002-20260615 gcc-16.1.0
riscv randconfig-002-20260616 gcc-16.1.0
s390 allmodconfig clang-17
s390 allmodconfig clang-23
s390 allnoconfig clang-23
s390 allyesconfig gcc-16.1.0
s390 defconfig gcc-16.1.0
s390 randconfig-001-20260615 gcc-16.1.0
s390 randconfig-001-20260616 gcc-16.1.0
s390 randconfig-002-20260615 gcc-16.1.0
s390 randconfig-002-20260616 gcc-16.1.0
sh allmodconfig gcc-16.1.0
sh allnoconfig clang-23
sh allyesconfig clang-17
sh allyesconfig clang-23
sh defconfig gcc-14
sh defconfig gcc-16.1.0
sh randconfig-001-20260615 gcc-16.1.0
sh randconfig-001-20260616 gcc-16.1.0
sh randconfig-002-20260615 gcc-16.1.0
sh randconfig-002-20260616 gcc-16.1.0
sparc allnoconfig clang-23
sparc defconfig gcc-16.1.0
sparc randconfig-001-20260615 gcc-13.4.0
sparc randconfig-001-20260615 gcc-15.2.0
sparc randconfig-001-20260616 gcc-8.5.0
sparc randconfig-002-20260615 gcc-15.2.0
sparc randconfig-002-20260616 gcc-8.5.0
sparc64 allmodconfig clang-20
sparc64 defconfig clang-23
sparc64 defconfig gcc-14
sparc64 randconfig-001-20260615 gcc-15.2.0
sparc64 randconfig-001-20260615 gcc-8.5.0
sparc64 randconfig-001-20260616 gcc-8.5.0
sparc64 randconfig-002-20260615 gcc-15.2.0
sparc64 randconfig-002-20260615 gcc-8.5.0
sparc64 randconfig-002-20260616 gcc-8.5.0
um allmodconfig clang-17
um allmodconfig clang-23
um allnoconfig clang-23
um allyesconfig gcc-16.1.0
um defconfig clang-23
um defconfig gcc-14
um i386_defconfig gcc-14
um randconfig-001-20260615 clang-23
um randconfig-001-20260615 gcc-15.2.0
um randconfig-001-20260616 gcc-8.5.0
um randconfig-002-20260615 clang-23
um randconfig-002-20260615 gcc-15.2.0
um randconfig-002-20260616 gcc-8.5.0
um x86_64_defconfig clang-23
um x86_64_defconfig gcc-14
x86_64 allmodconfig clang-22
x86_64 allnoconfig clang-23
x86_64 allyesconfig clang-22
x86_64 buildonly-randconfig-001 clang-22
x86_64 buildonly-randconfig-001 gcc-12
x86_64 buildonly-randconfig-001-20260615 clang-22
x86_64 buildonly-randconfig-001-20260616 gcc-14
x86_64 buildonly-randconfig-002 clang-22
x86_64 buildonly-randconfig-002-20260615 clang-22
x86_64 buildonly-randconfig-002-20260615 gcc-14
x86_64 buildonly-randconfig-002-20260616 gcc-14
x86_64 buildonly-randconfig-003 clang-22
x86_64 buildonly-randconfig-003 gcc-14
x86_64 buildonly-randconfig-003-20260615 clang-22
x86_64 buildonly-randconfig-003-20260616 gcc-14
x86_64 buildonly-randconfig-004 clang-22
x86_64 buildonly-randconfig-004 gcc-14
x86_64 buildonly-randconfig-004-20260615 clang-22
x86_64 buildonly-randconfig-004-20260616 gcc-14
x86_64 buildonly-randconfig-005 clang-22
x86_64 buildonly-randconfig-005 gcc-14
x86_64 buildonly-randconfig-005-20260615 clang-22
x86_64 buildonly-randconfig-005-20260615 gcc-14
x86_64 buildonly-randconfig-005-20260616 gcc-14
x86_64 buildonly-randconfig-006 clang-22
x86_64 buildonly-randconfig-006-20260615 clang-22
x86_64 buildonly-randconfig-006-20260616 gcc-14
x86_64 defconfig gcc-14
x86_64 kexec clang-22
x86_64 randconfig-001-20260615 clang-22
x86_64 randconfig-002-20260615 clang-22
x86_64 randconfig-003-20260615 clang-22
x86_64 randconfig-004-20260615 clang-22
x86_64 randconfig-005-20260615 clang-22
x86_64 randconfig-006-20260615 clang-22
x86_64 randconfig-011 clang-22
x86_64 randconfig-011-20260615 clang-22
x86_64 randconfig-011-20260616 clang-22
x86_64 randconfig-012 clang-22
x86_64 randconfig-012-20260615 clang-22
x86_64 randconfig-012-20260616 clang-22
x86_64 randconfig-013 clang-22
x86_64 randconfig-013-20260615 clang-22
x86_64 randconfig-013-20260616 clang-22
x86_64 randconfig-014 clang-22
x86_64 randconfig-014-20260615 clang-22
x86_64 randconfig-014-20260616 clang-22
x86_64 randconfig-015 clang-22
x86_64 randconfig-015-20260615 clang-22
x86_64 randconfig-015-20260616 clang-22
x86_64 randconfig-016 clang-22
x86_64 randconfig-016-20260615 clang-22
x86_64 randconfig-016-20260616 clang-22
x86_64 randconfig-071 gcc-13
x86_64 randconfig-071-20260615 gcc-13
x86_64 randconfig-071-20260615 gcc-14
x86_64 randconfig-071-20260616 gcc-14
x86_64 randconfig-072 gcc-13
x86_64 randconfig-072-20260615 clang-22
x86_64 randconfig-072-20260615 gcc-13
x86_64 randconfig-072-20260616 gcc-14
x86_64 randconfig-073 gcc-13
x86_64 randconfig-073-20260615 clang-22
x86_64 randconfig-073-20260615 gcc-13
x86_64 randconfig-073-20260616 gcc-14
x86_64 randconfig-074 gcc-13
x86_64 randconfig-074-20260615 gcc-13
x86_64 randconfig-074-20260615 gcc-14
x86_64 randconfig-074-20260616 gcc-14
x86_64 randconfig-075 gcc-13
x86_64 randconfig-075-20260615 clang-22
x86_64 randconfig-075-20260615 gcc-13
x86_64 randconfig-075-20260616 gcc-14
x86_64 randconfig-076 gcc-13
x86_64 randconfig-076-20260615 clang-22
x86_64 randconfig-076-20260615 gcc-13
x86_64 randconfig-076-20260616 gcc-14
x86_64 rhel-9.4 clang-22
x86_64 rhel-9.4-bpf gcc-14
x86_64 rhel-9.4-func clang-22
x86_64 rhel-9.4-kselftests clang-22
x86_64 rhel-9.4-kunit gcc-14
x86_64 rhel-9.4-ltp gcc-14
x86_64 rhel-9.4-rust clang-22
xtensa allnoconfig clang-23
xtensa allyesconfig clang-20
xtensa randconfig-001-20260615 gcc-13.4.0
xtensa randconfig-001-20260615 gcc-15.2.0
xtensa randconfig-001-20260616 gcc-8.5.0
xtensa randconfig-002-20260615 gcc-15.2.0
xtensa randconfig-002-20260615 gcc-8.5.0
xtensa randconfig-002-20260616 gcc-8.5.0
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v6 RESEND 0/2] pinctrl: qcom: lpass-lpi: Switch to PM clock framework
From: Linus Walleij @ 2026-06-15 22:37 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Bjorn Andersson, linux-arm-msm, linux-gpio, linux-kernel,
mohammad.rafi.shaik, Ajay Kumar Nandam
In-Reply-To: <CAMRc=MfLspdy3Ncx7_dq57KXYs2ge=ZCp3jO2D7z6Gd=8XN9XQ@mail.gmail.com>
On Mon, Jun 15, 2026 at 5:54 PM Bartosz Golaszewski <brgl@kernel.org> wrote:
> > Actually the volume of Qualcomm patches has gone up the recent
> > months so I'm starting to feel like I need a Qualcomm submaintainer
> > who does the nice things that Geert does for Renesas and Krzysztof
> > does for Samsung Exynos and collect the Qcom/MSM patches and
> > send pull request to me. Think about it! (I know very well Bjorn and
> > Krzysztof have enough to do alread, so maybe someone else?)
>
> Hi!
>
> I've been volunteered to do this. If you agree, should I have a separate tree
> like for Renesas and Samsung and make pull-requests to you?
Excellent choice, I trust this maintainer a lot :D
Yes just set up some tree on kernel org (or use a branch on one
of your existing ones if it makes more sense) and send signed
pull request from there.
Chain of trust with GPG keys is already in place.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: pinctrl: qcom,pmic-gpio: Add Qualcomm PMK7750
From: Rob Herring (Arm) @ 2026-06-15 21:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-arm-msm, Abel Vesa, devicetree, linux-gpio,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij, Bjorn Andersson,
linux-kernel
In-Reply-To: <20260612090426.23403-2-krzysztof.kozlowski@oss.qualcomm.com>
On Fri, 12 Jun 2026 11:04:27 +0200, Krzysztof Kozlowski wrote:
> Document Qualcomm PMK7750 GPIO used with Eliza SoC. PMIC is almost the
> same as PMK8550, thus compatible with it.
>
> Cc: Abel Vesa <abel.vesa@oss.qualcomm.com>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
> ---
>
> Changes in v3:
> 1. Drop stale pmk7750 from main enum lisrt (the big one) - leftover of
> previous version
>
> Changes in v2:
> 1. Add fallback compatible.
> ---
> .../bindings/pinctrl/qcom,pmic-gpio.yaml | 151 +++++++++---------
> 1 file changed, 78 insertions(+), 73 deletions(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v11 4/6] dt-bindings: pinctrl: s32g2-siul2: describe GPIO and EIRQ resources
From: Rob Herring (Arm) @ 2026-06-15 18:49 UTC (permalink / raw)
To: Khristine Andreea Barbulescu
Cc: Linus Walleij, Rafael J. Wysocki, Eric Chanudet, Christophe Lizzi,
NXP S32 Linux Team, Larisa Grigore, Vincent Guittot,
Pengutronix Kernel Team, linux-kernel, Alberto Ruiz,
Matthias Brugger, Sascha Hauer, linux-arm-kernel,
Greg Kroah-Hartman, Fabio Estevam, Krzysztof Kozlowski,
Ghennadi Procopciuc, Dong Aisheng, Chester Lin, imx, Lee Jones,
linux-gpio, Enric Balletbo, Shawn Guo, Bartosz Golaszewski,
devicetree, Conor Dooley, Jacky Bai, Srinivas Kandagatla
In-Reply-To: <20260610132116.1998140-5-khristineandreea.barbulescu@oss.nxp.com>
On Wed, 10 Jun 2026 15:21:14 +0200, Khristine Andreea Barbulescu wrote:
> Extend the S32G2 SIUL2 pinctrl binding to describe the GPIO data and
> external interrupt resources present in the same SIUL2 hardware block.
>
> Besides the MSCR and IMCR registers used for pin multiplexing and pad
> configuration, SIUL2 also contains PGPDO and PGPDI registers
> for GPIO data and EIRQ registers for external interrupt control.
>
> Add GPIO controller properties because the SIUL2 block also provides
> GPIO functionality, and gpio-ranges are needed to describe the
> mapping between GPIO lines and pin controller pins.
>
> Document the interrupt controller properties. The SIUL2 block
> contains EIRQ hardware as part of the same register space. IRQ support
> itself will be added in a follow-up patch series.
>
> Update the example accordingly to show the complete SIUL2 register
> layout, including the GPIO data and EIRQ register windows.
>
> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
> ---
> .../pinctrl/nxp,s32g2-siul2-pinctrl.yaml | 90 +++++++++++++++++--
> 1 file changed, 84 insertions(+), 6 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [06/11] pinctrl: airoha: an7583: fix incorrect led mapping in phy4_led1 pin function
From: Mikhail Kshevetskiy @ 2026-06-15 17:19 UTC (permalink / raw)
To: Wayen Yan; +Cc: linux-gpio, lorenzo
In-Reply-To: <6a2ffcc6.2afc2531.35ffc5.cfba@mx.google.com>
On 6/15/26 16:23, Wayen Yan wrote:
> [You don't often get email from win847@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On 2026-06-06, Mikhail Kshevetskiy wrote:
>> phy4_led1 pin function maps led incorrectly. It uses the same map as
>> phy3_led1. PHY{X} should map to LAN{N}_PHY_LED_MAP(X-1).
>>
>> Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
> Hi Mikhail,
>
> Thanks for this fix series. I noticed that the same MAP(2) bug also
> exists in the EN7581 phy4_led1 table, not just AN7583.
>
> In drivers/pinctrl/mediatek/pinctrl-airoha.c:
>
> EN7581 phy4_led1_func_group[] also uses LAN*_PHY_LED_MAP(2) — identical
> to phy3_led1. Should be MAP(3) following the PHY{X} -> MAP(X-1) rule:
>
> AIROHA_PINCTRL_PHY_LED1("gpio43", ..., LAN0_PHY_LED_MAP(2)), // EN7581
> AIROHA_PINCTRL_PHY_LED1("gpio44", ..., LAN1_PHY_LED_MAP(2)), // EN7581
> AIROHA_PINCTRL_PHY_LED1("gpio45", ..., LAN2_PHY_LED_MAP(2)), // EN7581
> AIROHA_PINCTRL_PHY_LED1("gpio46", ..., LAN3_PHY_LED_MAP(2)), // EN7581
>
> Could you include EN7581 in this fix as well?
This is a previous patch in a series, isn't it?
>
> Regards,
> Wayen
^ permalink raw reply
* Re: [PATCH v6 1/7] dt-bindings: mfd: mt6397: Add MT6392 PMIC
From: Luca Leonardo Scorcia @ 2026-06-15 17:09 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-mediatek, Fabien Parent, Val Packett, Dmitry Torokhov,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sen Chu,
Sean Wang, Macpaul Lin, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, Linus Walleij, Julien Massot,
Louis-Alexis Eyraud, Akari Tsuyukusa, Chen Zhong, linux-input,
devicetree, linux-kernel, linux-pm, linux-arm-kernel, linux-gpio
In-Reply-To: <20260615-palatable-aerobics-3091229b6ada@spud>
Hi,
yes, sorry about that, series v6 has been superseded by v7 (I replied
to the thread and marked it as archived in patchwork, please let me
know if I have to do something else to mark it as obsolete).
Sashiko was correct, the regulators node is required for this device.
Sashiko also has suggestions for v7, a few pre existing issues and a
few nits here and there but some are actual improvements. One bit that
caught my eye is the use of the modeset register in the
mt6392_ldo_get_mode function. I have to double check that with the
data sheet and the android kernel sources. Not sure if I can do that
before next week though.
Is there any way I can trigger a Sashiko review before sending patches
to the ML?
Thank you,
Luca
^ permalink raw reply
* Re: [PATCH RFC 1/2] dt-bindings: pinctl: amlogic,pinctrl-a4: Add gpio irq property
From: Conor Dooley @ 2026-06-15 16:52 UTC (permalink / raw)
To: xianwei.zhao
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
linux-amlogic, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260611-gpio-to-irq-v1-1-12201716f23f@amlogic.com>
[-- Attachment #1: Type: text/plain, Size: 85 bytes --]
Given Linus' comments on the cover letter,
pw-bot: changes-requested
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v6 1/7] dt-bindings: mfd: mt6397: Add MT6392 PMIC
From: Conor Dooley @ 2026-06-15 16:50 UTC (permalink / raw)
To: Luca Leonardo Scorcia
Cc: linux-mediatek, Fabien Parent, Val Packett, Dmitry Torokhov,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sen Chu,
Sean Wang, Macpaul Lin, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, Linus Walleij, Julien Massot,
Louis-Alexis Eyraud, Akari Tsuyukusa, Chen Zhong, linux-input,
devicetree, linux-kernel, linux-pm, linux-arm-kernel, linux-gpio
In-Reply-To: <20260612200717.361018-2-l.scorcia@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1612 bytes --]
On Fri, Jun 12, 2026 at 10:04:06PM +0200, Luca Leonardo Scorcia wrote:
> From: Fabien Parent <parent.f@gmail.com>
>
> Add the initial bindings for the MT6392 PMIC and its RTC device.
>
> Signed-off-by: Fabien Parent <parent.f@gmail.com>
> Signed-off-by: Val Packett <val@packett.cool>
> Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
Sashiko complaint about missing regulators looks valid.
Is it?
Cheers,
Conor.
> ---
> .../devicetree/bindings/mfd/mediatek,mt6397.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
> index 3cbc0dc12c31..e39e81aa9924 100644
> --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
> +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
> @@ -40,6 +40,10 @@ properties:
> - mediatek,mt6358
> - mediatek,mt6359
> - mediatek,mt6397
> + - items:
> + - enum:
> + - mediatek,mt6392
> + - const: mediatek,mt6323
> - items:
> - enum:
> - mediatek,mt6366
> @@ -72,6 +76,10 @@ properties:
> - mediatek,mt6331-rtc
> - mediatek,mt6358-rtc
> - mediatek,mt6397-rtc
> + - items:
> + - enum:
> + - mediatek,mt6392-rtc
> + - const: mediatek,mt6323-rtc
> - items:
> - enum:
> - mediatek,mt6359-rtc
> --
> 2.43.0
>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v6 RESEND 0/2] pinctrl: qcom: lpass-lpi: Switch to PM clock framework
From: Bartosz Golaszewski @ 2026-06-15 15:54 UTC (permalink / raw)
To: Linus Walleij
Cc: Bjorn Andersson, linux-arm-msm, linux-gpio, linux-kernel,
mohammad.rafi.shaik, Ajay Kumar Nandam
In-Reply-To: <CAD++jL=gPF9jzPe90sy0W6ogEWq6LqTnbRfnoH5qxwGnBTiGMg@mail.gmail.com>
On Tue, 26 May 2026 11:37:43 +0200, Linus Walleij <linusw@kernel.org> said:
> On Fri, May 22, 2026 at 10:47 PM Ajay Kumar Nandam
> <ajay.nandam@oss.qualcomm.com> wrote:
>
>> This series converts LPASS LPI pinctrl runtime clock handling to the PM
>> clock framework and ensures GPIO register accesses runtime-resume the
>> block before MMIO.
>
> I hope I can get some feedback from the Qualcomm maintainers
> or I will feel tempted to just apply this...
>
> Actually the volume of Qualcomm patches has gone up the recent
> months so I'm starting to feel like I need a Qualcomm submaintainer
> who does the nice things that Geert does for Renesas and Krzysztof
> does for Samsung Exynos and collect the Qcom/MSM patches and
> send pull request to me. Think about it! (I know very well Bjorn and
> Krzysztof have enough to do alread, so maybe someone else?)
>
Hi!
I've been volunteered to do this. If you agree, should I have a separate tree
like for Renesas and Samsung and make pull-requests to you?
Bart
^ permalink raw reply
* Re: [PATCH v2 0/2] upboard pinctrl support for device id INTC1055
From: Andy Shevchenko @ 2026-06-15 15:00 UTC (permalink / raw)
To: GaryWang
Cc: Linus Walleij, Mika Westerberg, Andy Shevchenko, Thomas Richard,
Daniele Cleri, JunYingLai, Louis Chen, linux-gpio, linux-kernel
In-Reply-To: <CANYHO6pmq+YE3M3kUOegsYwxjfV3qBasX56RSTtwRvVMaFCgPg@mail.gmail.com>
On Mon, Jun 15, 2026 at 10:25:32PM +0800, GaryWang wrote:
> On Mon, 15 Jun 2026 at 22:07, Andy Shevchenko
> <andriy.shevchenko@intel.com> wrote:
> > On Mon, Jun 15, 2026 at 02:32:51PM +0200, Linus Walleij wrote:
> > > On Fri, Jun 12, 2026 at 12:13 PM GaryWang <is0124@gmail.com> wrote:
> > >
> > > > Add missing groups and functions in Tigerlake's pinctrl driver for INTC1055.
> > > > Add support "UP Xtreme i12", "UP Squared Pro 7000", "UP Squared i12", "UP 7000" boards.
> > > >
> > > > The pinctrl-upboard is provide additional driving power & pin mux function
> > > > through native SOC pins -> FPGA/CPLD -> hat pins for flexable board level
> > > > applications. it's probe from ACPI device id AANT0F01 & AANT0F04.
> > > >
> > > > Signed-off-by: GaryWang <is0124@gmail.com>
> > >
> > > LGTM
> > > Acked-by: Linus Walleij <linusw@kernel.org>
> > >
> > > Since these touch Tigerlake, I expect Andy to queue and send me
> > > the patches from his tree.
> >
> > Yes, this is the idea, but first I want to hear form Gary about Up 7000, which
> > seems doesn't work with this.
> >
> It's my bad, the up squared pro has p & n series processor, I only checked the
> p series.
> The p series is used INTC1055 and n series is using INTC1057 has confirmed.
> I need remove n series boards, until we finished testing, thanks.
Okay, please finish testing, update commit messages (and code if necessary),
collected tags, and send a v3. Take your time as it won't be proceeded within
two weeks (merge window is ongoing).
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH 3/3] pinctrl: qcom: Avoid assigning thread_op_remain in unthreaded test
From: Konrad Dybcio @ 2026-06-15 14:38 UTC (permalink / raw)
To: Sneh Mankad, Bjorn Andersson, Linus Walleij, Yuanjie Yang
Cc: linux-arm-msm, linux-gpio, linux-kernel
In-Reply-To: <8b110f90-2001-4655-856d-ec8cff98fc0a@oss.qualcomm.com>
On 6/10/26 8:16 AM, Sneh Mankad wrote:
>
>
> On 03-Jun-26 7:28 PM, Konrad Dybcio wrote:
>>
>>
>> On 29-May-26 14:55, Sneh Mankad wrote:
>>> tlmm_test_rising_while_disabled() sets thread_op_remain to 10, but this
>>> variable is only used by the threaded IRQ handler to control the number
>>> of GPIO pin toggles. Since tlmm_test_rising_while_disabled() does not
>>> register a threaded IRQ handler, the assignment is never used.
>>>
>>> Remove the thread_op_remain assignment from
>>> tlmm_test_rising_while_disabled().
>>>
>>> This does not cause any change in functionality.
>>>
>>> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
>>> ---
>>> drivers/pinctrl/qcom/tlmm-test.c | 1 -
>>> 1 file changed, 1 deletion(-)
>>>
>>> diff --git a/drivers/pinctrl/qcom/tlmm-test.c b/drivers/pinctrl/qcom/tlmm-test.c
>>> index 007d6539ceced294e81cfbe93a00c75a98c858de..e9e04300ab3687825255885821ebde0f3ee586a8 100644
>>> --- a/drivers/pinctrl/qcom/tlmm-test.c
>>> +++ b/drivers/pinctrl/qcom/tlmm-test.c
>>> @@ -521,7 +521,6 @@ static void tlmm_test_rising_while_disabled(struct kunit *test)
>>> unsigned int before_edge;
>>>
>>> priv->intr_op = TLMM_TEST_COUNT;
>>> - atomic_set(&priv->thread_op_remain, 10);
>>
>> Should this be setting priv->intr_op_remain instead?
>
> Should not be needed.
> priv->intr_op_remain is to indicate the hard IRQ handler how many times to toggle the GPIO line within the irq handler.
> Here the test case does not require any toggles within IRQ handler.
Oh yeah seems you're right
> I also found other test cases where intr_op_remain is assigned but never used. Will remove them in v2.
Thanks!
Konrad
^ permalink raw reply
* Re: [PATCH v2 4/5] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk
From: Peter Griffin @ 2026-06-15 14:37 UTC (permalink / raw)
To: Alim Akhtar
Cc: krzk, robh, conor+dt, linusw, linux-samsung-soc, linux-kernel,
devicetree, linux-gpio, hajun.sung
In-Reply-To: <20260615085252.1964423-5-alim.akhtar@samsung.com>
Hi Alim,
On Mon, 15 Jun 2026 at 09:34, Alim Akhtar <alim.akhtar@samsung.com> wrote:
>
> Add initial devicetree support for Samsung smdk board using
> Exynos8855 SoC.
I think it would be worthwhile adding a more verbose description of
the Exynos8855 SoC in the commit message e.g. a brief list of the
major IPs on the SoC.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
[..]
> diff --git a/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
> new file mode 100644
> index 000000000000..f5132bcaa47c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung Exynos8855 SMDK board device tree source
> + *
> + * Copyright (C) 2026 Samsung Electronics Co., Ltd.
> + *
> + * Device tree source file for WinLink's E850-96 board which is based on
> + * Samsung Exynos8855 SoC.
E850-96 isn't based on the Exynos8855 SoC. I guess it's leftover from
a copy/paste.
regards,
Peter
> + */
> +
> +/dts-v1/;
> +
> +#include "exynos8855.dtsi"
> +
> +/ {
> + model = "Samsung Exynos8855 SMDK board";
> + compatible = "samsung,exynos8855-smdk","samsung,exynos8855";
> +
> + chosen {
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x80000000>;
> + };
> +
> +};
> +
> +&oscclk {
> + clock-frequency = <76800000>;
> +};
> +
> diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
> new file mode 100644
> index 000000000000..d403f41bbecb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
> @@ -0,0 +1,199 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung Exynos8855 SoC device tree source
> + *
> + * Copyright (C) 2023 Samsung Electronics Co., Ltd.
> + *
> + * Samsung Exynos8855 SoC device nodes are listed in this file.
> + * Exynos8855 based board files can include this file and provide
> + * values for board specific bindings.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "samsung,exynos8855";
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + pinctrl0 = &pinctrl_alive;
> + pinctrl1 = &pinctrl_cmgp;
> + pinctrl2 = &pinctrl_hsi_ufs;
> + pinctrl3 = &pinctrl_peric;
> + pinctrl4 = &pinctrl_pericmmc;
> + pinctrl5 = &pinctrl_usi;
> + };
> +
> + oscclk: clock-oscclk {
> + compatible = "fixed-clock";
> + clock-output-names = "oscclk";
> + #clock-cells = <0>;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu4>;
> + };
> + core1 {
> + cpu = <&cpu5>;
> + };
> + core2 {
> + cpu = <&cpu6>;
> + };
> + };
> +
> + cluster2 {
> + core0 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a520";
> + reg = <0x0>;
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a520";
> + reg = <0x100>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a520";
> + reg = <0x200>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a520";
> + reg = <0x300>;
> + enable-method = "psci";
> + };
> +
> + cpu4: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a720";
> + reg = <0x400>;
> + enable-method = "psci";
> + };
> +
> + cpu5: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a720";
> + reg = <0x500>;
> + enable-method = "psci";
> + };
> +
> + cpu6: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a720";
> + reg = <0x600>;
> + enable-method = "psci";
> + };
> +
> + cpu7: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a720";
> + reg = <0x700>;
> + enable-method = "psci";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x20000000>;
> +
> + gic: interrupt-controller@10200000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x10200000 0x10000>,
> + <0x10240000 0x140000>;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pinctrl_alive: pinctrl@11850000 {
> + compatible = "samsung,exynos8855-pinctrl";
> + reg = <0x11850000 0x1000>;
> +
> + wakeup-interrupt-controller {
> + compatible = "samsung,exynos850-wakeup-eint",
> + "samsung,exynos7-wakeup-eint";
> + };
> + };
> +
> + pinctrl_cmgp: pinctrl@12030000 {
> + compatible = "samsung,exynos8855-pinctrl";
> + reg = <0x12030000 0x1000>;
> + };
> +
> + pinctrl_usi: pinctrl@15030000 {
> + compatible = "samsung,exynos8855-pinctrl";
> + reg = <0x15030000 0x1000>;
> + };
> +
> + pinctrl_peric: pinctrl@15440000 {
> + compatible = "samsung,exynos8855-pinctrl";
> + reg = <0x15440000 0x1000>;
> + };
> +
> + pinctrl_pericmmc: pinctrl@154f0000 {
> + compatible = "samsung,exynos8855-pinctrl";
> + reg = <0x154f0000 0x1000>;
> + };
> +
> + pinctrl_hsi_ufs: pinctrl@17040000 {
> + compatible = "samsung,exynos8855-pinctrl";
> + reg = <0x17040000 0x1000>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + /* Hypervisor Virtual Timer interrupt is not wired to GIC */
> + interrupts =
> + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +};
> +
> +#include "exynos8855-pinctrl.dtsi"
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH v2 0/2] upboard pinctrl support for device id INTC1055
From: GaryWang @ 2026-06-15 14:25 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Linus Walleij, Mika Westerberg, Andy Shevchenko, Thomas Richard,
Daniele Cleri, JunYingLai, Louis Chen, linux-gpio, linux-kernel
In-Reply-To: <ajAHE29I3IWQNVsV@ashevche-desk.local>
On Mon, 15 Jun 2026 at 22:07, Andy Shevchenko
<andriy.shevchenko@intel.com> wrote:
>
> On Mon, Jun 15, 2026 at 02:32:51PM +0200, Linus Walleij wrote:
> > On Fri, Jun 12, 2026 at 12:13 PM GaryWang <is0124@gmail.com> wrote:
> >
> > > Add missing groups and functions in Tigerlake's pinctrl driver for INTC1055.
> > > Add support "UP Xtreme i12", "UP Squared Pro 7000", "UP Squared i12", "UP 7000" boards.
> > >
> > > The pinctrl-upboard is provide additional driving power & pin mux function
> > > through native SOC pins -> FPGA/CPLD -> hat pins for flexable board level
> > > applications. it's probe from ACPI device id AANT0F01 & AANT0F04.
> > >
> > > Signed-off-by: GaryWang <is0124@gmail.com>
> >
> > LGTM
> > Acked-by: Linus Walleij <linusw@kernel.org>
> >
> > Since these touch Tigerlake, I expect Andy to queue and send me
> > the patches from his tree.
>
> Yes, this is the idea, but first I want to hear form Gary about Up 7000, which
> seems doesn't work with this.
>
It's my bad, the up squared pro has p & n series processor, I only checked the
p series.
The p series is used INTC1055 and n series is using INTC1057 has confirmed.
I need remove n series boards, until we finished testing, thanks.
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH v2 3/5] pinctrl: samsung: Add Exynos8855 pinctrl configuration
From: Peter Griffin @ 2026-06-15 14:14 UTC (permalink / raw)
To: Alim Akhtar
Cc: krzk, robh, conor+dt, linusw, linux-samsung-soc, linux-kernel,
devicetree, linux-gpio, hajun.sung
In-Reply-To: <20260615085252.1964423-4-alim.akhtar@samsung.com>
Hi Alim,
Thanks for your patch. It's great to see more Exynos SoCs being supported!
On Mon, 15 Jun 2026 at 09:34, Alim Akhtar <alim.akhtar@samsung.com> wrote:
>
> Add pinctrl configuration for Exynos8855. The bank type
> macros are reused from Exynos850 SoC.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 123 ++++++++++++++++++
> drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
> drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
> 3 files changed, 126 insertions(+)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index fe9f92cb037e..db120ae4d847 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -943,6 +943,129 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
> .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl),
> };
>
Are you sure you want to use E850 pinctrl macros and not the GS101
ones? The GS101 macros allow the fltcon offset to be specified, which
I think is required for all Exynos9 (including e850 SoC). Youngmin
sent a series previously
https://lore.kernel.org/lkml/20251202093613.852109-1-youngmin.nam@samsung.com/
fixing up some of this but it hasn't been re-spun in a while. In
particular this patch
https://lore.kernel.org/lkml/20251202093613.852109-4-youngmin.nam@samsung.com/.
> +/* pin banks of exynos8855 pin-controller 0 (ALIVE) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks0[] __initconst = {
> + /* Must start with EINTG banks, ordered by EINT group number. */
> + EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
> + EXYNOS850_PIN_BANK_EINTW(4, 0x020, "gpa1", 0x04),
> + EXYNOS850_PIN_BANK_EINTN(3, 0x040, "gpq0"),
> + EXYNOS850_PIN_BANK_EINTN(2, 0x060, "gpq1"),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpc0", 0x10),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpc1", 0x14),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpc2", 0x18),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpc3", 0x1c),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpc4", 0x20),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpc5", 0x24),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpc6", 0x28),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpc7", 0x2c),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpc8", 0x30),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x1a0, "gpc9", 0x34),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpc10", 0x38),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpc11", 0x3c),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpc12", 0x40),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpc13", 0x44),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpc14", 0x48),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpj0", 0x4c),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpj1", 0x50),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpj2", 0x54),
> +};
> +
> +/* pin banks of exynos8855 pin-controller 1 (CMGP) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks1[] __initconst = {
> + EXYNOS850_PIN_BANK_EINTW(1, 0x00, "gpm0", 0x00),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x20, "gpm1", 0x04),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x40, "gpm2", 0x08),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x60, "gpm3", 0x0c),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x80, "gpm4", 0x10),
> + EXYNOS850_PIN_BANK_EINTW(1, 0xa0, "gpm5", 0x14),
> + EXYNOS850_PIN_BANK_EINTW(1, 0xc0, "gpm6", 0x18),
> + EXYNOS850_PIN_BANK_EINTW(1, 0xe0, "gpm7", 0x1c),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2c),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x1a0, "gpm13", 0x34),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4c),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50),
> + EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpm21", 0x54),
> +};
> +
> +
> +/* pin banks of exynos8855 pin-controller 2 (HSI UFS) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks2[] __initconst = {
> + EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gpf3", 0x00),
> +};
> +
> +/* pin banks of exynos8855 pin-controller 3 (PERIC) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks3[] __initconst = {
> + EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp0", 0x00),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpp1", 0x04),
> + EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gpp2", 0x08),
> + EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpg0", 0x0c),
> + EXYNOS850_PIN_BANK_EINTG(3, 0x80, "gpg1", 0x10),
> + EXYNOS850_PIN_BANK_EINTG(6, 0xa0, "gpb0", 0x14),
> + EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpb1", 0x18),
> +};
> +
> +/* pin banks of exynos8855 pin-controller 4 (PERICMMC) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks4[] __initconst = {
> + EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpf2", 0x00),
> +};
> +
> +/* pin banks of exynos8855 pin-controller 5 (USI) */
> +static const struct samsung_pin_bank_data exynos8855_pin_banks5[] __initconst = {
> + EXYNOS850_PIN_BANK_EINTG(8, 0x00, "gpp3", 0x00),
> + EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gpp4", 0x04),
> + EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpg2", 0x08),
> + EXYNOS850_PIN_BANK_EINTG(1, 0x60, "gpg3", 0x0c),
> +};
> +
> +static const struct samsung_pin_ctrl exynos8855_pin_ctrl[] __initconst = {
> + {
> + /* pin-controller instance 0 ALIVE data */
> + .pin_banks = exynos8855_pin_banks0,
> + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks0),
> + .eint_wkup_init = exynos_eint_wkup_init,
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
With fltcon_offset specified, you could then use
gs101_pinctrl_suspend/gs101_pinctrl_resume callbacks here.
regards,
Peter.
> + /* pin-controller instance 1 CMGP data */
> + .pin_banks = exynos8855_pin_banks1,
> + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks1),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
> + /* pin-controller instance 2 HSI UFS data */
> + .pin_banks = exynos8855_pin_banks2,
> + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks2),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
> + /* pin-controller instance 3 PERIC data */
> + .pin_banks = exynos8855_pin_banks3,
> + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks3),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
> + /* pin-controller instance 4 PERICMMC data */
> + .pin_banks = exynos8855_pin_banks4,
> + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks4),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
> + /* pin-controller instance 5 USI data */
> + .pin_banks = exynos8855_pin_banks5,
> + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks5),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + },
> +};
> +
> +const struct samsung_pinctrl_of_match_data exynos8855_of_data __initconst = {
> + .ctrl = exynos8855_pin_ctrl,
> + .num_ctrl = ARRAY_SIZE(exynos8855_pin_ctrl),
> +};
> +
> /* pin banks of exynos990 pin-controller 0 (ALIVE) */
> static struct samsung_pin_bank_data exynos990_pin_banks0[] = {
> /* Must start with EINTG banks, ordered by EINT group number. */
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> index 5ac6f6b02327..5ecc9ed4c44d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> @@ -1500,6 +1500,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
> .data = &exynos7885_of_data },
> { .compatible = "samsung,exynos850-pinctrl",
> .data = &exynos850_of_data },
> + { .compatible = "samsung,exynos8855-pinctrl",
> + .data = &exynos8855_of_data },
> { .compatible = "samsung,exynos8890-pinctrl",
> .data = &exynos8890_of_data },
> { .compatible = "samsung,exynos8895-pinctrl",
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> index 937600430a6e..bb02fb49b2af 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> @@ -396,6 +396,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
> extern const struct samsung_pinctrl_of_match_data exynos7870_of_data;
> extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
> extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
> +extern const struct samsung_pinctrl_of_match_data exynos8855_of_data;
> extern const struct samsung_pinctrl_of_match_data exynos8890_of_data;
> extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
> extern const struct samsung_pinctrl_of_match_data exynos9610_of_data;
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH v2 0/2] upboard pinctrl support for device id INTC1055
From: Andy Shevchenko @ 2026-06-15 14:07 UTC (permalink / raw)
To: Linus Walleij
Cc: GaryWang, Mika Westerberg, Andy Shevchenko, Thomas Richard,
Daniele Cleri, JunYingLai, Louis Chen, linux-gpio, linux-kernel
In-Reply-To: <CAD++jLmFKz19CRp-E=JcUnNkxNzKtSow6T8_9jDpR-wTrs9Ptw@mail.gmail.com>
On Mon, Jun 15, 2026 at 02:32:51PM +0200, Linus Walleij wrote:
> On Fri, Jun 12, 2026 at 12:13 PM GaryWang <is0124@gmail.com> wrote:
>
> > Add missing groups and functions in Tigerlake's pinctrl driver for INTC1055.
> > Add support "UP Xtreme i12", "UP Squared Pro 7000", "UP Squared i12", "UP 7000" boards.
> >
> > The pinctrl-upboard is provide additional driving power & pin mux function
> > through native SOC pins -> FPGA/CPLD -> hat pins for flexable board level
> > applications. it's probe from ACPI device id AANT0F01 & AANT0F04.
> >
> > Signed-off-by: GaryWang <is0124@gmail.com>
>
> LGTM
> Acked-by: Linus Walleij <linusw@kernel.org>
>
> Since these touch Tigerlake, I expect Andy to queue and send me
> the patches from his tree.
Yes, this is the idea, but first I want to hear form Gary about Up 7000, which
seems doesn't work with this.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
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