* [RFC PATCH 3/3] arm64: dts: mt8516/mt8167: Update pinctrl nodes for the new paris driver
From: Luca Leonardo Scorcia @ 2026-06-25 10:46 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Sean Wang, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260625104742.113803-1-l.scorcia@gmail.com>
Update the MediaTek mt8516-mt8167 SoCs descriptions to respect the
constraints of the Paris pinctrl driver.
In those SoCs the pinctrl has base address 0x10005000 for gpio settings
while 0x1000b000 is used for eint configuration.
This change also drops the no longer required syscfg_pctl syscon node
that was used before to access the gpio regmap, fixing the following
dtbs_check errors:
mt8167-pumpkin.dtb: syscfg-pctl@10005000 (syscon): compatible: ['syscon']
is too short
mt8516-pumpkin.dtb: syscfg-pctl@10005000 (syscon): compatible: ['syscon']
is too short
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 15 ++++-----------
arch/arm64/boot/dts/mediatek/mt8516.dtsi | 12 ++++--------
2 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 27cf32d7ae35..65da6c0538b1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -95,17 +95,6 @@ power-domain@MT8167_POWER_DOMAIN_CONN {
};
};
- pio: pinctrl@1000b000 {
- compatible = "mediatek,mt8167-pinctrl";
- reg = <0 0x1000b000 0 0x1000>;
- mediatek,pctl-regmap = <&syscfg_pctl>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- };
-
apmixedsys: apmixedsys@10018000 {
compatible = "mediatek,mt8167-apmixedsys", "syscon";
reg = <0 0x10018000 0 0x710>;
@@ -178,3 +167,7 @@ larb2: larb@16010000 {
};
};
};
+
+&pio {
+ compatible = "mediatek,mt8167-pinctrl";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
index b5e753759465..63f36df4d1b4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
@@ -231,17 +231,13 @@ keypad: keypad@10002000 {
status = "disabled";
};
- syscfg_pctl: syscfg-pctl@10005000 {
- compatible = "syscon";
- reg = <0 0x10005000 0 0x1000>;
- };
-
- pio: pinctrl@1000b000 {
+ pio: pinctrl@10005000 {
compatible = "mediatek,mt8516-pinctrl";
- reg = <0 0x1000b000 0 0x1000>;
- mediatek,pctl-regmap = <&syscfg_pctl>;
+ reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
+ reg-names = "base", "eint";
gpio-controller;
#gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 124>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
--
2.43.0
^ permalink raw reply related
* [RFC PATCH 2/3] pinctrl: mediatek: mt8516/mt8167: Migrate driver to pinctrl-paris platform
From: Luca Leonardo Scorcia @ 2026-06-25 10:46 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Sean Wang, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260625104742.113803-1-l.scorcia@gmail.com>
Migrate the mt8516/mt8167 pinctrl driver to the paris platform driver.
This change lets us correctly describe the two base addresses (GPIO/EINT)
used by the SoCs in their device tree. It also adds support for driving
strength capability and R1R0 pullup-pulldown on pins.
Since the driver for mt8167 pinctrl is identical to the mt8516 one except
for pin definitions there is no need for a separate driver, so drop it and
add a compatible to the other one.
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
drivers/pinctrl/mediatek/Kconfig | 11 +-
drivers/pinctrl/mediatek/Makefile | 1 -
drivers/pinctrl/mediatek/pinctrl-mt8167.c | 345 --------
drivers/pinctrl/mediatek/pinctrl-mt8516.c | 770 +++++++++++-------
drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h | 562 +++++++------
drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h | 512 ++++++------
6 files changed, 1006 insertions(+), 1195 deletions(-)
delete mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8167.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 97980cc28b9c..28edd53f12ed 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -214,13 +214,6 @@ config PINCTRL_MT7988
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE
-config PINCTRL_MT8167
- bool "MediaTek MT8167 pin control"
- depends on OF
- depends on ARM64 || COMPILE_TEST
- default ARM64 && ARCH_MEDIATEK
- select PINCTRL_MTK
-
config PINCTRL_MT8173
bool "MediaTek MT8173 pin control"
depends on OF
@@ -300,11 +293,11 @@ config PINCTRL_MT8365
select PINCTRL_MTK
config PINCTRL_MT8516
- bool "MediaTek MT8516 pin control"
+ bool "MediaTek MT8516/MT8167 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
- select PINCTRL_MTK
+ select PINCTRL_MTK_PARIS
# For PMIC
config PINCTRL_MT6397
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 6dc17b0c23f9..1533a93b14d3 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -30,7 +30,6 @@ obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
-obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
deleted file mode 100644
index c812d614e9d4..000000000000
--- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c
+++ /dev/null
@@ -1,345 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2020 MediaTek Inc.
- * Author: Min.Guo <min.guo@mediatek.com>
- */
-
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <linux/of.h>
-#include <linux/module.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#include "pinctrl-mtk-common.h"
-#include "pinctrl-mtk-mt8167.h"
-
-static const struct mtk_drv_group_desc mt8167_drv_grp[] = {
- /* 0E4E8SR 4/8/12/16 */
- MTK_DRV_GRP(4, 16, 1, 2, 4),
- /* 0E2E4SR 2/4/6/8 */
- MTK_DRV_GRP(2, 8, 1, 2, 2),
- /* E8E4E2 2/4/6/8/10/12/14/16 */
- MTK_DRV_GRP(2, 16, 0, 2, 2)
-};
-
-static const struct mtk_pin_drv_grp mt8167_pin_drv[] = {
- MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
-
- MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
-
- MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
-
- MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
-
- MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
- MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
- MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
-
- MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
-
- MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
-
- MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
-
- MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
- MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
- MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
-
- MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
- MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
-
- MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
-
- MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
-
- MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
- MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
- MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
-
- MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
-
- MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
-
- MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
-
- MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
- MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
- MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
-
- MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
-
- MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
-
- MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
-
- MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
-
- MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
-
- MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
-
- MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
-
- MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
-
- MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
-
- MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
-
- MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
-
- MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
-
- MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
-};
-
-static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = {
- MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
-
- MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
-
- MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
-
- MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
-
- MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
-};
-
-static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
- MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
- MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
- MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
- MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
- MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
- MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
- MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
- MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
- MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
- MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
- MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
- MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
- MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
- MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
- MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
- MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
- MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
- MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
- MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
- MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
- MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
- MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
- MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
- MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
- MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
- MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
- MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
- MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
- MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
- MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
- MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
- MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
- MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
- MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
- MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
- MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
- MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
- MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
- MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
- MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
- MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
- MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
- MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
- MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
- MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
-};
-
-static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
- MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
- MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
- MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
- MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
- MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
- MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
- MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
- MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
- MTK_PIN_IES_SMT_SPEC(34, 39, 0xA00, 2),
- MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
- MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
- MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
- MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
- MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
- MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
- MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
- MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
- MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
- MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
- MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
- MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
- MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
- MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
- MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
- MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
- MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
-
- MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
- MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
- MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
- MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
- MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
- MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
- MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
- MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
- MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
- MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
- MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
- MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
- MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
- MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
- MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
- MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
- MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
- MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
- MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
-};
-
-static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
- .pins = mtk_pins_mt8167,
- .npins = ARRAY_SIZE(mtk_pins_mt8167),
- .grp_desc = mt8167_drv_grp,
- .n_grp_cls = ARRAY_SIZE(mt8167_drv_grp),
- .pin_drv_grp = mt8167_pin_drv,
- .n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv),
- .spec_ies = mt8167_ies_set,
- .n_spec_ies = ARRAY_SIZE(mt8167_ies_set),
- .spec_pupd = mt8167_spec_pupd,
- .n_spec_pupd = ARRAY_SIZE(mt8167_spec_pupd),
- .spec_smt = mt8167_smt_set,
- .n_spec_smt = ARRAY_SIZE(mt8167_smt_set),
- .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
- .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
- .dir_offset = 0x0000,
- .pullen_offset = 0x0500,
- .pullsel_offset = 0x0600,
- .dout_offset = 0x0100,
- .din_offset = 0x0200,
- .pinmux_offset = 0x0300,
- .type1_start = 125,
- .type1_end = 125,
- .port_shf = 4,
- .port_mask = 0xf,
- .port_align = 4,
- .mode_mask = 0xf,
- .mode_per_reg = 5,
- .mode_shf = 4,
- .eint_hw = {
- .port_mask = 7,
- .ports = 6,
- .ap_num = 169,
- .db_cnt = 64,
- .db_time = debounce_time_mt6795,
- },
-};
-
-static const struct of_device_id mt8167_pctrl_match[] = {
- { .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data },
- {}
-};
-
-MODULE_DEVICE_TABLE(of, mt8167_pctrl_match);
-
-static struct platform_driver mtk_pinctrl_driver = {
- .probe = mtk_pctrl_common_probe,
- .driver = {
- .name = "mediatek-mt8167-pinctrl",
- .of_match_table = mt8167_pctrl_match,
- .pm = pm_sleep_ptr(&mtk_eint_pm_ops),
- },
-};
-
-static int __init mtk_pinctrl_init(void)
-{
- return platform_driver_register(&mtk_pinctrl_driver);
-}
-arch_initcall(mtk_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
index 68d6638e7f4b..e00b5633bc67 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
@@ -1,345 +1,517 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2019 MediaTek Inc.
* Author: Min.Guo <min.guo@mediatek.com>
+ * Author: Luca Leonardo Scorcia <l.scorcia@gmail.com>
*/
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <linux/of.h>
-#include <linux/module.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt8167.h"
#include "pinctrl-mtk-mt8516.h"
+#include "pinctrl-paris.h"
-static const struct mtk_drv_group_desc mt8516_drv_grp[] = {
- /* 0E4E8SR 4/8/12/16 */
- MTK_DRV_GRP(4, 16, 1, 2, 4),
- /* 0E2E4SR 2/4/6/8 */
- MTK_DRV_GRP(2, 8, 1, 2, 2),
- /* E8E4E2 2/4/6/8/10/12/14/16 */
- MTK_DRV_GRP(2, 16, 0, 2, 2)
-};
-
-static const struct mtk_pin_drv_grp mt8516_pin_drv[] = {
- MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
-
- MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
-
- MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
-
- MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
-
- MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
- MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
- MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
-
- MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
-
- MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
+#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 15, 0)
- MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
+#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, 0)
- MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
- MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
- MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
+#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, 1)
- MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
- MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
-
- MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
-
- MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
-
- MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
- MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
- MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
-
- MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
-
- MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
-
- MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
-
- MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
- MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
- MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
+static const struct mtk_pin_field_calc mt8516_pin_dir_range[] = {
+ PIN_FIELD16(0, 124, 0x000, 0x10, 0, 1),
+};
- MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
+static const struct mtk_pin_field_calc mt8516_pin_do_range[] = {
+ PIN_FIELD16(0, 124, 0x100, 0x10, 0, 1),
+};
- MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
+static const struct mtk_pin_field_calc mt8516_pin_di_range[] = {
+ PIN_FIELD16(0, 124, 0x200, 0x10, 0, 1),
+};
- MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
+static const struct mtk_pin_field_calc mt8516_pin_mode_range[] = {
+ PIN_FIELD15(0, 124, 0x300, 0x10, 0, 3),
+};
- MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
+static const struct mtk_pin_field_calc mt8516_pin_pullen_range[] = {
+ PIN_FIELD16(0, 124, 0x500, 0x10, 0, 1),
+};
- MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
+static const struct mtk_pin_field_calc mt8516_pin_pullsel_range[] = {
+ PIN_FIELD16(0, 124, 0x600, 0x10, 0, 1),
+};
- MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
+static const struct mtk_pin_field_calc mt8516_pin_ies_range[] = {
+ PINS_FIELD16(0, 6, 0x900, 0x10, 2, 1),
+ PINS_FIELD16(7, 10, 0x900, 0x10, 3, 1),
+ PINS_FIELD16(11, 13, 0x900, 0x10, 12, 1),
+ PINS_FIELD16(14, 17, 0x900, 0x10, 13, 1),
+ PINS_FIELD16(18, 20, 0x910, 0x10, 10, 1),
+ PINS_FIELD16(21, 23, 0x900, 0x10, 13, 1),
+ PINS_FIELD16(24, 25, 0x900, 0x10, 12, 1),
+ PINS_FIELD16(26, 30, 0x900, 0x10, 0, 1),
+ PINS_FIELD16(31, 33, 0x900, 0x10, 1, 1),
+ PINS_FIELD16(34, 39, 0x900, 0x10, 2, 1),
+ PIN_FIELD16(40, 40, 0x910, 0x10, 11, 1),
+ PINS_FIELD16(41, 43, 0x900, 0x10, 10, 1),
+ PINS_FIELD16(44, 47, 0x900, 0x10, 11, 1),
+ PINS_FIELD16(48, 51, 0x900, 0x10, 14, 1),
+ PINS_FIELD16(52, 53, 0x910, 0x10, 0, 1),
+ PIN_FIELD16(54, 54, 0x910, 0x10, 2, 1),
+ PINS_FIELD16(55, 57, 0x910, 0x10, 4, 1),
+ PINS_FIELD16(58, 59, 0x900, 0x10, 15, 1),
+ PINS_FIELD16(60, 61, 0x910, 0x10, 1, 1),
+ PINS_FIELD16(62, 65, 0x910, 0x10, 5, 1),
+ PINS_FIELD16(66, 67, 0x910, 0x10, 6, 1),
+ PIN_FIELD16(68, 68, 0x930, 0x10, 2, 1),
+ PIN_FIELD16(69, 69, 0x930, 0x10, 1, 1),
+ PIN_FIELD16(70, 70, 0x930, 0x10, 6, 1),
+ PIN_FIELD16(71, 71, 0x930, 0x10, 5, 1),
+ PIN_FIELD16(72, 72, 0x930, 0x10, 4, 1),
+ PIN_FIELD16(73, 73, 0x930, 0x10, 3, 1),
+ PINS_FIELD16(100, 103, 0x910, 0x10, 7, 1),
+ PIN_FIELD16(104, 104, 0x920, 0x10, 12, 1),
+ PIN_FIELD16(105, 105, 0x920, 0x10, 11, 1),
+ PIN_FIELD16(106, 106, 0x930, 0x10, 0, 1),
+ PIN_FIELD16(107, 107, 0x920, 0x10, 15, 1),
+ PIN_FIELD16(108, 108, 0x920, 0x10, 14, 1),
+ PIN_FIELD16(109, 109, 0x920, 0x10, 13, 1),
+ PIN_FIELD16(110, 110, 0x920, 0x10, 9, 1),
+ PIN_FIELD16(111, 111, 0x920, 0x10, 8, 1),
+ PIN_FIELD16(112, 112, 0x920, 0x10, 7, 1),
+ PIN_FIELD16(113, 113, 0x920, 0x10, 6, 1),
+ PIN_FIELD16(114, 114, 0x920, 0x10, 10, 1),
+ PIN_FIELD16(115, 115, 0x920, 0x10, 1, 1),
+ PIN_FIELD16(116, 116, 0x920, 0x10, 0, 1),
+ PIN_FIELD16(117, 117, 0x920, 0x10, 5, 1),
+ PIN_FIELD16(118, 118, 0x920, 0x10, 4, 1),
+ PIN_FIELD16(119, 119, 0x920, 0x10, 3, 1),
+ PIN_FIELD16(120, 120, 0x920, 0x10, 2, 1),
+ PINS_FIELD16(121, 124, 0x910, 0x10, 9, 1),
+};
- MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
+static const struct mtk_pin_field_calc mt8516_pin_smt_range[] = {
+ PINS_FIELD16(0, 6, 0xa00, 0x10, 2, 1),
+ PINS_FIELD16(7, 10, 0xa00, 0x10, 3, 1),
+ PINS_FIELD16(11, 13, 0xa00, 0x10, 12, 1),
+ PINS_FIELD16(14, 17, 0xa00, 0x10, 13, 1),
+ PINS_FIELD16(18, 20, 0xa10, 0x10, 10, 1),
+ PINS_FIELD16(21, 23, 0xa00, 0x10, 13, 1),
+ PINS_FIELD16(24, 25, 0xa00, 0x10, 12, 1),
+ PINS_FIELD16(26, 30, 0xa00, 0x10, 0, 1),
+ PINS_FIELD16(31, 33, 0xa00, 0x10, 1, 1),
+ PINS_FIELD16(34, 39, 0xa00, 0x10, 2, 1),
+ PIN_FIELD16(40, 40, 0xa10, 0x10, 11, 1),
+ PINS_FIELD16(41, 43, 0xa00, 0x10, 10, 1),
+ PINS_FIELD16(44, 47, 0xa00, 0x10, 11, 1),
+ PINS_FIELD16(48, 51, 0xa00, 0x10, 14, 1),
+ PINS_FIELD16(52, 53, 0xa10, 0x10, 0, 1),
+ PIN_FIELD16(54, 54, 0xa10, 0x10, 2, 1),
+ PINS_FIELD16(55, 57, 0xa10, 0x10, 4, 1),
+ PINS_FIELD16(58, 59, 0xa00, 0x10, 15, 1),
+ PINS_FIELD16(60, 61, 0xa10, 0x10, 1, 1),
+ PINS_FIELD16(62, 65, 0xa10, 0x10, 5, 1),
+ PINS_FIELD16(66, 67, 0xa10, 0x10, 6, 1),
+ PIN_FIELD16(68, 68, 0xa30, 0x10, 2, 1),
+ PIN_FIELD16(69, 69, 0xa30, 0x10, 1, 1),
+ PIN_FIELD16(70, 70, 0xa30, 0x10, 3, 1),
+ PIN_FIELD16(71, 71, 0xa30, 0x10, 4, 1),
+ PIN_FIELD16(72, 72, 0xa30, 0x10, 5, 1),
+ PIN_FIELD16(73, 73, 0xa30, 0x10, 6, 1),
+ PINS_FIELD16(100, 103, 0xa10, 0x10, 7, 1),
+ PIN_FIELD16(104, 104, 0xa20, 0x10, 12, 1),
+ PIN_FIELD16(105, 105, 0xa20, 0x10, 11, 1),
+ PIN_FIELD16(106, 106, 0xa20, 0x10, 13, 1),
+ PIN_FIELD16(107, 107, 0xa20, 0x10, 14, 1),
+ PIN_FIELD16(108, 108, 0xa20, 0x10, 15, 1),
+ PIN_FIELD16(109, 109, 0xa30, 0x10, 0, 1),
+ PIN_FIELD16(110, 110, 0xa20, 0x10, 9, 1),
+ PIN_FIELD16(111, 111, 0xa20, 0x10, 8, 1),
+ PIN_FIELD16(112, 112, 0xa20, 0x10, 7, 1),
+ PIN_FIELD16(113, 113, 0xa20, 0x10, 6, 1),
+ PIN_FIELD16(114, 114, 0xa20, 0x10, 10, 1),
+ PIN_FIELD16(115, 115, 0xa20, 0x10, 1, 1),
+ PIN_FIELD16(116, 116, 0xa20, 0x10, 0, 1),
+ PIN_FIELD16(117, 117, 0xa20, 0x10, 5, 1),
+ PIN_FIELD16(118, 118, 0xa20, 0x10, 4, 1),
+ PIN_FIELD16(119, 119, 0xa20, 0x10, 3, 1),
+ PIN_FIELD16(120, 120, 0xa20, 0x10, 2, 1),
+ PINS_FIELD16(121, 124, 0xa10, 0x10, 9, 1),
+};
- MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
+static const struct mtk_pin_field_calc mt8516_pin_pupd_range[] = {
+ /* EINT */
+ PIN_FIELD16(14, 14, 0xe50, 0x10, 14, 1), /* EINT14 */
+ PIN_FIELD16(15, 15, 0xe60, 0x10, 2, 1), /* EINT15 */
+ PIN_FIELD16(16, 16, 0xe60, 0x10, 6, 1), /* EINT16 */
+ PIN_FIELD16(17, 17, 0xe60, 0x10, 10, 1), /* EINT17 */
+ PIN_FIELD16(21, 21, 0xe60, 0x10, 14, 1), /* EINT21 */
+ PIN_FIELD16(22, 22, 0xe70, 0x10, 2, 1), /* EINT22 */
+ PIN_FIELD16(23, 23, 0xe70, 0x10, 6, 1), /* EINT23 */
+
+ /* KPROW */
+ PIN_FIELD16(40, 40, 0xe80, 0x10, 2, 1), /* KPROW0 */
+ PIN_FIELD16(41, 41, 0xe80, 0x10, 6, 1), /* KPROW1 */
+
+ PIN_FIELD16(42, 42, 0xe90, 0x10, 2, 1), /* KPCOL0 */
+ PIN_FIELD16(43, 43, 0xe90, 0x10, 6, 1), /* KPCOL1 */
+
+ /* MSDC2 */
+ PIN_FIELD16(68, 68, 0xe50, 0x10, 10, 1), /* MSDC2_CMD */
+ PIN_FIELD16(69, 69, 0xe50, 0x10, 6, 1), /* MSDC2_CLK */
+ PIN_FIELD16(70, 70, 0xe40, 0x10, 6, 1), /* MSDC2_DAT0 */
+ PIN_FIELD16(71, 71, 0xe40, 0x10, 10, 1), /* MSDC2_DAT1 */
+ PIN_FIELD16(72, 72, 0xe40, 0x10, 14, 1), /* MSDC2_DAT2 */
+ PIN_FIELD16(73, 73, 0xe50, 0x10, 2, 1), /* MSDC2_DAT3 */
+
+ /* MSDC1 */
+ PIN_FIELD16(104, 104, 0xe40, 0x10, 2, 1), /* MSDC1_CMD */
+ PIN_FIELD16(105, 105, 0xe30, 0x10, 14, 1), /* MSDC1_CLK */
+ PIN_FIELD16(106, 106, 0xe20, 0x10, 14, 1), /* MSDC1_DAT0 */
+ PIN_FIELD16(107, 107, 0xe30, 0x10, 2, 1), /* MSDC1_DAT1 */
+ PIN_FIELD16(108, 108, 0xe30, 0x10, 6, 1), /* MSDC1_DAT2 */
+ PIN_FIELD16(109, 109, 0xe30, 0x10, 10, 1), /* MSDC1_DAT3 */
+
+ /* MSDC0 */
+ PIN_FIELD16(110, 110, 0xe10, 0x10, 14, 1), /* MSDC0_DAT7 */
+ PIN_FIELD16(111, 111, 0xe10, 0x10, 10, 1), /* MSDC0_DAT6 */
+ PIN_FIELD16(112, 112, 0xe10, 0x10, 6, 1), /* MSDC0_DAT5 */
+ PIN_FIELD16(113, 113, 0xe10, 0x10, 2, 1), /* MSDC0_DAT4 */
+ PIN_FIELD16(114, 114, 0xe20, 0x10, 10, 1), /* MSDC0_RSTB */
+ PIN_FIELD16(115, 115, 0xe20, 0x10, 2, 1), /* MSDC0_CMD */
+ PIN_FIELD16(116, 116, 0xe20, 0x10, 6, 1), /* MSDC0_CLK */
+ PIN_FIELD16(117, 117, 0xe00, 0x10, 14, 1), /* MSDC0_DAT3 */
+ PIN_FIELD16(118, 118, 0xe00, 0x10, 10, 1), /* MSDC0_DAT2 */
+ PIN_FIELD16(119, 119, 0xe00, 0x10, 6, 1), /* MSDC0_DAT1 */
+ PIN_FIELD16(120, 120, 0xe00, 0x10, 2, 1), /* MSDC0_DAT0 */
+};
- MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
+static const struct mtk_pin_field_calc mt8516_pin_r0_range[] = {
+ /* EINT */
+ PIN_FIELD16(14, 14, 0xe50, 0x10, 12, 1), /* EINT14 */
+ PIN_FIELD16(15, 15, 0xe60, 0x10, 0, 1), /* EINT15 */
+ PIN_FIELD16(16, 16, 0xe60, 0x10, 4, 1), /* EINT16 */
+ PIN_FIELD16(17, 17, 0xe60, 0x10, 8, 1), /* EINT17 */
+ PIN_FIELD16(21, 21, 0xe60, 0x10, 12, 1), /* EINT21 */
+ PIN_FIELD16(22, 22, 0xe70, 0x10, 0, 1), /* EINT22 */
+ PIN_FIELD16(23, 23, 0xe70, 0x10, 4, 1), /* EINT23 */
+
+ /* KPROW */
+ PIN_FIELD16(40, 40, 0xe80, 0x10, 0, 1), /* KPROW0 */
+ PIN_FIELD16(41, 41, 0xe80, 0x10, 4, 1), /* KPROW1 */
+ PIN_FIELD16(42, 42, 0xe90, 0x10, 0, 1), /* KPCOL0 */
+ PIN_FIELD16(43, 43, 0xe90, 0x10, 4, 1), /* KPCOL1 */
+
+ /* MSDC2 */
+ PIN_FIELD16(68, 68, 0xe50, 0x10, 8, 1), /* MSDC2_CMD */
+ PIN_FIELD16(69, 69, 0xe50, 0x10, 4, 1), /* MSDC2_CLK */
+ PIN_FIELD16(70, 70, 0xe40, 0x10, 4, 1), /* MSDC2_DAT0 */
+ PIN_FIELD16(71, 71, 0xe40, 0x10, 8, 1), /* MSDC2_DAT1 */
+ PIN_FIELD16(72, 72, 0xe40, 0x10, 12, 1), /* MSDC2_DAT2 */
+ PIN_FIELD16(73, 73, 0xe50, 0x10, 0, 1), /* MSDC2_DAT3 */
+
+ /* MSDC1 */
+ PIN_FIELD16(104, 104, 0xe40, 0x10, 0, 1), /* MSDC1_CMD */
+ PIN_FIELD16(105, 105, 0xe30, 0x10, 12, 1), /* MSDC1_CLK */
+ PIN_FIELD16(106, 106, 0xe20, 0x10, 12, 1), /* MSDC1_DAT0 */
+ PIN_FIELD16(107, 107, 0xe30, 0x10, 0, 1), /* MSDC1_DAT1 */
+ PIN_FIELD16(108, 108, 0xe30, 0x10, 4, 1), /* MSDC1_DAT2 */
+ PIN_FIELD16(109, 109, 0xe30, 0x10, 8, 1), /* MSDC1_DAT3 */
+
+ /* MSDC0 */
+ PIN_FIELD16(110, 110, 0xe10, 0x10, 12, 1), /* MSDC0_DAT7 */
+ PIN_FIELD16(111, 111, 0xe10, 0x10, 8, 1), /* MSDC0_DAT6 */
+ PIN_FIELD16(112, 112, 0xe10, 0x10, 4, 1), /* MSDC0_DAT5 */
+ PIN_FIELD16(113, 113, 0xe10, 0x10, 0, 1), /* MSDC0_DAT4 */
+ PIN_FIELD16(114, 114, 0xe20, 0x10, 8, 1), /* MSDC0_RSTB */
+ PIN_FIELD16(115, 115, 0xe20, 0x10, 0, 1), /* MSDC0_CMD */
+ PIN_FIELD16(116, 116, 0xe20, 0x10, 4, 1), /* MSDC0_CLK */
+ PIN_FIELD16(117, 117, 0xe00, 0x10, 12, 1), /* MSDC0_DAT3 */
+ PIN_FIELD16(118, 118, 0xe00, 0x10, 8, 1), /* MSDC0_DAT2 */
+ PIN_FIELD16(119, 119, 0xe00, 0x10, 4, 1), /* MSDC0_DAT1 */
+ PIN_FIELD16(120, 120, 0xe00, 0x10, 0, 1), /* MSDC0_DAT0 */
+};
- MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
+static const struct mtk_pin_field_calc mt8516_pin_r1_range[] = {
+ /* EINT */
+ PIN_FIELD16(14, 14, 0xe50, 0x10, 13, 1), /* EINT14 */
+ PIN_FIELD16(15, 15, 0xe60, 0x10, 1, 1), /* EINT15 */
+ PIN_FIELD16(16, 16, 0xe60, 0x10, 5, 1), /* EINT16 */
+ PIN_FIELD16(17, 17, 0xe60, 0x10, 9, 1), /* EINT17 */
+ PIN_FIELD16(21, 21, 0xe60, 0x10, 13, 1), /* EINT21 */
+ PIN_FIELD16(22, 22, 0xe70, 0x10, 1, 1), /* EINT22 */
+ PIN_FIELD16(23, 23, 0xe70, 0x10, 5, 1), /* EINT23 */
+
+ /* KPROW */
+ PIN_FIELD16(40, 40, 0xe80, 0x10, 1, 1), /* KPROW0 */
+ PIN_FIELD16(41, 41, 0xe80, 0x10, 5, 1), /* KPROW1 */
+ PIN_FIELD16(42, 42, 0xe90, 0x10, 1, 1), /* KPCOL0 */
+ PIN_FIELD16(43, 43, 0xe90, 0x10, 5, 1), /* KPCOL1 */
+
+ /* MSDC2 */
+ PIN_FIELD16(68, 68, 0xe50, 0x10, 9, 1), /* MSDC2_CMD */
+ PIN_FIELD16(69, 69, 0xe50, 0x10, 5, 1), /* MSDC2_CLK */
+ PIN_FIELD16(70, 70, 0xe40, 0x10, 5, 1), /* MSDC2_DAT0 */
+ PIN_FIELD16(71, 71, 0xe40, 0x10, 9, 1), /* MSDC2_DAT1 */
+ PIN_FIELD16(72, 72, 0xe40, 0x10, 13, 1), /* MSDC2_DAT2 */
+ PIN_FIELD16(73, 73, 0xe50, 0x10, 1, 1), /* MSDC2_DAT3 */
+
+ /* MSDC1 */
+ PIN_FIELD16(104, 104, 0xe40, 0x10, 1, 1), /* MSDC1_CMD */
+ PIN_FIELD16(105, 105, 0xe30, 0x10, 13, 1), /* MSDC1_CLK */
+ PIN_FIELD16(106, 106, 0xe20, 0x10, 13, 1), /* MSDC1_DAT0 */
+ PIN_FIELD16(107, 107, 0xe30, 0x10, 1, 1), /* MSDC1_DAT1 */
+ PIN_FIELD16(108, 108, 0xe30, 0x10, 5, 1), /* MSDC1_DAT2 */
+ PIN_FIELD16(109, 109, 0xe30, 0x10, 9, 1), /* MSDC1_DAT3 */
+
+ /* MSDC0 */
+ PIN_FIELD16(110, 110, 0xe10, 0x10, 13, 1), /* MSDC0_DAT7 */
+ PIN_FIELD16(111, 111, 0xe10, 0x10, 9, 1), /* MSDC0_DAT6 */
+ PIN_FIELD16(112, 112, 0xe10, 0x10, 5, 1), /* MSDC0_DAT5 */
+ PIN_FIELD16(113, 113, 0xe10, 0x10, 1, 1), /* MSDC0_DAT4 */
+ PIN_FIELD16(114, 114, 0xe20, 0x10, 9, 1), /* MSDC0_RSTB */
+ PIN_FIELD16(115, 115, 0xe20, 0x10, 1, 1), /* MSDC0_CMD */
+ PIN_FIELD16(116, 116, 0xe20, 0x10, 5, 1), /* MSDC0_CLK */
+ PIN_FIELD16(117, 117, 0xe00, 0x10, 13, 1), /* MSDC0_DAT3 */
+ PIN_FIELD16(118, 118, 0xe00, 0x10, 9, 1), /* MSDC0_DAT2 */
+ PIN_FIELD16(119, 119, 0xe00, 0x10, 5, 1), /* MSDC0_DAT1 */
+ PIN_FIELD16(120, 120, 0xe00, 0x10, 1, 1), /* MSDC0_DAT0 */
+};
- MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
+static const struct mtk_pin_field_calc mt8516_pin_drv_range[] = {
+ PINS_FIELD16(0, 4, 0xd00, 0x10, 0, 2),
+ PINS_FIELD16(5, 10, 0xd00, 0x10, 4, 2),
+ PINS_FIELD16(11, 13, 0xd00, 0x10, 8, 2),
+ PINS_FIELD16(14, 17, 0xd00, 0x10, 12, 2),
+ PINS_FIELD16(18, 20, 0xd10, 0x10, 0, 2),
+ PINS_FIELD16(21, 23, 0xd00, 0x10, 12, 2),
+ PINS_FIELD16(24, 25, 0xd00, 0x10, 8, 2),
+ PINS_FIELD16(26, 30, 0xd10, 0x10, 4, 2),
+ PINS_FIELD16(31, 33, 0xd10, 0x10, 8, 2),
+ PINS_FIELD16(34, 35, 0xd10, 0x10, 12, 2),
+ PINS_FIELD16(36, 39, 0xd20, 0x10, 0, 2),
+ PIN_FIELD16(40, 40, 0xd20, 0x10, 4, 2),
+ PINS_FIELD16(41, 43, 0xd20, 0x10, 8, 2),
+ PINS_FIELD16(44, 47, 0xd20, 0x10, 12, 2),
+ PINS_FIELD16(48, 51, 0xd30, 0x10, 12, 2),
+
+ PIN_FIELD16(54, 54, 0xd30, 0x10, 8, 2),
+ PINS_FIELD16(55, 57, 0xd30, 0x10, 0, 2),
+
+ PINS_FIELD16(62, 67, 0xd40, 0x10, 8, 2),
+ PIN_FIELD16(68, 68, 0xd40, 0x10, 12, 2),
+ PIN_FIELD16(69, 69, 0xd50, 0x10, 0, 2),
+ PINS_FIELD16(70, 73, 0xd50, 0x10, 4, 2),
+
+ PINS_FIELD16(100, 103, 0xd50, 0x10, 8, 2),
+ PIN_FIELD16(104, 104, 0xd50, 0x10, 12, 2),
+ PIN_FIELD16(105, 105, 0xd60, 0x10, 0, 2),
+ PINS_FIELD16(106, 109, 0xd60, 0x10, 4, 2),
+ PINS_FIELD16(110, 113, 0xd70, 0x10, 0, 2),
+ PIN_FIELD16(114, 114, 0xd70, 0x10, 4, 2),
+ PIN_FIELD16(115, 115, 0xd60, 0x10, 12, 2),
+ PIN_FIELD16(116, 116, 0xd60, 0x10, 8, 2),
+ PINS_FIELD16(117, 120, 0xd70, 0x10, 0, 2),
+};
- MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
+static const struct mtk_pin_field_calc mt8516_pin_sr_range[] = {
+ PINS_FIELD16(0, 4, 0xd00, 0x10, 3, 1),
+ PINS_FIELD16(5, 10, 0xd00, 0x10, 7, 1),
+ PINS_FIELD16(11, 13, 0xd00, 0x10, 11, 1),
+ PINS_FIELD16(14, 17, 0xd00, 0x10, 15, 1),
+ PINS_FIELD16(18, 20, 0xd10, 0x10, 3, 1),
+ PINS_FIELD16(21, 23, 0xd00, 0x10, 15, 1),
+ PINS_FIELD16(24, 25, 0xd00, 0x10, 11, 1),
+ PINS_FIELD16(26, 30, 0xd10, 0x10, 7, 1),
+ PINS_FIELD16(31, 33, 0xd10, 0x10, 11, 1),
+ PINS_FIELD16(34, 35, 0xd10, 0x10, 15, 1),
+ PINS_FIELD16(36, 39, 0xd20, 0x10, 3, 1),
+ PIN_FIELD16(40, 40, 0xd20, 0x10, 7, 1),
+ PINS_FIELD16(41, 43, 0xd20, 0x10, 11, 1),
+ PINS_FIELD16(44, 47, 0xd20, 0x10, 15, 1),
+ PINS_FIELD16(48, 51, 0xd30, 0x10, 15, 1),
+
+ PIN_FIELD16(54, 54, 0xd30, 0x10, 11, 1),
+ PINS_FIELD16(55, 57, 0xd30, 0x10, 3, 1),
+
+ PINS_FIELD16(62, 67, 0xd40, 0x10, 11, 1),
+ PIN_FIELD16(68, 68, 0xd40, 0x10, 15, 1),
+ PIN_FIELD16(69, 69, 0xd50, 0x10, 3, 1),
+ PINS_FIELD16(70, 73, 0xd50, 0x10, 7, 1),
+
+ PINS_FIELD16(100, 103, 0xd50, 0x10, 11, 1),
+ PIN_FIELD16(104, 104, 0xd50, 0x10, 15, 1),
+ PIN_FIELD16(105, 105, 0xd60, 0x10, 3, 1),
+ PINS_FIELD16(106, 109, 0xd60, 0x10, 7, 1),
+ PINS_FIELD16(110, 113, 0xd70, 0x10, 3, 1),
+ PIN_FIELD16(114, 114, 0xd70, 0x10, 7, 1),
+ PIN_FIELD16(115, 115, 0xd60, 0x10, 15, 1),
+ PIN_FIELD16(116, 116, 0xd60, 0x10, 11, 1),
+ PINS_FIELD16(117, 120, 0xd70, 0x10, 3, 1),
+};
- MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
+static const struct mtk_pin_reg_calc mt8516_reg_cals[PINCTRL_PIN_REG_MAX] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8516_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8516_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8516_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8516_pin_do_range),
+ [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8516_pin_sr_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8516_pin_smt_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8516_pin_drv_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8516_pin_pupd_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8516_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8516_pin_r1_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8516_pin_ies_range),
+ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8516_pin_pullen_range),
+ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8516_pin_pullsel_range),
};
-static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = {
- MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
-
- MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
-
- MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
-
- MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
-
- MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
+static const struct mtk_eint_hw mt8516_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num = 169,
+ .db_cnt = 64,
+ .db_time = debounce_time_mt6795,
};
-static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
- MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
- MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
- MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
- MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
- MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
- MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
- MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
- MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
- MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
- MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
- MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
- MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
- MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
- MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
- MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
- MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
- MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
- MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
- MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
- MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
- MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
- MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
- MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
- MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
- MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
- MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
- MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
- MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
- MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
- MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
- MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
- MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
- MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
- MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
- MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
- MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
- MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
- MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
- MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
- MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
- MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
- MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
- MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
- MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
- MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
+static const unsigned int mt8516_pull_type[] = {
+ MTK_PULL_PULLSEL_TYPE,/*0*/ MTK_PULL_PULLSEL_TYPE,/*1*/
+ MTK_PULL_PULLSEL_TYPE,/*2*/ MTK_PULL_PULLSEL_TYPE,/*3*/
+ MTK_PULL_PULLSEL_TYPE,/*4*/ MTK_PULL_PULLSEL_TYPE,/*5*/
+ MTK_PULL_PULLSEL_TYPE,/*6*/ MTK_PULL_PULLSEL_TYPE,/*7*/
+ MTK_PULL_PULLSEL_TYPE,/*8*/ MTK_PULL_PULLSEL_TYPE,/*9*/
+ MTK_PULL_PULLSEL_TYPE,/*10*/ MTK_PULL_PULLSEL_TYPE,/*11*/
+ MTK_PULL_PULLSEL_TYPE,/*12*/ MTK_PULL_PULLSEL_TYPE,/*13*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
+ MTK_PULL_PULLSEL_TYPE,/*18*/ MTK_PULL_PULLSEL_TYPE,/*19*/
+ MTK_PULL_PULLSEL_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
+ MTK_PULL_PULLSEL_TYPE,/*24*/ MTK_PULL_PULLSEL_TYPE,/*25*/
+ MTK_PULL_PULLSEL_TYPE,/*26*/ MTK_PULL_PULLSEL_TYPE,/*27*/
+ MTK_PULL_PULLSEL_TYPE,/*28*/ MTK_PULL_PULLSEL_TYPE,/*29*/
+ MTK_PULL_PULLSEL_TYPE,/*30*/ MTK_PULL_PULLSEL_TYPE,/*31*/
+ MTK_PULL_PULLSEL_TYPE,/*32*/ MTK_PULL_PULLSEL_TYPE,/*33*/
+ MTK_PULL_PULLSEL_TYPE,/*34*/ MTK_PULL_PULLSEL_TYPE,/*35*/
+ MTK_PULL_PULLSEL_TYPE,/*36*/ MTK_PULL_PULLSEL_TYPE,/*37*/
+ MTK_PULL_PULLSEL_TYPE,/*38*/ MTK_PULL_PULLSEL_TYPE,/*39*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
+ MTK_PULL_PULLSEL_TYPE,/*44*/ MTK_PULL_PULLSEL_TYPE,/*45*/
+ MTK_PULL_PULLSEL_TYPE,/*46*/ MTK_PULL_PULLSEL_TYPE,/*47*/
+ MTK_PULL_PULLSEL_TYPE,/*48*/ MTK_PULL_PULLSEL_TYPE,/*49*/
+ MTK_PULL_PULLSEL_TYPE,/*50*/ MTK_PULL_PULLSEL_TYPE,/*51*/
+ MTK_PULL_PULLSEL_TYPE,/*52*/ MTK_PULL_PULLSEL_TYPE,/*53*/
+ MTK_PULL_PULLSEL_TYPE,/*54*/ MTK_PULL_PULLSEL_TYPE,/*55*/
+ MTK_PULL_PULLSEL_TYPE,/*56*/ MTK_PULL_PULLSEL_TYPE,/*57*/
+ MTK_PULL_PULLSEL_TYPE,/*58*/ MTK_PULL_PULLSEL_TYPE,/*59*/
+ MTK_PULL_PULLSEL_TYPE,/*60*/ MTK_PULL_PULLSEL_TYPE,/*61*/
+ MTK_PULL_PULLSEL_TYPE,/*62*/ MTK_PULL_PULLSEL_TYPE,/*63*/
+ MTK_PULL_PULLSEL_TYPE,/*64*/ MTK_PULL_PULLSEL_TYPE,/*65*/
+ MTK_PULL_PULLSEL_TYPE,/*66*/ MTK_PULL_PULLSEL_TYPE,/*67*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PUPD_R1R0_TYPE,/*71*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
+ MTK_PULL_PULLSEL_TYPE,/*74*/ MTK_PULL_PULLSEL_TYPE,/*75*/
+ MTK_PULL_PULLSEL_TYPE,/*76*/ MTK_PULL_PULLSEL_TYPE,/*77*/
+ MTK_PULL_PULLSEL_TYPE,/*78*/ MTK_PULL_PULLSEL_TYPE,/*79*/
+ MTK_PULL_PULLSEL_TYPE,/*80*/ MTK_PULL_PULLSEL_TYPE,/*81*/
+ MTK_PULL_PULLSEL_TYPE,/*82*/ MTK_PULL_PULLSEL_TYPE,/*83*/
+ MTK_PULL_PULLSEL_TYPE,/*84*/ MTK_PULL_PULLSEL_TYPE,/*85*/
+ MTK_PULL_PULLSEL_TYPE,/*86*/ MTK_PULL_PULLSEL_TYPE,/*87*/
+ MTK_PULL_PULLSEL_TYPE,/*88*/ MTK_PULL_PULLSEL_TYPE,/*89*/
+ MTK_PULL_PULLSEL_TYPE,/*90*/ MTK_PULL_PULLSEL_TYPE,/*91*/
+ MTK_PULL_PULLSEL_TYPE,/*92*/ MTK_PULL_PULLSEL_TYPE,/*93*/
+ MTK_PULL_PULLSEL_TYPE,/*94*/ MTK_PULL_PULLSEL_TYPE,/*95*/
+ MTK_PULL_PULLSEL_TYPE,/*96*/ MTK_PULL_PULLSEL_TYPE,/*97*/
+ MTK_PULL_PULLSEL_TYPE,/*98*/ MTK_PULL_PULLSEL_TYPE,/*99*/
+ MTK_PULL_PULLSEL_TYPE,/*100*/ MTK_PULL_PULLSEL_TYPE,/*101*/
+ MTK_PULL_PULLSEL_TYPE,/*102*/ MTK_PULL_PULLSEL_TYPE,/*103*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*104*/ MTK_PULL_PUPD_R1R0_TYPE,/*105*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*106*/ MTK_PULL_PUPD_R1R0_TYPE,/*107*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*108*/ MTK_PULL_PUPD_R1R0_TYPE,/*109*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*110*/ MTK_PULL_PUPD_R1R0_TYPE,/*111*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*112*/ MTK_PULL_PUPD_R1R0_TYPE,/*113*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*114*/ MTK_PULL_PUPD_R1R0_TYPE,/*115*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*116*/ MTK_PULL_PUPD_R1R0_TYPE,/*117*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*118*/ MTK_PULL_PUPD_R1R0_TYPE,/*119*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*120*/ MTK_PULL_PULLSEL_TYPE,/*121*/
+ MTK_PULL_PULLSEL_TYPE,/*122*/ MTK_PULL_PULLSEL_TYPE,/*123*/
+ MTK_PULL_PULLSEL_TYPE,/*124*/
};
-static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
- MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
- MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
- MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
- MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
- MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
- MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
- MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
- MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
- MTK_PIN_IES_SMT_SPEC(34, 39, 0xA00, 2),
- MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
- MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
- MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
- MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
- MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
- MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
- MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
- MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
- MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
- MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
- MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
- MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
- MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
- MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
- MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
- MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
- MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
-
- MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
- MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
- MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
- MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
- MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
- MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
- MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
- MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
- MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
- MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
- MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
- MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
- MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
- MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
- MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
- MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
- MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
- MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
- MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
+static const struct mtk_pin_soc mt8167_pinctrl_data = {
+ .reg_cal = mt8516_reg_cals,
+ .pins = mtk_pins_mt8167,
+ .npins = ARRAY_SIZE(mtk_pins_mt8167),
+ .ngrps = ARRAY_SIZE(mtk_pins_mt8167),
+ .nfuncs = 8,
+ .eint_hw = &mt8516_eint_hw,
+ .gpio_m = 0,
+ .ies_present = true,
+ .base_names = mtk_default_register_base_names,
+ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
+ .pull_type = mt8516_pull_type,
+ .bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
+ .bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
+ .bias_set = mtk_pinconf_bias_set_rev1,
+ .bias_get = mtk_pinconf_bias_get_rev1,
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
};
-static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
+static const struct mtk_pin_soc mt8516_pinctrl_data = {
+ .reg_cal = mt8516_reg_cals,
.pins = mtk_pins_mt8516,
.npins = ARRAY_SIZE(mtk_pins_mt8516),
- .grp_desc = mt8516_drv_grp,
- .n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
- .pin_drv_grp = mt8516_pin_drv,
- .n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
- .spec_ies = mt8516_ies_set,
- .n_spec_ies = ARRAY_SIZE(mt8516_ies_set),
- .spec_pupd = mt8516_spec_pupd,
- .n_spec_pupd = ARRAY_SIZE(mt8516_spec_pupd),
- .spec_smt = mt8516_smt_set,
- .n_spec_smt = ARRAY_SIZE(mt8516_smt_set),
- .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
- .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
- .dir_offset = 0x0000,
- .pullen_offset = 0x0500,
- .pullsel_offset = 0x0600,
- .dout_offset = 0x0100,
- .din_offset = 0x0200,
- .pinmux_offset = 0x0300,
- .type1_start = 125,
- .type1_end = 125,
- .port_shf = 4,
- .port_mask = 0xf,
- .port_align = 4,
- .mode_mask = 0xf,
- .mode_per_reg = 5,
- .mode_shf = 4,
- .eint_hw = {
- .port_mask = 7,
- .ports = 6,
- .ap_num = 169,
- .db_cnt = 64,
- .db_time = debounce_time_mt6795,
- },
+ .ngrps = ARRAY_SIZE(mtk_pins_mt8516),
+ .nfuncs = 8,
+ .eint_hw = &mt8516_eint_hw,
+ .gpio_m = 0,
+ .ies_present = true,
+ .base_names = mtk_default_register_base_names,
+ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
+ .pull_type = mt8516_pull_type,
+ .bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
+ .bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
+ .bias_set = mtk_pinconf_bias_set_rev1,
+ .bias_get = mtk_pinconf_bias_get_rev1,
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
};
-static const struct of_device_id mt8516_pctrl_match[] = {
+static const struct of_device_id mt8516_pinctrl_of_match[] = {
+ { .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data },
{ .compatible = "mediatek,mt8516-pinctrl", .data = &mt8516_pinctrl_data },
{}
};
+MODULE_DEVICE_TABLE(of, mt8516_pinctrl_of_match);
-MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
-
-static struct platform_driver mtk_pinctrl_driver = {
- .probe = mtk_pctrl_common_probe,
+static struct platform_driver mt8516_pinctrl_driver = {
.driver = {
.name = "mediatek-mt8516-pinctrl",
- .of_match_table = mt8516_pctrl_match,
- .pm = pm_sleep_ptr(&mtk_eint_pm_ops),
+ .of_match_table = mt8516_pinctrl_of_match,
+ .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops),
},
+ .probe = mtk_paris_pinctrl_probe,
};
-static int __init mtk_pinctrl_init(void)
+static int __init mt8516_pinctrl_init(void)
{
- return platform_driver_register(&mtk_pinctrl_driver);
+ return platform_driver_register(&mt8516_pinctrl_driver);
}
-arch_initcall(mtk_pinctrl_init);
+arch_initcall(mt8516_pinctrl_init);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek MT8516/MT8167 Pinctrl Driver");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h
index 225c41fc9b75..d0c603838644 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h
@@ -1,18 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2020 MediaTek Inc.
- */
#ifndef __PINCTRL_MTK_MT8167_H
#define __PINCTRL_MTK_MT8167_H
-#include <linux/pinctrl/pinctrl.h>
-#include "pinctrl-mtk-common.h"
+#include "pinctrl-paris.h"
-static const struct mtk_desc_pin mtk_pins_mt8167[] = {
+static const struct mtk_pin_desc mtk_pins_mt8167[] = {
MTK_PIN(
- PINCTRL_PIN(0, "EINT0"),
- NULL, "mt8167",
+ 0, "EINT0",
MTK_EINT_FUNCTION(0, 0),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO0"),
MTK_FUNCTION(1, "PWM_B"),
MTK_FUNCTION(2, "DPI_CK"),
@@ -22,9 +18,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[6]")
),
MTK_PIN(
- PINCTRL_PIN(1, "EINT1"),
- NULL, "mt8167",
+ 1, "EINT1",
MTK_EINT_FUNCTION(0, 1),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO1"),
MTK_FUNCTION(1, "PWM_C"),
MTK_FUNCTION(2, "DPI_D12"),
@@ -35,9 +31,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[7]")
),
MTK_PIN(
- PINCTRL_PIN(2, "EINT2"),
- NULL, "mt8167",
+ 2, "EINT2",
MTK_EINT_FUNCTION(0, 2),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO2"),
MTK_FUNCTION(1, "CLKM0"),
MTK_FUNCTION(2, "DPI_D13"),
@@ -48,9 +44,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[8]")
),
MTK_PIN(
- PINCTRL_PIN(3, "EINT3"),
- NULL, "mt8167",
+ 3, "EINT3",
MTK_EINT_FUNCTION(0, 3),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO3"),
MTK_FUNCTION(1, "CLKM1"),
MTK_FUNCTION(2, "DPI_D14"),
@@ -61,9 +57,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[9]")
),
MTK_PIN(
- PINCTRL_PIN(4, "EINT4"),
- NULL, "mt8167",
+ 4, "EINT4",
MTK_EINT_FUNCTION(0, 4),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO4"),
MTK_FUNCTION(1, "CLKM2"),
MTK_FUNCTION(2, "DPI_D15"),
@@ -74,9 +70,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[10]")
),
MTK_PIN(
- PINCTRL_PIN(5, "EINT5"),
- NULL, "mt8167",
+ 5, "EINT5",
MTK_EINT_FUNCTION(0, 5),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO5"),
MTK_FUNCTION(1, "UCTS2"),
MTK_FUNCTION(2, "DPI_D16"),
@@ -87,9 +83,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[11]")
),
MTK_PIN(
- PINCTRL_PIN(6, "EINT6"),
- NULL, "mt8167",
+ 6, "EINT6",
MTK_EINT_FUNCTION(0, 6),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO6"),
MTK_FUNCTION(1, "URTS2"),
MTK_FUNCTION(2, "DPI_D17"),
@@ -100,9 +96,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[12]")
),
MTK_PIN(
- PINCTRL_PIN(7, "EINT7"),
- NULL, "mt8167",
+ 7, "EINT7",
MTK_EINT_FUNCTION(0, 7),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO7"),
MTK_FUNCTION(1, "SQIRST"),
MTK_FUNCTION(2, "DPI_D6"),
@@ -113,9 +109,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[13]")
),
MTK_PIN(
- PINCTRL_PIN(8, "EINT8"),
- NULL, "mt8167",
+ 8, "EINT8",
MTK_EINT_FUNCTION(0, 8),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO8"),
MTK_FUNCTION(1, "SQICK"),
MTK_FUNCTION(2, "CLKM3"),
@@ -126,9 +122,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[14]")
),
MTK_PIN(
- PINCTRL_PIN(9, "EINT9"),
- NULL, "mt8167",
+ 9, "EINT9",
MTK_EINT_FUNCTION(0, 9),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO9"),
MTK_FUNCTION(1, "CLKM4"),
MTK_FUNCTION(2, "SDA2_0"),
@@ -139,9 +135,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[15]")
),
MTK_PIN(
- PINCTRL_PIN(10, "EINT10"),
- NULL, "mt8167",
+ 10, "EINT10",
MTK_EINT_FUNCTION(0, 10),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO10"),
MTK_FUNCTION(1, "CLKM5"),
MTK_FUNCTION(2, "SCL2_0"),
@@ -152,9 +148,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[16]")
),
MTK_PIN(
- PINCTRL_PIN(11, "EINT11"),
- NULL, "mt8167",
+ 11, "EINT11",
MTK_EINT_FUNCTION(0, 11),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO11"),
MTK_FUNCTION(1, "CLKM4"),
MTK_FUNCTION(2, "PWM_C"),
@@ -165,9 +161,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[17]")
),
MTK_PIN(
- PINCTRL_PIN(12, "EINT12"),
- NULL, "mt8167",
+ 12, "EINT12",
MTK_EINT_FUNCTION(0, 12),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO12"),
MTK_FUNCTION(1, "CLKM5"),
MTK_FUNCTION(2, "PWM_A"),
@@ -178,9 +174,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[18]")
),
MTK_PIN(
- PINCTRL_PIN(13, "EINT13"),
- NULL, "mt8167",
+ 13, "EINT13",
MTK_EINT_FUNCTION(0, 13),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO13"),
MTK_FUNCTION(3, "TSF_IN"),
MTK_FUNCTION(4, "ANT_SEL5"),
@@ -189,9 +185,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[19]")
),
MTK_PIN(
- PINCTRL_PIN(14, "EINT14"),
- NULL, "mt8167",
+ 14, "EINT14",
MTK_EINT_FUNCTION(0, 14),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO14"),
MTK_FUNCTION(2, "I2S_8CH_DO1"),
MTK_FUNCTION(3, "TDM_RX_MCK"),
@@ -201,9 +197,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[8]")
),
MTK_PIN(
- PINCTRL_PIN(15, "EINT15"),
- NULL, "mt8167",
+ 15, "EINT15",
MTK_EINT_FUNCTION(0, 15),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO15"),
MTK_FUNCTION(2, "I2S_8CH_LRCK"),
MTK_FUNCTION(3, "TDM_RX_BCK"),
@@ -213,9 +209,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[9]")
),
MTK_PIN(
- PINCTRL_PIN(16, "EINT16"),
- NULL, "mt8167",
+ 16, "EINT16",
MTK_EINT_FUNCTION(0, 16),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO16"),
MTK_FUNCTION(2, "I2S_8CH_BCK"),
MTK_FUNCTION(3, "TDM_RX_LRCK"),
@@ -225,9 +221,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[10]")
),
MTK_PIN(
- PINCTRL_PIN(17, "EINT17"),
- NULL, "mt8167",
+ 17, "EINT17",
MTK_EINT_FUNCTION(0, 17),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO17"),
MTK_FUNCTION(2, "I2S_8CH_MCK"),
MTK_FUNCTION(3, "TDM_RX_DI"),
@@ -237,9 +233,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[11]")
),
MTK_PIN(
- PINCTRL_PIN(18, "EINT18"),
- NULL, "mt8167",
+ 18, "EINT18",
MTK_EINT_FUNCTION(0, 18),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO18"),
MTK_FUNCTION(2, "USB_DRVVBUS"),
MTK_FUNCTION(3, "I2S3_LRCK"),
@@ -249,9 +245,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[20]")
),
MTK_PIN(
- PINCTRL_PIN(19, "EINT19"),
- NULL, "mt8167",
+ 19, "EINT19",
MTK_EINT_FUNCTION(0, 19),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO19"),
MTK_FUNCTION(1, "UCTS1"),
MTK_FUNCTION(2, "IDDIG"),
@@ -262,9 +258,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[21]")
),
MTK_PIN(
- PINCTRL_PIN(20, "EINT20"),
- NULL, "mt8167",
+ 20, "EINT20",
MTK_EINT_FUNCTION(0, 20),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO20"),
MTK_FUNCTION(1, "URTS1"),
MTK_FUNCTION(3, "I2S3_DO"),
@@ -274,9 +270,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[22]")
),
MTK_PIN(
- PINCTRL_PIN(21, "EINT21"),
- NULL, "mt8167",
+ 21, "EINT21",
MTK_EINT_FUNCTION(0, 21),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO21"),
MTK_FUNCTION(1, "NRNB"),
MTK_FUNCTION(2, "ANT_SEL0"),
@@ -284,9 +280,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[31]")
),
MTK_PIN(
- PINCTRL_PIN(22, "EINT22"),
- NULL, "mt8167",
+ 22, "EINT22",
MTK_EINT_FUNCTION(0, 22),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO22"),
MTK_FUNCTION(2, "I2S_8CH_DO2"),
MTK_FUNCTION(3, "TSF_IN"),
@@ -296,9 +292,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[12]")
),
MTK_PIN(
- PINCTRL_PIN(23, "EINT23"),
- NULL, "mt8167",
+ 23, "EINT23",
MTK_EINT_FUNCTION(0, 23),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO23"),
MTK_FUNCTION(2, "I2S_8CH_DO3"),
MTK_FUNCTION(3, "CLKM0"),
@@ -308,9 +304,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[13]")
),
MTK_PIN(
- PINCTRL_PIN(24, "EINT24"),
- NULL, "mt8167",
+ 24, "EINT24",
MTK_EINT_FUNCTION(0, 24),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO24"),
MTK_FUNCTION(1, "DPI_D20"),
MTK_FUNCTION(2, "DPI_DE"),
@@ -321,9 +317,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[0]")
),
MTK_PIN(
- PINCTRL_PIN(25, "EINT25"),
- NULL, "mt8167",
+ 25, "EINT25",
MTK_EINT_FUNCTION(0, 25),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO25"),
MTK_FUNCTION(1, "DPI_D19"),
MTK_FUNCTION(2, "DPI_VSYNC"),
@@ -334,25 +330,25 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[1]")
),
MTK_PIN(
- PINCTRL_PIN(26, "PWRAP_SPI0_MI"),
- NULL, "mt8167",
+ 26, "PWRAP_SPI0_MI",
MTK_EINT_FUNCTION(0, 26),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO26"),
MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
MTK_FUNCTION(2, "PWRAP_SPI0_MI")
),
MTK_PIN(
- PINCTRL_PIN(27, "PWRAP_SPI0_MO"),
- NULL, "mt8167",
+ 27, "PWRAP_SPI0_MO",
MTK_EINT_FUNCTION(0, 27),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO27"),
MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
MTK_FUNCTION(2, "PWRAP_SPI0_MO")
),
MTK_PIN(
- PINCTRL_PIN(28, "PWRAP_INT"),
- NULL, "mt8167",
+ 28, "PWRAP_INT",
MTK_EINT_FUNCTION(0, 28),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO28"),
MTK_FUNCTION(1, "I2S0_MCK"),
MTK_FUNCTION(4, "I2S_8CH_MCK"),
@@ -360,44 +356,44 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(6, "I2S3_MCK")
),
MTK_PIN(
- PINCTRL_PIN(29, "PWRAP_SPI0_CK"),
- NULL, "mt8167",
+ 29, "PWRAP_SPI0_CK",
MTK_EINT_FUNCTION(0, 29),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO29"),
MTK_FUNCTION(1, "PWRAP_SPI0_CK")
),
MTK_PIN(
- PINCTRL_PIN(30, "PWRAP_SPI0_CSN"),
- NULL, "mt8167",
+ 30, "PWRAP_SPI0_CSN",
MTK_EINT_FUNCTION(0, 30),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO30"),
MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
),
MTK_PIN(
- PINCTRL_PIN(31, "RTC32K_CK"),
- NULL, "mt8167",
+ 31, "RTC32K_CK",
MTK_EINT_FUNCTION(0, 31),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO31"),
MTK_FUNCTION(1, "RTC32K_CK")
),
MTK_PIN(
- PINCTRL_PIN(32, "WATCHDOG"),
- NULL, "mt8167",
+ 32, "WATCHDOG",
MTK_EINT_FUNCTION(0, 32),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO32"),
MTK_FUNCTION(1, "WATCHDOG")
),
MTK_PIN(
- PINCTRL_PIN(33, "SRCLKENA"),
- NULL, "mt8167",
+ 33, "SRCLKENA",
MTK_EINT_FUNCTION(0, 33),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO33"),
MTK_FUNCTION(1, "SRCLKENA0")
),
MTK_PIN(
- PINCTRL_PIN(34, "URXD2"),
- NULL, "mt8167",
+ 34, "URXD2",
MTK_EINT_FUNCTION(0, 34),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO34"),
MTK_FUNCTION(1, "URXD2"),
MTK_FUNCTION(2, "DPI_D5"),
@@ -407,9 +403,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[0]")
),
MTK_PIN(
- PINCTRL_PIN(35, "UTXD2"),
- NULL, "mt8167",
+ 35, "UTXD2",
MTK_EINT_FUNCTION(0, 35),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO35"),
MTK_FUNCTION(1, "UTXD2"),
MTK_FUNCTION(2, "DPI_HSYNC"),
@@ -420,9 +416,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[1]")
),
MTK_PIN(
- PINCTRL_PIN(36, "MRG_CLK"),
- NULL, "mt8167",
+ 36, "MRG_CLK",
MTK_EINT_FUNCTION(0, 36),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO36"),
MTK_FUNCTION(1, "MRG_CLK"),
MTK_FUNCTION(2, "DPI_D4"),
@@ -433,9 +429,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[2]")
),
MTK_PIN(
- PINCTRL_PIN(37, "MRG_SYNC"),
- NULL, "mt8167",
+ 37, "MRG_SYNC",
MTK_EINT_FUNCTION(0, 37),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO37"),
MTK_FUNCTION(1, "MRG_SYNC"),
MTK_FUNCTION(2, "DPI_D3"),
@@ -446,9 +442,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[3]")
),
MTK_PIN(
- PINCTRL_PIN(38, "MRG_DI"),
- NULL, "mt8167",
+ 38, "MRG_DI",
MTK_EINT_FUNCTION(0, 38),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO38"),
MTK_FUNCTION(1, "MRG_DI"),
MTK_FUNCTION(2, "DPI_D1"),
@@ -459,9 +455,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[4]")
),
MTK_PIN(
- PINCTRL_PIN(39, "MRG_DO"),
- NULL, "mt8167",
+ 39, "MRG_DO",
MTK_EINT_FUNCTION(0, 39),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO39"),
MTK_FUNCTION(1, "MRG_DO"),
MTK_FUNCTION(2, "DPI_D2"),
@@ -472,18 +468,18 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[5]")
),
MTK_PIN(
- PINCTRL_PIN(40, "KPROW0"),
- NULL, "mt8167",
+ 40, "KPROW0",
MTK_EINT_FUNCTION(0, 40),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO40"),
MTK_FUNCTION(1, "KPROW0"),
MTK_FUNCTION(4, "IMG_TEST_CK"),
MTK_FUNCTION(7, "DBG_MON_B[4]")
),
MTK_PIN(
- PINCTRL_PIN(41, "KPROW1"),
- NULL, "mt8167",
+ 41, "KPROW1",
MTK_EINT_FUNCTION(0, 41),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO41"),
MTK_FUNCTION(1, "KPROW1"),
MTK_FUNCTION(2, "IDDIG"),
@@ -492,17 +488,17 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[5]")
),
MTK_PIN(
- PINCTRL_PIN(42, "KPCOL0"),
- NULL, "mt8167",
+ 42, "KPCOL0",
MTK_EINT_FUNCTION(0, 42),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO42"),
MTK_FUNCTION(1, "KPCOL0"),
MTK_FUNCTION(7, "DBG_MON_B[6]")
),
MTK_PIN(
- PINCTRL_PIN(43, "KPCOL1"),
- NULL, "mt8167",
+ 43, "KPCOL1",
MTK_EINT_FUNCTION(0, 43),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO43"),
MTK_FUNCTION(1, "KPCOL1"),
MTK_FUNCTION(2, "USB_DRVVBUS"),
@@ -513,9 +509,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[7]")
),
MTK_PIN(
- PINCTRL_PIN(44, "JTMS"),
- NULL, "mt8167",
+ 44, "JTMS",
MTK_EINT_FUNCTION(0, 44),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO44"),
MTK_FUNCTION(1, "JTMS"),
MTK_FUNCTION(2, "CONN_MCU_TMS"),
@@ -525,9 +521,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(6, "UDI_TMS_XI")
),
MTK_PIN(
- PINCTRL_PIN(45, "JTCK"),
- NULL, "mt8167",
+ 45, "JTCK",
MTK_EINT_FUNCTION(0, 45),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO45"),
MTK_FUNCTION(1, "JTCK"),
MTK_FUNCTION(2, "CONN_MCU_TCK"),
@@ -537,9 +533,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(6, "UDI_TCK_XI")
),
MTK_PIN(
- PINCTRL_PIN(46, "JTDI"),
- NULL, "mt8167",
+ 46, "JTDI",
MTK_EINT_FUNCTION(0, 46),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO46"),
MTK_FUNCTION(1, "JTDI"),
MTK_FUNCTION(2, "CONN_MCU_TDI"),
@@ -548,9 +544,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(6, "UDI_TDI_XI")
),
MTK_PIN(
- PINCTRL_PIN(47, "JTDO"),
- NULL, "mt8167",
+ 47, "JTDO",
MTK_EINT_FUNCTION(0, 47),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO47"),
MTK_FUNCTION(1, "JTDO"),
MTK_FUNCTION(2, "CONN_MCU_TDO"),
@@ -559,9 +555,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(6, "UDI_TDO")
),
MTK_PIN(
- PINCTRL_PIN(48, "SPI_CS"),
- NULL, "mt8167",
+ 48, "SPI_CS",
MTK_EINT_FUNCTION(0, 48),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO48"),
MTK_FUNCTION(1, "SPI_CSB"),
MTK_FUNCTION(3, "I2S0_DI"),
@@ -569,9 +565,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[23]")
),
MTK_PIN(
- PINCTRL_PIN(49, "SPI_CK"),
- NULL, "mt8167",
+ 49, "SPI_CK",
MTK_EINT_FUNCTION(0, 49),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO49"),
MTK_FUNCTION(1, "SPI_CLK"),
MTK_FUNCTION(3, "I2S0_LRCK"),
@@ -579,9 +575,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[24]")
),
MTK_PIN(
- PINCTRL_PIN(50, "SPI_MI"),
- NULL, "mt8167",
+ 50, "SPI_MI",
MTK_EINT_FUNCTION(0, 50),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO50"),
MTK_FUNCTION(1, "SPI_MI"),
MTK_FUNCTION(2, "SPI_MO"),
@@ -590,9 +586,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[25]")
),
MTK_PIN(
- PINCTRL_PIN(51, "SPI_MO"),
- NULL, "mt8167",
+ 51, "SPI_MO",
MTK_EINT_FUNCTION(0, 51),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO51"),
MTK_FUNCTION(1, "SPI_MO"),
MTK_FUNCTION(2, "SPI_MI"),
@@ -601,32 +597,32 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[26]")
),
MTK_PIN(
- PINCTRL_PIN(52, "SDA1"),
- NULL, "mt8167",
+ 52, "SDA1",
MTK_EINT_FUNCTION(0, 52),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO52"),
MTK_FUNCTION(1, "SDA1_0")
),
MTK_PIN(
- PINCTRL_PIN(53, "SCL1"),
- NULL, "mt8167",
+ 53, "SCL1",
MTK_EINT_FUNCTION(0, 53),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO53"),
MTK_FUNCTION(1, "SCL1_0")
),
MTK_PIN(
- PINCTRL_PIN(54, "DISP_PWM"),
- NULL, "mt8167",
+ 54, "DISP_PWM",
MTK_EINT_FUNCTION(0, 54),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO54"),
MTK_FUNCTION(1, "DISP_PWM"),
MTK_FUNCTION(2, "PWM_B"),
MTK_FUNCTION(7, "DBG_MON_B[2]")
),
MTK_PIN(
- PINCTRL_PIN(55, "I2S_DATA_IN"),
- NULL, "mt8167",
+ 55, "I2S_DATA_IN",
MTK_EINT_FUNCTION(0, 55),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO55"),
MTK_FUNCTION(1, "I2S0_DI"),
MTK_FUNCTION(2, "UCTS0"),
@@ -637,9 +633,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[28]")
),
MTK_PIN(
- PINCTRL_PIN(56, "I2S_LRCK"),
- NULL, "mt8167",
+ 56, "I2S_LRCK",
MTK_EINT_FUNCTION(0, 56),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO56"),
MTK_FUNCTION(1, "I2S0_LRCK"),
MTK_FUNCTION(3, "I2S3_LRCK"),
@@ -649,9 +645,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[29]")
),
MTK_PIN(
- PINCTRL_PIN(57, "I2S_BCK"),
- NULL, "mt8167",
+ 57, "I2S_BCK",
MTK_EINT_FUNCTION(0, 57),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO57"),
MTK_FUNCTION(1, "I2S0_BCK"),
MTK_FUNCTION(2, "URTS0"),
@@ -662,91 +658,91 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[30]")
),
MTK_PIN(
- PINCTRL_PIN(58, "SDA0"),
- NULL, "mt8167",
+ 58, "SDA0",
MTK_EINT_FUNCTION(0, 58),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO58"),
MTK_FUNCTION(1, "SDA0_0")
),
MTK_PIN(
- PINCTRL_PIN(59, "SCL0"),
- NULL, "mt8167",
+ 59, "SCL0",
MTK_EINT_FUNCTION(0, 59),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO59"),
MTK_FUNCTION(1, "SCL0_0")
),
MTK_PIN(
- PINCTRL_PIN(60, "SDA2"),
- NULL, "mt8167",
+ 60, "SDA2",
MTK_EINT_FUNCTION(0, 60),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO60"),
MTK_FUNCTION(1, "SDA2_0"),
MTK_FUNCTION(2, "PWM_B")
),
MTK_PIN(
- PINCTRL_PIN(61, "SCL2"),
- NULL, "mt8167",
+ 61, "SCL2",
MTK_EINT_FUNCTION(0, 61),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO61"),
MTK_FUNCTION(1, "SCL2_0"),
MTK_FUNCTION(2, "PWM_C")
),
MTK_PIN(
- PINCTRL_PIN(62, "URXD0"),
- NULL, "mt8167",
+ 62, "URXD0",
MTK_EINT_FUNCTION(0, 62),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO62"),
MTK_FUNCTION(1, "URXD0"),
MTK_FUNCTION(2, "UTXD0")
),
MTK_PIN(
- PINCTRL_PIN(63, "UTXD0"),
- NULL, "mt8167",
+ 63, "UTXD0",
MTK_EINT_FUNCTION(0, 63),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO63"),
MTK_FUNCTION(1, "UTXD0"),
MTK_FUNCTION(2, "URXD0")
),
MTK_PIN(
- PINCTRL_PIN(64, "URXD1"),
- NULL, "mt8167",
+ 64, "URXD1",
MTK_EINT_FUNCTION(0, 64),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO64"),
MTK_FUNCTION(1, "URXD1"),
MTK_FUNCTION(2, "UTXD1"),
MTK_FUNCTION(7, "DBG_MON_A[27]")
),
MTK_PIN(
- PINCTRL_PIN(65, "UTXD1"),
- NULL, "mt8167",
+ 65, "UTXD1",
MTK_EINT_FUNCTION(0, 65),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO65"),
MTK_FUNCTION(1, "UTXD1"),
MTK_FUNCTION(2, "URXD1"),
MTK_FUNCTION(7, "DBG_MON_A[31]")
),
MTK_PIN(
- PINCTRL_PIN(66, "LCM_RST"),
- NULL, "mt8167",
+ 66, "LCM_RST",
MTK_EINT_FUNCTION(0, 66),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO66"),
MTK_FUNCTION(1, "LCM_RST"),
MTK_FUNCTION(3, "I2S0_MCK"),
MTK_FUNCTION(7, "DBG_MON_B[3]")
),
MTK_PIN(
- PINCTRL_PIN(67, "DSI_TE"),
- NULL, "mt8167",
+ 67, "DSI_TE",
MTK_EINT_FUNCTION(0, 67),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO67"),
MTK_FUNCTION(1, "DSI_TE"),
MTK_FUNCTION(3, "I2S_8CH_MCK"),
MTK_FUNCTION(7, "DBG_MON_B[14]")
),
MTK_PIN(
- PINCTRL_PIN(68, "MSDC2_CMD"),
- NULL, "mt8167",
+ 68, "MSDC2_CMD",
MTK_EINT_FUNCTION(0, 68),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO68"),
MTK_FUNCTION(1, "MSDC2_CMD"),
MTK_FUNCTION(2, "I2S_8CH_DO4"),
@@ -756,9 +752,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[15]")
),
MTK_PIN(
- PINCTRL_PIN(69, "MSDC2_CLK"),
- NULL, "mt8167",
+ 69, "MSDC2_CLK",
MTK_EINT_FUNCTION(0, 69),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO69"),
MTK_FUNCTION(1, "MSDC2_CLK"),
MTK_FUNCTION(2, "I2S_8CH_DO3"),
@@ -769,9 +765,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[16]")
),
MTK_PIN(
- PINCTRL_PIN(70, "MSDC2_DAT0"),
- NULL, "mt8167",
+ 70, "MSDC2_DAT0",
MTK_EINT_FUNCTION(0, 70),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO70"),
MTK_FUNCTION(1, "MSDC2_DAT0"),
MTK_FUNCTION(2, "I2S_8CH_DO2"),
@@ -781,9 +777,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[17]")
),
MTK_PIN(
- PINCTRL_PIN(71, "MSDC2_DAT1"),
- NULL, "mt8167",
+ 71, "MSDC2_DAT1",
MTK_EINT_FUNCTION(0, 71),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO71"),
MTK_FUNCTION(1, "MSDC2_DAT1"),
MTK_FUNCTION(2, "I2S_8CH_DO1"),
@@ -794,9 +790,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[18]")
),
MTK_PIN(
- PINCTRL_PIN(72, "MSDC2_DAT2"),
- NULL, "mt8167",
+ 72, "MSDC2_DAT2",
MTK_EINT_FUNCTION(0, 72),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO72"),
MTK_FUNCTION(1, "MSDC2_DAT2"),
MTK_FUNCTION(2, "I2S_8CH_LRCK"),
@@ -807,9 +803,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[19]")
),
MTK_PIN(
- PINCTRL_PIN(73, "MSDC2_DAT3"),
- NULL, "mt8167",
+ 73, "MSDC2_DAT3",
MTK_EINT_FUNCTION(0, 73),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO73"),
MTK_FUNCTION(1, "MSDC2_DAT3"),
MTK_FUNCTION(2, "I2S_8CH_BCK"),
@@ -820,203 +816,203 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[20]")
),
MTK_PIN(
- PINCTRL_PIN(74, "TDN3"),
- NULL, "mt8167",
+ 74, "TDN3",
MTK_EINT_FUNCTION(0, 74),
- MTK_FUNCTION(0, "GPI74"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO74"),
MTK_FUNCTION(1, "TDN3")
),
MTK_PIN(
- PINCTRL_PIN(75, "TDP3"),
- NULL, "mt8167",
+ 75, "TDP3",
MTK_EINT_FUNCTION(0, 75),
- MTK_FUNCTION(0, "GPI75"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO75"),
MTK_FUNCTION(1, "TDP3")
),
MTK_PIN(
- PINCTRL_PIN(76, "TDN2"),
- NULL, "mt8167",
+ 76, "TDN2",
MTK_EINT_FUNCTION(0, 76),
- MTK_FUNCTION(0, "GPI76"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO76"),
MTK_FUNCTION(1, "TDN2")
),
MTK_PIN(
- PINCTRL_PIN(77, "TDP2"),
- NULL, "mt8167",
+ 77, "TDP2",
MTK_EINT_FUNCTION(0, 77),
- MTK_FUNCTION(0, "GPI77"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO77"),
MTK_FUNCTION(1, "TDP2")
),
MTK_PIN(
- PINCTRL_PIN(78, "TCN"),
- NULL, "mt8167",
+ 78, "TCN",
MTK_EINT_FUNCTION(0, 78),
- MTK_FUNCTION(0, "GPI78"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO78"),
MTK_FUNCTION(1, "TCN")
),
MTK_PIN(
- PINCTRL_PIN(79, "TCP"),
- NULL, "mt8167",
+ 79, "TCP",
MTK_EINT_FUNCTION(0, 79),
- MTK_FUNCTION(0, "GPI79"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO79"),
MTK_FUNCTION(1, "TCP")
),
MTK_PIN(
- PINCTRL_PIN(80, "TDN1"),
- NULL, "mt8167",
+ 80, "TDN1",
MTK_EINT_FUNCTION(0, 80),
- MTK_FUNCTION(0, "GPI80"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO80"),
MTK_FUNCTION(1, "TDN1")
),
MTK_PIN(
- PINCTRL_PIN(81, "TDP1"),
- NULL, "mt8167",
+ 81, "TDP1",
MTK_EINT_FUNCTION(0, 81),
- MTK_FUNCTION(0, "GPI81"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO81"),
MTK_FUNCTION(1, "TDP1")
),
MTK_PIN(
- PINCTRL_PIN(82, "TDN0"),
- NULL, "mt8167",
+ 82, "TDN0",
MTK_EINT_FUNCTION(0, 82),
- MTK_FUNCTION(0, "GPI82"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO82"),
MTK_FUNCTION(1, "TDN0")
),
MTK_PIN(
- PINCTRL_PIN(83, "TDP0"),
- NULL, "mt8167",
+ 83, "TDP0",
MTK_EINT_FUNCTION(0, 83),
- MTK_FUNCTION(0, "GPI83"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO83"),
MTK_FUNCTION(1, "TDP0")
),
MTK_PIN(
- PINCTRL_PIN(84, "RDN0"),
- NULL, "mt8167",
+ 84, "RDN0",
MTK_EINT_FUNCTION(0, 84),
- MTK_FUNCTION(0, "GPI84"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO84"),
MTK_FUNCTION(1, "RDN0")
),
MTK_PIN(
- PINCTRL_PIN(85, "RDP0"),
- NULL, "mt8167",
+ 85, "RDP0",
MTK_EINT_FUNCTION(0, 85),
- MTK_FUNCTION(0, "GPI85"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO85"),
MTK_FUNCTION(1, "RDP0")
),
MTK_PIN(
- PINCTRL_PIN(86, "RDN1"),
- NULL, "mt8167",
+ 86, "RDN1",
MTK_EINT_FUNCTION(0, 86),
- MTK_FUNCTION(0, "GPI86"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO86"),
MTK_FUNCTION(1, "RDN1")
),
MTK_PIN(
- PINCTRL_PIN(87, "RDP1"),
- NULL, "mt8167",
+ 87, "RDP1",
MTK_EINT_FUNCTION(0, 87),
- MTK_FUNCTION(0, "GPI87"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO87"),
MTK_FUNCTION(1, "RDP1")
),
MTK_PIN(
- PINCTRL_PIN(88, "RCN"),
- NULL, "mt8167",
+ 88, "RCN",
MTK_EINT_FUNCTION(0, 88),
- MTK_FUNCTION(0, "GPI88"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO88"),
MTK_FUNCTION(1, "RCN")
),
MTK_PIN(
- PINCTRL_PIN(89, "RCP"),
- NULL, "mt8167",
+ 89, "RCP",
MTK_EINT_FUNCTION(0, 89),
- MTK_FUNCTION(0, "GPI89"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO89"),
MTK_FUNCTION(1, "RCP")
),
MTK_PIN(
- PINCTRL_PIN(90, "RDN2"),
- NULL, "mt8167",
+ 90, "RDN2",
MTK_EINT_FUNCTION(0, 90),
- MTK_FUNCTION(0, "GPI90"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO90"),
MTK_FUNCTION(1, "RDN2"),
MTK_FUNCTION(2, "CMDAT8")
),
MTK_PIN(
- PINCTRL_PIN(91, "RDP2"),
- NULL, "mt8167",
+ 91, "RDP2",
MTK_EINT_FUNCTION(0, 91),
- MTK_FUNCTION(0, "GPI91"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO91"),
MTK_FUNCTION(1, "RDP2"),
MTK_FUNCTION(2, "CMDAT9")
),
MTK_PIN(
- PINCTRL_PIN(92, "RDN3"),
- NULL, "mt8167",
+ 92, "RDN3",
MTK_EINT_FUNCTION(0, 92),
- MTK_FUNCTION(0, "GPI92"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO92"),
MTK_FUNCTION(1, "RDN3"),
MTK_FUNCTION(2, "CMDAT4")
),
MTK_PIN(
- PINCTRL_PIN(93, "RDP3"),
- NULL, "mt8167",
+ 93, "RDP3",
MTK_EINT_FUNCTION(0, 93),
- MTK_FUNCTION(0, "GPI93"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO93"),
MTK_FUNCTION(1, "RDP3"),
MTK_FUNCTION(2, "CMDAT5")
),
MTK_PIN(
- PINCTRL_PIN(94, "RCN_A"),
- NULL, "mt8167",
+ 94, "RCN_A",
MTK_EINT_FUNCTION(0, 94),
- MTK_FUNCTION(0, "GPI94"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO94"),
MTK_FUNCTION(1, "RCN_A"),
MTK_FUNCTION(2, "CMDAT6")
),
MTK_PIN(
- PINCTRL_PIN(95, "RCP_A"),
- NULL, "mt8167",
+ 95, "RCP_A",
MTK_EINT_FUNCTION(0, 95),
- MTK_FUNCTION(0, "GPI95"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO95"),
MTK_FUNCTION(1, "RCP_A"),
MTK_FUNCTION(2, "CMDAT7")
),
MTK_PIN(
- PINCTRL_PIN(96, "RDN1_A"),
- NULL, "mt8167",
+ 96, "RDN1_A",
MTK_EINT_FUNCTION(0, 96),
- MTK_FUNCTION(0, "GPI96"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO96"),
MTK_FUNCTION(1, "RDN1_A"),
MTK_FUNCTION(2, "CMDAT2"),
MTK_FUNCTION(3, "CMCSD2")
),
MTK_PIN(
- PINCTRL_PIN(97, "RDP1_A"),
- NULL, "mt8167",
+ 97, "RDP1_A",
MTK_EINT_FUNCTION(0, 97),
- MTK_FUNCTION(0, "GPI97"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO97"),
MTK_FUNCTION(1, "RDP1_A"),
MTK_FUNCTION(2, "CMDAT3"),
MTK_FUNCTION(3, "CMCSD3")
),
MTK_PIN(
- PINCTRL_PIN(98, "RDN0_A"),
- NULL, "mt8167",
+ 98, "RDN0_A",
MTK_EINT_FUNCTION(0, 98),
- MTK_FUNCTION(0, "GPI98"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO98"),
MTK_FUNCTION(1, "RDN0_A"),
MTK_FUNCTION(2, "CMHSYNC")
),
MTK_PIN(
- PINCTRL_PIN(99, "RDP0_A"),
- NULL, "mt8167",
+ 99, "RDP0_A",
MTK_EINT_FUNCTION(0, 99),
- MTK_FUNCTION(0, "GPI99"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO99"),
MTK_FUNCTION(1, "RDP0_A"),
MTK_FUNCTION(2, "CMVSYNC")
),
MTK_PIN(
- PINCTRL_PIN(100, "CMDAT0"),
- NULL, "mt8167",
+ 100, "CMDAT0",
MTK_EINT_FUNCTION(0, 100),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO100"),
MTK_FUNCTION(1, "CMDAT0"),
MTK_FUNCTION(2, "CMCSD0"),
@@ -1025,9 +1021,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[21]")
),
MTK_PIN(
- PINCTRL_PIN(101, "CMDAT1"),
- NULL, "mt8167",
+ 101, "CMDAT1",
MTK_EINT_FUNCTION(0, 101),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO101"),
MTK_FUNCTION(1, "CMDAT1"),
MTK_FUNCTION(2, "CMCSD1"),
@@ -1037,9 +1033,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[22]")
),
MTK_PIN(
- PINCTRL_PIN(102, "CMMCLK"),
- NULL, "mt8167",
+ 102, "CMMCLK",
MTK_EINT_FUNCTION(0, 102),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO102"),
MTK_FUNCTION(1, "CMMCLK"),
MTK_FUNCTION(3, "ANT_SEL4"),
@@ -1047,29 +1043,29 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[23]")
),
MTK_PIN(
- PINCTRL_PIN(103, "CMPCLK"),
- NULL, "mt8167",
+ 103, "CMPCLK",
MTK_EINT_FUNCTION(0, 103),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO103"),
MTK_FUNCTION(1, "CMPCLK"),
MTK_FUNCTION(2, "CMCSK"),
MTK_FUNCTION(3, "ANT_SEL5"),
- MTK_FUNCTION(5, " TDM_RX_DI"),
+ MTK_FUNCTION(5, "TDM_RX_DI"),
MTK_FUNCTION(7, "DBG_MON_B[24]")
),
MTK_PIN(
- PINCTRL_PIN(104, "MSDC1_CMD"),
- NULL, "mt8167",
+ 104, "MSDC1_CMD",
MTK_EINT_FUNCTION(0, 104),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO104"),
MTK_FUNCTION(1, "MSDC1_CMD"),
MTK_FUNCTION(4, "SQICS"),
MTK_FUNCTION(7, "DBG_MON_B[25]")
),
MTK_PIN(
- PINCTRL_PIN(105, "MSDC1_CLK"),
- NULL, "mt8167",
+ 105, "MSDC1_CLK",
MTK_EINT_FUNCTION(0, 105),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO105"),
MTK_FUNCTION(1, "MSDC1_CLK"),
MTK_FUNCTION(2, "UDI_NTRST_XI"),
@@ -1079,9 +1075,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[26]")
),
MTK_PIN(
- PINCTRL_PIN(106, "MSDC1_DAT0"),
- NULL, "mt8167",
+ 106, "MSDC1_DAT0",
MTK_EINT_FUNCTION(0, 106),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO106"),
MTK_FUNCTION(1, "MSDC1_DAT0"),
MTK_FUNCTION(2, "UDI_TMS_XI"),
@@ -1091,9 +1087,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[27]")
),
MTK_PIN(
- PINCTRL_PIN(107, "MSDC1_DAT1"),
- NULL, "mt8167",
+ 107, "MSDC1_DAT1",
MTK_EINT_FUNCTION(0, 107),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO107"),
MTK_FUNCTION(1, "MSDC1_DAT1"),
MTK_FUNCTION(2, "UDI_TCK_XI"),
@@ -1103,9 +1099,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[28]")
),
MTK_PIN(
- PINCTRL_PIN(108, "MSDC1_DAT2"),
- NULL, "mt8167",
+ 108, "MSDC1_DAT2",
MTK_EINT_FUNCTION(0, 108),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO108"),
MTK_FUNCTION(1, "MSDC1_DAT2"),
MTK_FUNCTION(2, "UDI_TDI_XI"),
@@ -1115,9 +1111,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[29]")
),
MTK_PIN(
- PINCTRL_PIN(109, "MSDC1_DAT3"),
- NULL, "mt8167",
+ 109, "MSDC1_DAT3",
MTK_EINT_FUNCTION(0, 109),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO109"),
MTK_FUNCTION(1, "MSDC1_DAT3"),
MTK_FUNCTION(2, "UDI_TDO"),
@@ -1127,119 +1123,119 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[30]")
),
MTK_PIN(
- PINCTRL_PIN(110, "MSDC0_DAT7"),
- NULL, "mt8167",
+ 110, "MSDC0_DAT7",
MTK_EINT_FUNCTION(0, 110),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO110"),
MTK_FUNCTION(1, "MSDC0_DAT7"),
MTK_FUNCTION(4, "NLD7")
),
MTK_PIN(
- PINCTRL_PIN(111, "MSDC0_DAT6"),
- NULL, "mt8167",
+ 111, "MSDC0_DAT6",
MTK_EINT_FUNCTION(0, 111),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO111"),
MTK_FUNCTION(1, "MSDC0_DAT6"),
MTK_FUNCTION(4, "NLD6")
),
MTK_PIN(
- PINCTRL_PIN(112, "MSDC0_DAT5"),
- NULL, "mt8167",
+ 112, "MSDC0_DAT5",
MTK_EINT_FUNCTION(0, 112),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO112"),
MTK_FUNCTION(1, "MSDC0_DAT5"),
MTK_FUNCTION(4, "NLD4")
),
MTK_PIN(
- PINCTRL_PIN(113, "MSDC0_DAT4"),
- NULL, "mt8167",
+ 113, "MSDC0_DAT4",
MTK_EINT_FUNCTION(0, 113),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO113"),
MTK_FUNCTION(1, "MSDC0_DAT4"),
MTK_FUNCTION(4, "NLD3")
),
MTK_PIN(
- PINCTRL_PIN(114, "MSDC0_RSTB"),
- NULL, "mt8167",
+ 114, "MSDC0_RSTB",
MTK_EINT_FUNCTION(0, 114),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO114"),
MTK_FUNCTION(1, "MSDC0_RSTB"),
MTK_FUNCTION(4, "NLD0")
),
MTK_PIN(
- PINCTRL_PIN(115, "MSDC0_CMD"),
- NULL, "mt8167",
+ 115, "MSDC0_CMD",
MTK_EINT_FUNCTION(0, 115),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO115"),
MTK_FUNCTION(1, "MSDC0_CMD"),
MTK_FUNCTION(4, "NALE")
),
MTK_PIN(
- PINCTRL_PIN(116, "MSDC0_CLK"),
- NULL, "mt8167",
+ 116, "MSDC0_CLK",
MTK_EINT_FUNCTION(0, 116),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO116"),
MTK_FUNCTION(1, "MSDC0_CLK"),
MTK_FUNCTION(4, "NWEB")
),
MTK_PIN(
- PINCTRL_PIN(117, "MSDC0_DAT3"),
- NULL, "mt8167",
+ 117, "MSDC0_DAT3",
MTK_EINT_FUNCTION(0, 117),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO117"),
MTK_FUNCTION(1, "MSDC0_DAT3"),
MTK_FUNCTION(4, "NLD1")
),
MTK_PIN(
- PINCTRL_PIN(118, "MSDC0_DAT2"),
- NULL, "mt8167",
+ 118, "MSDC0_DAT2",
MTK_EINT_FUNCTION(0, 118),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO118"),
MTK_FUNCTION(1, "MSDC0_DAT2"),
MTK_FUNCTION(4, "NLD5")
),
MTK_PIN(
- PINCTRL_PIN(119, "MSDC0_DAT1"),
- NULL, "mt8167",
+ 119, "MSDC0_DAT1",
MTK_EINT_FUNCTION(0, 119),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO119"),
MTK_FUNCTION(1, "MSDC0_DAT1"),
MTK_FUNCTION(4, "NLD8")
),
MTK_PIN(
- PINCTRL_PIN(120, "MSDC0_DAT0"),
- NULL, "mt8167",
+ 120, "MSDC0_DAT0",
MTK_EINT_FUNCTION(0, 120),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO120"),
MTK_FUNCTION(1, "MSDC0_DAT0"),
MTK_FUNCTION(4, "WATCHDOG"),
MTK_FUNCTION(5, "NLD2")
),
MTK_PIN(
- PINCTRL_PIN(121, "CEC"),
- NULL, "mt8167",
+ 121, "CEC",
MTK_EINT_FUNCTION(0, 121),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO121"),
MTK_FUNCTION(1, "CEC")
),
MTK_PIN(
- PINCTRL_PIN(122, "HTPLG"),
- NULL, "mt8167",
+ 122, "HTPLG",
MTK_EINT_FUNCTION(0, 122),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO122"),
MTK_FUNCTION(1, "HTPLG")
),
MTK_PIN(
- PINCTRL_PIN(123, "HDMISCK"),
- NULL, "mt8167",
+ 123, "HDMISCK",
MTK_EINT_FUNCTION(0, 123),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO123"),
MTK_FUNCTION(1, "HDMISCK")
),
MTK_PIN(
- PINCTRL_PIN(124, "HDMISD"),
- NULL, "mt8167",
+ 124, "HDMISD",
MTK_EINT_FUNCTION(0, 124),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO124"),
MTK_FUNCTION(1, "HDMISD")
),
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
index f7a4c6e4a026..fc4f8401b3c6 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
@@ -1,18 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2019 MediaTek Inc.
- */
#ifndef __PINCTRL_MTK_MT8516_H
#define __PINCTRL_MTK_MT8516_H
-#include <linux/pinctrl/pinctrl.h>
-#include "pinctrl-mtk-common.h"
+#include "pinctrl-paris.h"
-static const struct mtk_desc_pin mtk_pins_mt8516[] = {
+static const struct mtk_pin_desc mtk_pins_mt8516[] = {
MTK_PIN(
- PINCTRL_PIN(0, "EINT0"),
- NULL, "mt8516",
+ 0, "EINT0",
MTK_EINT_FUNCTION(0, 0),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO0"),
MTK_FUNCTION(1, "PWM_B"),
MTK_FUNCTION(3, "I2S2_BCK"),
@@ -21,9 +17,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[6]")
),
MTK_PIN(
- PINCTRL_PIN(1, "EINT1"),
- NULL, "mt8516",
+ 1, "EINT1",
MTK_EINT_FUNCTION(0, 1),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO1"),
MTK_FUNCTION(1, "PWM_C"),
MTK_FUNCTION(3, "I2S2_DI"),
@@ -33,9 +29,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[7]")
),
MTK_PIN(
- PINCTRL_PIN(2, "EINT2"),
- NULL, "mt8516",
+ 2, "EINT2",
MTK_EINT_FUNCTION(0, 2),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO2"),
MTK_FUNCTION(1, "CLKM0"),
MTK_FUNCTION(3, "I2S2_LRCK"),
@@ -45,9 +41,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[8]")
),
MTK_PIN(
- PINCTRL_PIN(3, "EINT3"),
- NULL, "mt8516",
+ 3, "EINT3",
MTK_EINT_FUNCTION(0, 3),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO3"),
MTK_FUNCTION(1, "CLKM1"),
MTK_FUNCTION(3, "SPI_MI"),
@@ -57,9 +53,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[9]")
),
MTK_PIN(
- PINCTRL_PIN(4, "EINT4"),
- NULL, "mt8516",
+ 4, "EINT4",
MTK_EINT_FUNCTION(0, 4),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO4"),
MTK_FUNCTION(1, "CLKM2"),
MTK_FUNCTION(3, "SPI_MO"),
@@ -69,9 +65,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[10]")
),
MTK_PIN(
- PINCTRL_PIN(5, "EINT5"),
- NULL, "mt8516",
+ 5, "EINT5",
MTK_EINT_FUNCTION(0, 5),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO5"),
MTK_FUNCTION(1, "UCTS2"),
MTK_FUNCTION(3, "SPI_CSB"),
@@ -81,9 +77,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[11]")
),
MTK_PIN(
- PINCTRL_PIN(6, "EINT6"),
- NULL, "mt8516",
+ 6, "EINT6",
MTK_EINT_FUNCTION(0, 6),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO6"),
MTK_FUNCTION(1, "URTS2"),
MTK_FUNCTION(3, "SPI_CLK"),
@@ -92,9 +88,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[12]")
),
MTK_PIN(
- PINCTRL_PIN(7, "EINT7"),
- NULL, "mt8516",
+ 7, "EINT7",
MTK_EINT_FUNCTION(0, 7),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO7"),
MTK_FUNCTION(1, "SQIRST"),
MTK_FUNCTION(3, "SDA1_0"),
@@ -104,9 +100,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[13]")
),
MTK_PIN(
- PINCTRL_PIN(8, "EINT8"),
- NULL, "mt8516",
+ 8, "EINT8",
MTK_EINT_FUNCTION(0, 8),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO8"),
MTK_FUNCTION(1, "SQICK"),
MTK_FUNCTION(2, "CLKM3"),
@@ -116,9 +112,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[14]")
),
MTK_PIN(
- PINCTRL_PIN(9, "EINT9"),
- NULL, "mt8516",
+ 9, "EINT9",
MTK_EINT_FUNCTION(0, 9),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO9"),
MTK_FUNCTION(1, "CLKM4"),
MTK_FUNCTION(2, "SDA2_0"),
@@ -128,9 +124,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[15]")
),
MTK_PIN(
- PINCTRL_PIN(10, "EINT10"),
- NULL, "mt8516",
+ 10, "EINT10",
MTK_EINT_FUNCTION(0, 10),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO10"),
MTK_FUNCTION(1, "CLKM5"),
MTK_FUNCTION(2, "SCL2_0"),
@@ -140,9 +136,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[16]")
),
MTK_PIN(
- PINCTRL_PIN(11, "EINT11"),
- NULL, "mt8516",
+ 11, "EINT11",
MTK_EINT_FUNCTION(0, 11),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO11"),
MTK_FUNCTION(1, "CLKM4"),
MTK_FUNCTION(2, "PWM_C"),
@@ -152,9 +148,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[17]")
),
MTK_PIN(
- PINCTRL_PIN(12, "EINT12"),
- NULL, "mt8516",
+ 12, "EINT12",
MTK_EINT_FUNCTION(0, 12),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO12"),
MTK_FUNCTION(1, "CLKM5"),
MTK_FUNCTION(2, "PWM_A"),
@@ -164,9 +160,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[18]")
),
MTK_PIN(
- PINCTRL_PIN(13, "EINT13"),
- NULL, "mt8516",
+ 13, "EINT13",
MTK_EINT_FUNCTION(0, 13),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO13"),
MTK_FUNCTION(3, "TSF_IN"),
MTK_FUNCTION(4, "ANT_SEL5"),
@@ -174,9 +170,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[19]")
),
MTK_PIN(
- PINCTRL_PIN(14, "EINT14"),
- NULL, "mt8516",
+ 14, "EINT14",
MTK_EINT_FUNCTION(0, 14),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO14"),
MTK_FUNCTION(2, "I2S_8CH_DO1"),
MTK_FUNCTION(3, "TDM_RX_MCK"),
@@ -186,9 +182,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[8]")
),
MTK_PIN(
- PINCTRL_PIN(15, "EINT15"),
- NULL, "mt8516",
+ 15, "EINT15",
MTK_EINT_FUNCTION(0, 15),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO15"),
MTK_FUNCTION(2, "I2S_8CH_LRCK"),
MTK_FUNCTION(3, "TDM_RX_BCK"),
@@ -198,9 +194,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[9]")
),
MTK_PIN(
- PINCTRL_PIN(16, "EINT16"),
- NULL, "mt8516",
+ 16, "EINT16",
MTK_EINT_FUNCTION(0, 16),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO16"),
MTK_FUNCTION(2, "I2S_8CH_BCK"),
MTK_FUNCTION(3, "TDM_RX_LRCK"),
@@ -210,9 +206,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[10]")
),
MTK_PIN(
- PINCTRL_PIN(17, "EINT17"),
- NULL, "mt8516",
+ 17, "EINT17",
MTK_EINT_FUNCTION(0, 17),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO17"),
MTK_FUNCTION(2, "I2S_8CH_MCK"),
MTK_FUNCTION(3, "TDM_RX_DI"),
@@ -222,9 +218,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[11]")
),
MTK_PIN(
- PINCTRL_PIN(18, "EINT18"),
- NULL, "mt8516",
+ 18, "EINT18",
MTK_EINT_FUNCTION(0, 18),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO18"),
MTK_FUNCTION(2, "USB_DRVVBUS"),
MTK_FUNCTION(3, "I2S3_LRCK"),
@@ -234,9 +230,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[20]")
),
MTK_PIN(
- PINCTRL_PIN(19, "EINT19"),
- NULL, "mt8516",
+ 19, "EINT19",
MTK_EINT_FUNCTION(0, 19),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO19"),
MTK_FUNCTION(1, "UCTS1"),
MTK_FUNCTION(2, "IDDIG"),
@@ -247,9 +243,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[21]")
),
MTK_PIN(
- PINCTRL_PIN(20, "EINT20"),
- NULL, "mt8516",
+ 20, "EINT20",
MTK_EINT_FUNCTION(0, 20),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO20"),
MTK_FUNCTION(1, "URTS1"),
MTK_FUNCTION(3, "I2S3_DO"),
@@ -259,9 +255,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[22]")
),
MTK_PIN(
- PINCTRL_PIN(21, "EINT21"),
- NULL, "mt8516",
+ 21, "EINT21",
MTK_EINT_FUNCTION(0, 21),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO21"),
MTK_FUNCTION(1, "NRNB"),
MTK_FUNCTION(2, "ANT_SEL0"),
@@ -269,9 +265,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[31]")
),
MTK_PIN(
- PINCTRL_PIN(22, "EINT22"),
- NULL, "mt8516",
+ 22, "EINT22",
MTK_EINT_FUNCTION(0, 22),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO22"),
MTK_FUNCTION(2, "I2S_8CH_DO2"),
MTK_FUNCTION(3, "TSF_IN"),
@@ -281,9 +277,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[12]")
),
MTK_PIN(
- PINCTRL_PIN(23, "EINT23"),
- NULL, "mt8516",
+ 23, "EINT23",
MTK_EINT_FUNCTION(0, 23),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO23"),
MTK_FUNCTION(2, "I2S_8CH_DO3"),
MTK_FUNCTION(3, "CLKM0"),
@@ -293,9 +289,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[13]")
),
MTK_PIN(
- PINCTRL_PIN(24, "EINT24"),
- NULL, "mt8516",
+ 24, "EINT24",
MTK_EINT_FUNCTION(0, 24),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO24"),
MTK_FUNCTION(3, "ANT_SEL1"),
MTK_FUNCTION(4, "UCTS2"),
@@ -304,9 +300,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[0]")
),
MTK_PIN(
- PINCTRL_PIN(25, "EINT25"),
- NULL, "mt8516",
+ 25, "EINT25",
MTK_EINT_FUNCTION(0, 25),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO25"),
MTK_FUNCTION(3, "ANT_SEL0"),
MTK_FUNCTION(4, "URTS2"),
@@ -315,25 +311,25 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[1]")
),
MTK_PIN(
- PINCTRL_PIN(26, "PWRAP_SPI0_MI"),
- NULL, "mt8516",
+ 26, "PWRAP_SPI0_MI",
MTK_EINT_FUNCTION(0, 26),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO26"),
MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
MTK_FUNCTION(2, "PWRAP_SPI0_MI")
),
MTK_PIN(
- PINCTRL_PIN(27, "PWRAP_SPI0_MO"),
- NULL, "mt8516",
+ 27, "PWRAP_SPI0_MO",
MTK_EINT_FUNCTION(0, 27),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO27"),
MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
MTK_FUNCTION(2, "PWRAP_SPI0_MO")
),
MTK_PIN(
- PINCTRL_PIN(28, "PWRAP_INT"),
- NULL, "mt8516",
+ 28, "PWRAP_INT",
MTK_EINT_FUNCTION(0, 28),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO28"),
MTK_FUNCTION(1, "I2S0_MCK"),
MTK_FUNCTION(4, "I2S_8CH_MCK"),
@@ -341,44 +337,44 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(6, "I2S3_MCK")
),
MTK_PIN(
- PINCTRL_PIN(29, "PWRAP_SPI0_CK"),
- NULL, "mt8516",
+ 29, "PWRAP_SPI0_CK",
MTK_EINT_FUNCTION(0, 29),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO29"),
MTK_FUNCTION(1, "PWRAP_SPI0_CK")
),
MTK_PIN(
- PINCTRL_PIN(30, "PWRAP_SPI0_CSN"),
- NULL, "mt8516",
+ 30, "PWRAP_SPI0_CSN",
MTK_EINT_FUNCTION(0, 30),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO30"),
MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
),
MTK_PIN(
- PINCTRL_PIN(31, "RTC32K_CK"),
- NULL, "mt8516",
+ 31, "RTC32K_CK",
MTK_EINT_FUNCTION(0, 31),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO31"),
MTK_FUNCTION(1, "RTC32K_CK")
),
MTK_PIN(
- PINCTRL_PIN(32, "WATCHDOG"),
- NULL, "mt8516",
+ 32, "WATCHDOG",
MTK_EINT_FUNCTION(0, 32),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO32"),
MTK_FUNCTION(1, "WATCHDOG")
),
MTK_PIN(
- PINCTRL_PIN(33, "SRCLKENA"),
- NULL, "mt8516",
+ 33, "SRCLKENA",
MTK_EINT_FUNCTION(0, 33),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO33"),
MTK_FUNCTION(1, "SRCLKENA0")
),
MTK_PIN(
- PINCTRL_PIN(34, "URXD2"),
- NULL, "mt8516",
+ 34, "URXD2",
MTK_EINT_FUNCTION(0, 34),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO34"),
MTK_FUNCTION(1, "URXD2"),
MTK_FUNCTION(3, "UTXD2"),
@@ -387,9 +383,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[0]")
),
MTK_PIN(
- PINCTRL_PIN(35, "UTXD2"),
- NULL, "mt8516",
+ 35, "UTXD2",
MTK_EINT_FUNCTION(0, 35),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO35"),
MTK_FUNCTION(1, "UTXD2"),
MTK_FUNCTION(3, "URXD2"),
@@ -398,9 +394,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[1]")
),
MTK_PIN(
- PINCTRL_PIN(36, "MRG_CLK"),
- NULL, "mt8516",
+ 36, "MRG_CLK",
MTK_EINT_FUNCTION(0, 36),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO36"),
MTK_FUNCTION(1, "MRG_CLK"),
MTK_FUNCTION(3, "I2S0_BCK"),
@@ -410,9 +406,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[2]")
),
MTK_PIN(
- PINCTRL_PIN(37, "MRG_SYNC"),
- NULL, "mt8516",
+ 37, "MRG_SYNC",
MTK_EINT_FUNCTION(0, 37),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO37"),
MTK_FUNCTION(1, "MRG_SYNC"),
MTK_FUNCTION(3, "I2S0_LRCK"),
@@ -422,9 +418,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[3]")
),
MTK_PIN(
- PINCTRL_PIN(38, "MRG_DI"),
- NULL, "mt8516",
+ 38, "MRG_DI",
MTK_EINT_FUNCTION(0, 38),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO38"),
MTK_FUNCTION(1, "MRG_DI"),
MTK_FUNCTION(3, "I2S0_DI"),
@@ -434,9 +430,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[4]")
),
MTK_PIN(
- PINCTRL_PIN(39, "MRG_DO"),
- NULL, "mt8516",
+ 39, "MRG_DO",
MTK_EINT_FUNCTION(0, 39),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO39"),
MTK_FUNCTION(1, "MRG_DO"),
MTK_FUNCTION(3, "I2S0_MCK"),
@@ -446,17 +442,17 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[5]")
),
MTK_PIN(
- PINCTRL_PIN(40, "KPROW0"),
- NULL, "mt8516",
+ 40, "KPROW0",
MTK_EINT_FUNCTION(0, 40),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO40"),
MTK_FUNCTION(1, "KPROW0"),
MTK_FUNCTION(7, "DBG_MON_B[4]")
),
MTK_PIN(
- PINCTRL_PIN(41, "KPROW1"),
- NULL, "mt8516",
+ 41, "KPROW1",
MTK_EINT_FUNCTION(0, 41),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO41"),
MTK_FUNCTION(1, "KPROW1"),
MTK_FUNCTION(2, "IDDIG"),
@@ -464,17 +460,17 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[5]")
),
MTK_PIN(
- PINCTRL_PIN(42, "KPCOL0"),
- NULL, "mt8516",
+ 42, "KPCOL0",
MTK_EINT_FUNCTION(0, 42),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO42"),
MTK_FUNCTION(1, "KPCOL0"),
MTK_FUNCTION(7, "DBG_MON_B[6]")
),
MTK_PIN(
- PINCTRL_PIN(43, "KPCOL1"),
- NULL, "mt8516",
+ 43, "KPCOL1",
MTK_EINT_FUNCTION(0, 43),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO43"),
MTK_FUNCTION(1, "KPCOL1"),
MTK_FUNCTION(2, "USB_DRVVBUS"),
@@ -483,43 +479,43 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[7]")
),
MTK_PIN(
- PINCTRL_PIN(44, "JTMS"),
- NULL, "mt8516",
+ 44, "JTMS",
MTK_EINT_FUNCTION(0, 44),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO44"),
MTK_FUNCTION(1, "JTMS"),
MTK_FUNCTION(2, "CONN_MCU_TMS"),
MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC")
),
MTK_PIN(
- PINCTRL_PIN(45, "JTCK"),
- NULL, "mt8516",
+ 45, "JTCK",
MTK_EINT_FUNCTION(0, 45),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO45"),
MTK_FUNCTION(1, "JTCK"),
MTK_FUNCTION(2, "CONN_MCU_TCK"),
MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC")
),
MTK_PIN(
- PINCTRL_PIN(46, "JTDI"),
- NULL, "mt8516",
+ 46, "JTDI",
MTK_EINT_FUNCTION(0, 46),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO46"),
MTK_FUNCTION(1, "JTDI"),
MTK_FUNCTION(2, "CONN_MCU_TDI")
),
MTK_PIN(
- PINCTRL_PIN(47, "JTDO"),
- NULL, "mt8516",
+ 47, "JTDO",
MTK_EINT_FUNCTION(0, 47),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO47"),
MTK_FUNCTION(1, "JTDO"),
MTK_FUNCTION(2, "CONN_MCU_TDO")
),
MTK_PIN(
- PINCTRL_PIN(48, "SPI_CS"),
- NULL, "mt8516",
+ 48, "SPI_CS",
MTK_EINT_FUNCTION(0, 48),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO48"),
MTK_FUNCTION(1, "SPI_CSB"),
MTK_FUNCTION(3, "I2S0_DI"),
@@ -527,9 +523,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[23]")
),
MTK_PIN(
- PINCTRL_PIN(49, "SPI_CK"),
- NULL, "mt8516",
+ 49, "SPI_CK",
MTK_EINT_FUNCTION(0, 49),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO49"),
MTK_FUNCTION(1, "SPI_CLK"),
MTK_FUNCTION(3, "I2S0_LRCK"),
@@ -537,9 +533,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[24]")
),
MTK_PIN(
- PINCTRL_PIN(50, "SPI_MI"),
- NULL, "mt8516",
+ 50, "SPI_MI",
MTK_EINT_FUNCTION(0, 50),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO50"),
MTK_FUNCTION(1, "SPI_MI"),
MTK_FUNCTION(2, "SPI_MO"),
@@ -548,9 +544,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[25]")
),
MTK_PIN(
- PINCTRL_PIN(51, "SPI_MO"),
- NULL, "mt8516",
+ 51, "SPI_MO",
MTK_EINT_FUNCTION(0, 51),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO51"),
MTK_FUNCTION(1, "SPI_MO"),
MTK_FUNCTION(2, "SPI_MI"),
@@ -559,31 +555,31 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[26]")
),
MTK_PIN(
- PINCTRL_PIN(52, "SDA1"),
- NULL, "mt8516",
+ 52, "SDA1",
MTK_EINT_FUNCTION(0, 52),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO52"),
MTK_FUNCTION(1, "SDA1_0")
),
MTK_PIN(
- PINCTRL_PIN(53, "SCL1"),
- NULL, "mt8516",
+ 53, "SCL1",
MTK_EINT_FUNCTION(0, 53),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO53"),
MTK_FUNCTION(1, "SCL1_0")
),
MTK_PIN(
- PINCTRL_PIN(54, "GPIO54"),
- NULL, "mt8516",
+ 54, "GPIO54",
MTK_EINT_FUNCTION(0, 54),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO54"),
MTK_FUNCTION(2, "PWM_B"),
MTK_FUNCTION(7, "DBG_MON_B[2]")
),
MTK_PIN(
- PINCTRL_PIN(55, "I2S_DATA_IN"),
- NULL, "mt8516",
+ 55, "I2S_DATA_IN",
MTK_EINT_FUNCTION(0, 55),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO55"),
MTK_FUNCTION(1, "I2S0_DI"),
MTK_FUNCTION(2, "UCTS0"),
@@ -594,9 +590,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[28]")
),
MTK_PIN(
- PINCTRL_PIN(56, "I2S_LRCK"),
- NULL, "mt8516",
+ 56, "I2S_LRCK",
MTK_EINT_FUNCTION(0, 56),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO56"),
MTK_FUNCTION(1, "I2S0_LRCK"),
MTK_FUNCTION(3, "I2S3_LRCK"),
@@ -606,9 +602,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[29]")
),
MTK_PIN(
- PINCTRL_PIN(57, "I2S_BCK"),
- NULL, "mt8516",
+ 57, "I2S_BCK",
MTK_EINT_FUNCTION(0, 57),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO57"),
MTK_FUNCTION(1, "I2S0_BCK"),
MTK_FUNCTION(2, "URTS0"),
@@ -619,90 +615,90 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[30]")
),
MTK_PIN(
- PINCTRL_PIN(58, "SDA0"),
- NULL, "mt8516",
+ 58, "SDA0",
MTK_EINT_FUNCTION(0, 58),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO58"),
MTK_FUNCTION(1, "SDA0_0")
),
MTK_PIN(
- PINCTRL_PIN(59, "SCL0"),
- NULL, "mt8516",
+ 59, "SCL0",
MTK_EINT_FUNCTION(0, 59),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO59"),
MTK_FUNCTION(1, "SCL0_0")
),
MTK_PIN(
- PINCTRL_PIN(60, "SDA2"),
- NULL, "mt8516",
+ 60, "SDA2",
MTK_EINT_FUNCTION(0, 60),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO60"),
MTK_FUNCTION(1, "SDA2_0"),
MTK_FUNCTION(2, "PWM_B")
),
MTK_PIN(
- PINCTRL_PIN(61, "SCL2"),
- NULL, "mt8516",
+ 61, "SCL2",
MTK_EINT_FUNCTION(0, 61),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO61"),
MTK_FUNCTION(1, "SCL2_0"),
MTK_FUNCTION(2, "PWM_C")
),
MTK_PIN(
- PINCTRL_PIN(62, "URXD0"),
- NULL, "mt8516",
+ 62, "URXD0",
MTK_EINT_FUNCTION(0, 62),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO62"),
MTK_FUNCTION(1, "URXD0"),
MTK_FUNCTION(2, "UTXD0")
),
MTK_PIN(
- PINCTRL_PIN(63, "UTXD0"),
- NULL, "mt8516",
+ 63, "UTXD0",
MTK_EINT_FUNCTION(0, 63),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO63"),
MTK_FUNCTION(1, "UTXD0"),
MTK_FUNCTION(2, "URXD0")
),
MTK_PIN(
- PINCTRL_PIN(64, "URXD1"),
- NULL, "mt8516",
+ 64, "URXD1",
MTK_EINT_FUNCTION(0, 64),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO64"),
MTK_FUNCTION(1, "URXD1"),
MTK_FUNCTION(2, "UTXD1"),
MTK_FUNCTION(7, "DBG_MON_A[27]")
),
MTK_PIN(
- PINCTRL_PIN(65, "UTXD1"),
- NULL, "mt8516",
+ 65, "UTXD1",
MTK_EINT_FUNCTION(0, 65),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO65"),
MTK_FUNCTION(1, "UTXD1"),
MTK_FUNCTION(2, "URXD1"),
MTK_FUNCTION(7, "DBG_MON_A[31]")
),
MTK_PIN(
- PINCTRL_PIN(66, "LCM_RST"),
- NULL, "mt8516",
+ 66, "LCM_RST",
MTK_EINT_FUNCTION(0, 66),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO66"),
MTK_FUNCTION(1, "LCM_RST"),
MTK_FUNCTION(3, "I2S0_MCK"),
MTK_FUNCTION(7, "DBG_MON_B[3]")
),
MTK_PIN(
- PINCTRL_PIN(67, "GPIO67"),
- NULL, "mt8516",
+ 67, "GPIO67",
MTK_EINT_FUNCTION(0, 67),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO67"),
MTK_FUNCTION(3, "I2S_8CH_MCK"),
MTK_FUNCTION(7, "DBG_MON_B[14]")
),
MTK_PIN(
- PINCTRL_PIN(68, "MSDC2_CMD"),
- NULL, "mt8516",
+ 68, "MSDC2_CMD",
MTK_EINT_FUNCTION(0, 68),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO68"),
MTK_FUNCTION(1, "MSDC2_CMD"),
MTK_FUNCTION(2, "I2S_8CH_DO4"),
@@ -712,9 +708,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[15]")
),
MTK_PIN(
- PINCTRL_PIN(69, "MSDC2_CLK"),
- NULL, "mt8516",
+ 69, "MSDC2_CLK",
MTK_EINT_FUNCTION(0, 69),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO69"),
MTK_FUNCTION(1, "MSDC2_CLK"),
MTK_FUNCTION(2, "I2S_8CH_DO3"),
@@ -724,9 +720,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[16]")
),
MTK_PIN(
- PINCTRL_PIN(70, "MSDC2_DAT0"),
- NULL, "mt8516",
+ 70, "MSDC2_DAT0",
MTK_EINT_FUNCTION(0, 70),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO70"),
MTK_FUNCTION(1, "MSDC2_DAT0"),
MTK_FUNCTION(2, "I2S_8CH_DO2"),
@@ -735,9 +731,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[17]")
),
MTK_PIN(
- PINCTRL_PIN(71, "MSDC2_DAT1"),
- NULL, "mt8516",
+ 71, "MSDC2_DAT1",
MTK_EINT_FUNCTION(0, 71),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO71"),
MTK_FUNCTION(1, "MSDC2_DAT1"),
MTK_FUNCTION(2, "I2S_8CH_DO1"),
@@ -748,9 +744,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[18]")
),
MTK_PIN(
- PINCTRL_PIN(72, "MSDC2_DAT2"),
- NULL, "mt8516",
+ 72, "MSDC2_DAT2",
MTK_EINT_FUNCTION(0, 72),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO72"),
MTK_FUNCTION(1, "MSDC2_DAT2"),
MTK_FUNCTION(2, "I2S_8CH_LRCK"),
@@ -760,9 +756,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[19]")
),
MTK_PIN(
- PINCTRL_PIN(73, "MSDC2_DAT3"),
- NULL, "mt8516",
+ 73, "MSDC2_DAT3",
MTK_EINT_FUNCTION(0, 73),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO73"),
MTK_FUNCTION(1, "MSDC2_DAT3"),
MTK_FUNCTION(2, "I2S_8CH_BCK"),
@@ -773,203 +769,203 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[20]")
),
MTK_PIN(
- PINCTRL_PIN(74, "TDN3"),
- NULL, "mt8516",
+ 74, "TDN3",
MTK_EINT_FUNCTION(0, 74),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO74"),
MTK_FUNCTION(1, "TDN3")
),
MTK_PIN(
- PINCTRL_PIN(75, "TDP3"),
- NULL, "mt8516",
+ 75, "TDP3",
MTK_EINT_FUNCTION(0, 75),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO75"),
MTK_FUNCTION(1, "TDP3")
),
MTK_PIN(
- PINCTRL_PIN(76, "TDN2"),
- NULL, "mt8516",
+ 76, "TDN2",
MTK_EINT_FUNCTION(0, 76),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO76"),
MTK_FUNCTION(1, "TDN2")
),
MTK_PIN(
- PINCTRL_PIN(77, "TDP2"),
- NULL, "mt8516",
+ 77, "TDP2",
MTK_EINT_FUNCTION(0, 77),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO77"),
MTK_FUNCTION(1, "TDP2")
),
MTK_PIN(
- PINCTRL_PIN(78, "TCN"),
- NULL, "mt8516",
+ 78, "TCN",
MTK_EINT_FUNCTION(0, 78),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO78"),
MTK_FUNCTION(1, "TCN")
),
MTK_PIN(
- PINCTRL_PIN(79, "TCP"),
- NULL, "mt8516",
+ 79, "TCP",
MTK_EINT_FUNCTION(0, 79),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO79"),
MTK_FUNCTION(1, "TCP")
),
MTK_PIN(
- PINCTRL_PIN(80, "TDN1"),
- NULL, "mt8516",
+ 80, "TDN1",
MTK_EINT_FUNCTION(0, 80),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO80"),
MTK_FUNCTION(1, "TDN1")
),
MTK_PIN(
- PINCTRL_PIN(81, "TDP1"),
- NULL, "mt8516",
+ 81, "TDP1",
MTK_EINT_FUNCTION(0, 81),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO81"),
MTK_FUNCTION(1, "TDP1")
),
MTK_PIN(
- PINCTRL_PIN(82, "TDN0"),
- NULL, "mt8516",
+ 82, "TDN0",
MTK_EINT_FUNCTION(0, 82),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO82"),
MTK_FUNCTION(1, "TDN0")
),
MTK_PIN(
- PINCTRL_PIN(83, "TDP0"),
- NULL, "mt8516",
+ 83, "TDP0",
MTK_EINT_FUNCTION(0, 83),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO83"),
MTK_FUNCTION(1, "TDP0")
),
MTK_PIN(
- PINCTRL_PIN(84, "RDN0"),
- NULL, "mt8516",
+ 84, "RDN0",
MTK_EINT_FUNCTION(0, 84),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO84"),
MTK_FUNCTION(1, "RDN0")
),
MTK_PIN(
- PINCTRL_PIN(85, "RDP0"),
- NULL, "mt8516",
+ 85, "RDP0",
MTK_EINT_FUNCTION(0, 85),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO85"),
MTK_FUNCTION(1, "RDP0")
),
MTK_PIN(
- PINCTRL_PIN(86, "RDN1"),
- NULL, "mt8516",
+ 86, "RDN1",
MTK_EINT_FUNCTION(0, 86),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO86"),
MTK_FUNCTION(1, "RDN1")
),
MTK_PIN(
- PINCTRL_PIN(87, "RDP1"),
- NULL, "mt8516",
+ 87, "RDP1",
MTK_EINT_FUNCTION(0, 87),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO87"),
MTK_FUNCTION(1, "RDP1")
),
MTK_PIN(
- PINCTRL_PIN(88, "RCN"),
- NULL, "mt8516",
+ 88, "RCN",
MTK_EINT_FUNCTION(0, 88),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO88"),
MTK_FUNCTION(1, "RCN")
),
MTK_PIN(
- PINCTRL_PIN(89, "RCP"),
- NULL, "mt8516",
+ 89, "RCP",
MTK_EINT_FUNCTION(0, 89),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO89"),
MTK_FUNCTION(1, "RCP")
),
MTK_PIN(
- PINCTRL_PIN(90, "RDN2"),
- NULL, "mt8516",
+ 90, "RDN2",
MTK_EINT_FUNCTION(0, 90),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO90"),
MTK_FUNCTION(1, "RDN2"),
MTK_FUNCTION(2, "CMDAT8")
),
MTK_PIN(
- PINCTRL_PIN(91, "RDP2"),
- NULL, "mt8516",
+ 91, "RDP2",
MTK_EINT_FUNCTION(0, 91),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO91"),
MTK_FUNCTION(1, "RDP2"),
MTK_FUNCTION(2, "CMDAT9")
),
MTK_PIN(
- PINCTRL_PIN(92, "RDN3"),
- NULL, "mt8516",
+ 92, "RDN3",
MTK_EINT_FUNCTION(0, 92),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO92"),
MTK_FUNCTION(1, "RDN3"),
MTK_FUNCTION(2, "CMDAT4")
),
MTK_PIN(
- PINCTRL_PIN(93, "RDP3"),
- NULL, "mt8516",
+ 93, "RDP3",
MTK_EINT_FUNCTION(0, 93),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO93"),
MTK_FUNCTION(1, "RDP3"),
MTK_FUNCTION(2, "CMDAT5")
),
MTK_PIN(
- PINCTRL_PIN(94, "RCN_A"),
- NULL, "mt8516",
+ 94, "RCN_A",
MTK_EINT_FUNCTION(0, 94),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO94"),
MTK_FUNCTION(1, "RCN_A"),
MTK_FUNCTION(2, "CMDAT6")
),
MTK_PIN(
- PINCTRL_PIN(95, "RCP_A"),
- NULL, "mt8516",
+ 95, "RCP_A",
MTK_EINT_FUNCTION(0, 95),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO95"),
MTK_FUNCTION(1, "RCP_A"),
MTK_FUNCTION(2, "CMDAT7")
),
MTK_PIN(
- PINCTRL_PIN(96, "RDN1_A"),
- NULL, "mt8516",
+ 96, "RDN1_A",
MTK_EINT_FUNCTION(0, 96),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO96"),
MTK_FUNCTION(1, "RDN1_A"),
MTK_FUNCTION(2, "CMDAT2"),
MTK_FUNCTION(3, "CMCSD2")
),
MTK_PIN(
- PINCTRL_PIN(97, "RDP1_A"),
- NULL, "mt8516",
+ 97, "RDP1_A",
MTK_EINT_FUNCTION(0, 97),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO97"),
MTK_FUNCTION(1, "RDP1_A"),
MTK_FUNCTION(2, "CMDAT3"),
MTK_FUNCTION(3, "CMCSD3")
),
MTK_PIN(
- PINCTRL_PIN(98, "RDN0_A"),
- NULL, "mt8516",
+ 98, "RDN0_A",
MTK_EINT_FUNCTION(0, 98),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO98"),
MTK_FUNCTION(1, "RDN0_A"),
MTK_FUNCTION(2, "CMHSYNC")
),
MTK_PIN(
- PINCTRL_PIN(99, "RDP0_A"),
- NULL, "mt8516",
+ 99, "RDP0_A",
MTK_EINT_FUNCTION(0, 99),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO99"),
MTK_FUNCTION(1, "RDP0_A"),
MTK_FUNCTION(2, "CMVSYNC")
),
MTK_PIN(
- PINCTRL_PIN(100, "CMDAT0"),
- NULL, "mt8516",
+ 100, "CMDAT0",
MTK_EINT_FUNCTION(0, 100),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO100"),
MTK_FUNCTION(1, "CMDAT0"),
MTK_FUNCTION(2, "CMCSD0"),
@@ -978,9 +974,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[21]")
),
MTK_PIN(
- PINCTRL_PIN(101, "CMDAT1"),
- NULL, "mt8516",
+ 101, "CMDAT1",
MTK_EINT_FUNCTION(0, 101),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO101"),
MTK_FUNCTION(1, "CMDAT1"),
MTK_FUNCTION(2, "CMCSD1"),
@@ -990,9 +986,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[22]")
),
MTK_PIN(
- PINCTRL_PIN(102, "CMMCLK"),
- NULL, "mt8516",
+ 102, "CMMCLK",
MTK_EINT_FUNCTION(0, 102),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO102"),
MTK_FUNCTION(1, "CMMCLK"),
MTK_FUNCTION(3, "ANT_SEL4"),
@@ -1000,181 +996,181 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[23]")
),
MTK_PIN(
- PINCTRL_PIN(103, "CMPCLK"),
- NULL, "mt8516",
+ 103, "CMPCLK",
MTK_EINT_FUNCTION(0, 103),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO103"),
MTK_FUNCTION(1, "CMPCLK"),
MTK_FUNCTION(2, "CMCSK"),
MTK_FUNCTION(3, "ANT_SEL5"),
- MTK_FUNCTION(5, " TDM_RX_DI"),
+ MTK_FUNCTION(5, "TDM_RX_DI"),
MTK_FUNCTION(7, "DBG_MON_B[24]")
),
MTK_PIN(
- PINCTRL_PIN(104, "MSDC1_CMD"),
- NULL, "mt8516",
+ 104, "MSDC1_CMD",
MTK_EINT_FUNCTION(0, 104),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO104"),
MTK_FUNCTION(1, "MSDC1_CMD"),
MTK_FUNCTION(4, "SQICS"),
MTK_FUNCTION(7, "DBG_MON_B[25]")
),
MTK_PIN(
- PINCTRL_PIN(105, "MSDC1_CLK"),
- NULL, "mt8516",
+ 105, "MSDC1_CLK",
MTK_EINT_FUNCTION(0, 105),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO105"),
MTK_FUNCTION(1, "MSDC1_CLK"),
MTK_FUNCTION(4, "SQISO"),
MTK_FUNCTION(7, "DBG_MON_B[26]")
),
MTK_PIN(
- PINCTRL_PIN(106, "MSDC1_DAT0"),
- NULL, "mt8516",
+ 106, "MSDC1_DAT0",
MTK_EINT_FUNCTION(0, 106),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO106"),
MTK_FUNCTION(1, "MSDC1_DAT0"),
MTK_FUNCTION(4, "SQISI"),
MTK_FUNCTION(7, "DBG_MON_B[27]")
),
MTK_PIN(
- PINCTRL_PIN(107, "MSDC1_DAT1"),
- NULL, "mt8516",
+ 107, "MSDC1_DAT1",
MTK_EINT_FUNCTION(0, 107),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO107"),
MTK_FUNCTION(1, "MSDC1_DAT1"),
MTK_FUNCTION(4, "SQIWP"),
MTK_FUNCTION(7, "DBG_MON_B[28]")
),
MTK_PIN(
- PINCTRL_PIN(108, "MSDC1_DAT2"),
- NULL, "mt8516",
+ 108, "MSDC1_DAT2",
MTK_EINT_FUNCTION(0, 108),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO108"),
MTK_FUNCTION(1, "MSDC1_DAT2"),
MTK_FUNCTION(4, "SQIRST"),
MTK_FUNCTION(7, "DBG_MON_B[29]")
),
MTK_PIN(
- PINCTRL_PIN(109, "MSDC1_DAT3"),
- NULL, "mt8516",
+ 109, "MSDC1_DAT3",
MTK_EINT_FUNCTION(0, 109),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO109"),
MTK_FUNCTION(1, "MSDC1_DAT3"),
- MTK_FUNCTION(4, "SQICK"), /* WIP */
+ MTK_FUNCTION(4, "SQICK"),
MTK_FUNCTION(7, "DBG_MON_B[30]")
),
MTK_PIN(
- PINCTRL_PIN(110, "MSDC0_DAT7"),
- NULL, "mt8516",
+ 110, "MSDC0_DAT7",
MTK_EINT_FUNCTION(0, 110),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO110"),
MTK_FUNCTION(1, "MSDC0_DAT7"),
MTK_FUNCTION(4, "NLD7")
),
MTK_PIN(
- PINCTRL_PIN(111, "MSDC0_DAT6"),
- NULL, "mt8516",
+ 111, "MSDC0_DAT6",
MTK_EINT_FUNCTION(0, 111),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO111"),
MTK_FUNCTION(1, "MSDC0_DAT6"),
MTK_FUNCTION(4, "NLD6")
),
MTK_PIN(
- PINCTRL_PIN(112, "MSDC0_DAT5"),
- NULL, "mt8516",
+ 112, "MSDC0_DAT5",
MTK_EINT_FUNCTION(0, 112),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO112"),
MTK_FUNCTION(1, "MSDC0_DAT5"),
MTK_FUNCTION(4, "NLD4")
),
MTK_PIN(
- PINCTRL_PIN(113, "MSDC0_DAT4"),
- NULL, "mt8516",
+ 113, "MSDC0_DAT4",
MTK_EINT_FUNCTION(0, 113),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO113"),
MTK_FUNCTION(1, "MSDC0_DAT4"),
MTK_FUNCTION(4, "NLD3")
),
MTK_PIN(
- PINCTRL_PIN(114, "MSDC0_RSTB"),
- NULL, "mt8516",
+ 114, "MSDC0_RSTB",
MTK_EINT_FUNCTION(0, 114),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO114"),
MTK_FUNCTION(1, "MSDC0_RSTB"),
MTK_FUNCTION(4, "NLD0")
),
MTK_PIN(
- PINCTRL_PIN(115, "MSDC0_CMD"),
- NULL, "mt8516",
+ 115, "MSDC0_CMD",
MTK_EINT_FUNCTION(0, 115),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO115"),
MTK_FUNCTION(1, "MSDC0_CMD"),
MTK_FUNCTION(4, "NALE")
),
MTK_PIN(
- PINCTRL_PIN(116, "MSDC0_CLK"),
- NULL, "mt8516",
+ 116, "MSDC0_CLK",
MTK_EINT_FUNCTION(0, 116),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO116"),
MTK_FUNCTION(1, "MSDC0_CLK"),
MTK_FUNCTION(4, "NWEB")
),
MTK_PIN(
- PINCTRL_PIN(117, "MSDC0_DAT3"),
- NULL, "mt8516",
+ 117, "MSDC0_DAT3",
MTK_EINT_FUNCTION(0, 117),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO117"),
MTK_FUNCTION(1, "MSDC0_DAT3"),
MTK_FUNCTION(4, "NLD1")
),
MTK_PIN(
- PINCTRL_PIN(118, "MSDC0_DAT2"),
- NULL, "mt8516",
+ 118, "MSDC0_DAT2",
MTK_EINT_FUNCTION(0, 118),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO118"),
MTK_FUNCTION(1, "MSDC0_DAT2"),
MTK_FUNCTION(4, "NLD5")
),
MTK_PIN(
- PINCTRL_PIN(119, "MSDC0_DAT1"),
- NULL, "mt8516",
+ 119, "MSDC0_DAT1",
MTK_EINT_FUNCTION(0, 119),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO119"),
MTK_FUNCTION(1, "MSDC0_DAT1"),
MTK_FUNCTION(4, "NLD8")
),
MTK_PIN(
- PINCTRL_PIN(120, "MSDC0_DAT0"),
- NULL, "mt8516",
+ 120, "MSDC0_DAT0",
MTK_EINT_FUNCTION(0, 120),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO120"),
MTK_FUNCTION(1, "MSDC0_DAT0"),
MTK_FUNCTION(4, "WATCHDOG"),
MTK_FUNCTION(5, "NLD2")
),
MTK_PIN(
- PINCTRL_PIN(121, "GPIO121"),
- NULL, "mt8516",
+ 121, "GPIO121",
MTK_EINT_FUNCTION(0, 121),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO121")
),
MTK_PIN(
- PINCTRL_PIN(122, "GPIO122"),
- NULL, "mt8516",
+ 122, "GPIO122",
MTK_EINT_FUNCTION(0, 122),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO122")
),
MTK_PIN(
- PINCTRL_PIN(123, "GPIO123"),
- NULL, "mt8516",
+ 123, "GPIO123",
MTK_EINT_FUNCTION(0, 123),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO123")
),
MTK_PIN(
- PINCTRL_PIN(124, "GPIO124"),
- NULL, "mt8516",
+ 124, "GPIO124",
MTK_EINT_FUNCTION(0, 124),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO124")
),
};
--
2.43.0
^ permalink raw reply related
* [RFC PATCH 1/3] dt-bindings: pinctrl: mt8516/mt8167: Move compatibles from mt66xx to mt6795
From: Luca Leonardo Scorcia @ 2026-06-25 10:46 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Sean Wang, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260625104742.113803-1-l.scorcia@gmail.com>
Pinctrl settings for MediaTek mt8516-mt8167 SoCs use two reg base
addresses, one for GPIO and the other for EINT, as it is common in the
"Paris" pinctrl platform that is described in the MediaTek mt6795 docs.
Move the binding compatible for these two SoCs from mt66xx to the mt6796
one as a prerequisite for migrating the pinctrl driver to the
pinctrl-paris platform.
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
.../devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 2 --
.../devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml | 5 ++++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
index 1468c6f87cfa..0cff2a352b1f 100644
--- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
@@ -22,9 +22,7 @@ properties:
- mediatek,mt7623-pinctrl
- mediatek,mt8127-pinctrl
- mediatek,mt8135-pinctrl
- - mediatek,mt8167-pinctrl
- mediatek,mt8173-pinctrl
- - mediatek,mt8516-pinctrl
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
index 9a937f414cc9..c703de72e1d5 100644
--- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
@@ -15,7 +15,10 @@ description:
properties:
compatible:
- const: mediatek,mt6795-pinctrl
+ enum:
+ - mediatek,mt6795-pinctrl
+ - mediatek,mt8167-pinctrl
+ - mediatek,mt8516-pinctrl
gpio-controller: true
--
2.43.0
^ permalink raw reply related
* [RFC PATCH 0/3] pinctrl: mediatek: mt8516-mt8167: Convert to Paris driver
From: Luca Leonardo Scorcia @ 2026-06-25 10:46 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Sean Wang, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
The pinctrl registers of the mt8516 and mt8167 SoCs follow the layout of
the Paris platform, but their pinctrl driver is currently modeled on
the mt65xx legacy driver. As suggested in [1], it is possible to migrate
them to the Paris driver.
In the process it is also possible to completely drop one of the two
drivers as their register layout is identical, they only differ in some
pin functions (mt8167 is basically mt8516 with added display blocks).
The Paris driver allows specifying two base registers, gpio and eint;
this way it's no longer necessary to have a syscfg node in the device
tree, referenced as a phandle in the pinctrl node. This also fixes the
following long standing dtbs_check errors:
mt8167-pumpkin.dtb: syscfg-pctl@10005000 (syscon): compatible: ['syscon']
is too short
mt8516-pumpkin.dtb: syscfg-pctl@10005000 (syscon): compatible: ['syscon']
is too short
The new driver has been checked against the SoC data sheet and adds the
capability to control pin driving strength and R1R0 pullup-pulldown
resistors.
This series is sent as a RFC since the changes could theoretically impact
existing devices. I am pretty sure that no device ever used upstream
drivers though, not even the Pumpkin board that's present in Linux
sources since this board lacks the associated mt6392 PMIC driver that
is required for regulator management. If for compatibility reasons it is
deemed better to keep both drivers in the kernel I would welcome any
suggestion on how to name the new driver, and how to adjust the two
bindings for coexistence.
These changes have been tested on the Xiaomi Mi Smart Clock X04G and on
the Lenovo Smart Clock 2 CD-24502F.
[1] https://lore.kernel.org/linux-mediatek/296b000c-5970-4668-bd42-b99ca78d598f@collabora.com/
Luca Leonardo Scorcia (3):
dt-bindings: pinctrl: mt8516/mt8167: Move compatibles from mt66xx to
mt6795
pinctrl: mediatek: mt8516/mt8167: Migrate driver to pinctrl-paris
platform
arm64: dts: mt8516/mt8167: Update pinctrl nodes for the new paris
driver
.../pinctrl/mediatek,mt65xx-pinctrl.yaml | 2 -
.../pinctrl/mediatek,mt6795-pinctrl.yaml | 5 +-
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 15 +-
arch/arm64/boot/dts/mediatek/mt8516.dtsi | 12 +-
drivers/pinctrl/mediatek/Kconfig | 11 +-
drivers/pinctrl/mediatek/Makefile | 1 -
drivers/pinctrl/mediatek/pinctrl-mt8167.c | 345 --------
drivers/pinctrl/mediatek/pinctrl-mt8516.c | 770 +++++++++++-------
drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h | 562 +++++++------
drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h | 512 ++++++------
10 files changed, 1018 insertions(+), 1217 deletions(-)
delete mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8167.c
base-commit: 4e5dfb7c84012007c3c7061126491bbc92d71bf1
--
2.43.0
^ permalink raw reply
* Re: [PATCH v3 5/8] irqchip/qcom-pdc: Configure PDC to pass through mode
From: Maulik Shah (mkshah) @ 2026-06-25 9:25 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thomas Gleixner, Linus Walleij
Cc: linux-arm-msm, linux-kernel, devicetree, linux-gpio, Sneh Mankad
In-Reply-To: <c90884fd-a354-45f3-bbfa-77c58d8d3b1b@oss.qualcomm.com>
On 6/18/2026 1:49 PM, Konrad Dybcio wrote:
> On 6/16/26 11:25 AM, Maulik Shah wrote:
[...]
>> +
>> + if (pdc->version < PDC_VERSION_3_0)
>> + return;
>
> These version checks should be unnecessary now, given the function pointer
> is only assigned for hamoa
>
> Konrad
Yes, they are now unnecessary. I will remove in v4.
Thanks,
Maulik
^ permalink raw reply
* Re: [PATCH v3 5/8] irqchip/qcom-pdc: Configure PDC to pass through mode
From: Maulik Shah (mkshah) @ 2026-06-25 9:24 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thomas Gleixner, Linus Walleij
Cc: linux-arm-msm, linux-kernel, devicetree, linux-gpio, Sneh Mankad
In-Reply-To: <e513bc4c-ddeb-43b3-aa05-59051136ba4e@oss.qualcomm.com>
On 6/18/2026 1:48 PM, Konrad Dybcio wrote:
> On 6/16/26 11:25 AM, Maulik Shah wrote:
[...]
>> + type = IRQ_TYPE_LEVEL_HIGH;
>
>
> Please carry your comment from the previous revision:
>
> /*
> * PDC forwards GPIOs as level high to GIC in secondary
> * mode. Update the type and clear any previously latched
> * phantom interrupt at PDC.
> */
>
I will add back this comment in v4.
[...]
>> + if (pdc->mode == PDC_PASS_THROUGH_MODE || !pdc_pin_is_gpio(hwirq)) {
>> + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
>> + &qcom_pdc_gic_chip,
>> + NULL);
>> + if (ret)
>> + return ret;
>>
>> - region = get_pin_region(hwirq);
>> - if (!region)
>> - return irq_domain_disconnect_hierarchy(domain->parent, virq);
>> + if (type & IRQ_TYPE_EDGE_BOTH)
>> + type = IRQ_TYPE_EDGE_RISING;
>>
>> - if (type & IRQ_TYPE_EDGE_BOTH)
>> - type = IRQ_TYPE_EDGE_RISING;
>> + if (type & IRQ_TYPE_LEVEL_MASK)
>> + type = IRQ_TYPE_LEVEL_HIGH;
>> + } else {
>> + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
>> + &qcom_pdc_gic_secondary_chip,
>> + NULL);
>> + if (ret)
>> + return ret;
>>
>> - if (type & IRQ_TYPE_LEVEL_MASK)
>> + /* Secondary mode converts all interrupts to LEVEL HIGH type */
>> type = IRQ_TYPE_LEVEL_HIGH;
>> + }
>
> nit: (pdc->mode == PDC_SECONDARY_MODE && pdc_pin_is_gpio(hwirq))
> could be the primary case to better communicate intent
>
> Konrad
Made primary case as (pdc->mode == PDC_SECONDARY_MODE && pdc_pin_is_gpio(hwirq) in v4.
Thanks,
Maulik
^ permalink raw reply
* Re: [PATCH v3 4/8] irqchip/qcom-pdc: Differentiate between direct SPI and GPIO as SPI
From: Maulik Shah (mkshah) @ 2026-06-25 9:20 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thomas Gleixner, Linus Walleij
Cc: linux-arm-msm, linux-kernel, devicetree, linux-gpio, Sneh Mankad
In-Reply-To: <2978f55b-0b5c-4720-98ba-e14ef46b1169@oss.qualcomm.com>
On 6/18/2026 1:32 PM, Konrad Dybcio wrote:
> On 6/16/26 11:25 AM, Maulik Shah wrote:
>> Before commit 4dc70713dc24 ("irqchip/qcom-pdc: Kill non-wakeup irqdomain")
>> there are separate domains for direct SPIs and GPIO used as SPIs. Separate
>> domains can be useful in case irqchip want to differentiate both of them.
>> Since commit unified both the domains there is no way to differentiate.
>>
>> In preparation to add the second level interrupt controller support where
>> GPIO interrupts get latched at PDC (but not direct SPIs) there is a need to
>> differentiate between SPIs and GPIOs as SPIs. Reverting above commit do not
>> seem a good option either which leads to waste of resources.
>>
>> PDC HW have the IRQ_PARAM register telling number of direct SPIs and number
>> of GPIOs as SPIs. Further PDC allocates direct SPIs at the beginning and
>> all GPIOs as SPIs are allocated at the end. This information can be used in
>> driver to differentiate them.
>>
>> Add the support to read this register and keep this information in
>> struct pdc_desc. Later change utilizes same.
>>
>> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
>> ---
>
> [...]
>
>> + irq_param = pdc_reg_read(pdc->regs->irq_param_reg, 0);
>> + pdc->num_spis = FIELD_GET(GENMASK(7, 0), irq_param);
>> + pdc->num_gpios = FIELD_GET(GENMASK(15, 8), irq_param);
>
> num_gpios is not used in this series, please either drop it or
> use it to limit the index in the following patches
>
> Konrad
I will remove unused num_gpios from v4.
Thanks,
Maulik
^ permalink raw reply
* Re: [PATCH v3 2/8] irqchip/qcom-pdc: Move all statics to struct pdc_desc
From: Maulik Shah (mkshah) @ 2026-06-25 9:19 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thomas Gleixner, Linus Walleij
Cc: linux-arm-msm, linux-kernel, devicetree, linux-gpio, Sneh Mankad
In-Reply-To: <8754de51-bfbe-42f2-84bf-36cc000afa3f@oss.qualcomm.com>
On 6/17/2026 6:56 PM, Konrad Dybcio wrote:
> On 6/16/26 11:25 AM, Maulik Shah wrote:
>> There are multiple statics used. Move all to struct pdc_desc to better
>> align with versioning support. Document them.
>>
>> No functional impact.
>>
>> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
>> ---
>
> [...]
>
>> static void pdc_enable_intr(struct irq_data *d, bool on)
>> {
>> - unsigned long flags;
>> + guard(raw_spinlock)(&pdc->lock);
>
> tglx suggested to use guard(irq) around "the other callsite"..
> which I'm not sure where it'd be - maybe around __pdc_enable_intr()
> in pdc_setup_pin_mapping()?
>
> Otherwise this patch looks good to me
>
> Konrad
All callers will be from irqchip except pdc_setup_pin_mapping() which was
invoking lock-less because at that time irqchip is not setup and as such
can stay lock less.
Once the patch-3 of this series is applied pdc_setup_pin_mapping() too
will use the lock as it makes direct use of pdc->enable_intr() where the new lock
is kept (only for v2.7 version specific enable function).
Thanks,
Maulik
^ permalink raw reply
* Re: [PATCH v3 1/8] irqchip/qcom-pdc: restructure version support
From: Maulik Shah (mkshah) @ 2026-06-25 9:19 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thomas Gleixner, Linus Walleij
Cc: linux-arm-msm, linux-kernel, devicetree, linux-gpio, Sneh Mankad
In-Reply-To: <0fcfe7c3-ff54-4a72-9529-8f55d77814ef@oss.qualcomm.com>
On 6/17/2026 6:42 PM, Konrad Dybcio wrote:
> On 6/16/26 11:25 AM, Maulik Shah wrote:
>> PDC irqchip updates IRQ_ENABLE and IRQ_CFG and for three different
>> versions v2.7, v3.0 and v3.2. These registers are organized in H/W
>> as below on various SoCs.
>
> [...]
>
>> - ret = pdc_setup_pin_mapping(node);
>> + ret = pdc_setup_pin_mapping(dev, node);
>
> dev is enough, we can get the np in that function from dev->of_node
>
> otherwise:
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Konrad
Sure, Will update in v4 for getting np from dev->of_node.
Thanks,
Maulik
^ permalink raw reply
* [GIT PULL] gpio fixes for v7.2-rc1
From: Bartosz Golaszewski @ 2026-06-25 9:07 UTC (permalink / raw)
To: Linus Torvalds
Cc: Linus Walleij, linux-gpio, linux-kernel, brgl,
Bartosz Golaszewski
Linus,
Here's the second PR for this merge window. It's mostly fixes except for one
commit that requires some explanation.
During the last cycle I submitted a two-patch series with the first changeset
exposing the software node of the GPIO cell of the cs5535 MFD device in
a public header, and the second one using it in the Intel Geode board file[1].
Lee Jones picked up patch 1/2 into the MFD tree. I later got an Ack from
Borislav on patch 2/2 and decided to queue it for v7.2 as it's the last
remaining change that will allow me to drop the deprecated behavior of GPIO
core for software-node lookup by GPIO label match for v7.3.
To that end, however, I needed the prerequisite patch 1/2 from the MFD tree to
land upstream. At that point I had already more patches queued in my tree.
I was not sure whether the correct approach in this case is to:
a) Pull Lee's tag directly into my tree
b) Pull your merge commit
c) Rebase my branch and force-push
I decided to go with b) as it doesn't result in two merges of the same tag in
git history. I typically never rebase my branches fed into linux-next. Please
let me know if this is not the right approach. If you don't comment on it, I'll
assume it's ok. In any case, this was exceptional and should not be a common
occurrence.
Please consider pulling.
Thanks,
Bartosz
[1] https://lore.kernel.org/all/20260429-cs5535-swnode-v1-0-2bc5e17ddcf9@oss.qualcomm.com/
The following changes since commit 6beaec3aee9852438b89e4d7891caf5e84d45851:
Merge tag 'mfd-next-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd (2026-06-18 14:26:29 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git tags/gpio-fixes-for-v7.2-rc1
for you to fetch changes up to 4e8eb6952aa6749726c6c3763ae0032a6332c24f:
gpio: davinci: fix IRQ domain leak on devm_kzalloc failure (2026-06-23 10:44:29 +0200)
----------------------------------------------------------------
gpio fixes for v7.2-rc1
- fix locking context with shared GPIOs in gpio-tegra
- fix IRQ domain leak in error path in gpio-davinci
- fix returning a potentially uninitialized integer in
gpiochip_set_multiple()
- use raw spinlock in gpio-eic-sprd and gpio-sch to address locking
context issues
- bail out of probe() if registering the GPIO chip fails in gpio-mlxbf3
- fix varible type for storing the "ngpios" property in gpio-pisosr
- fix out-of-bounds pin access in GPIO ACPI
- make GPIO ACPI core only trigger interrupts on boot that are marked as
ActiveBoth
- fix kerneldoc in gpio-tb10x
- reference the real software node of the cs5535 GPIO controller in
Geode board file
----------------------------------------------------------------
Bartosz Golaszewski (3):
Merge tag 'intel-gpio-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into gpio/for-current
Merge commit '6beaec3aee9852438b89e4d7891caf5e84d45851' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-current
x86/platform/geode: reference the real node of the cs5535 GPIO controller
Igor Putko (1):
gpio: tb10x: fix struct tb10x_gpio kernel-doc
Marco Scardovi (2):
gpiolib: acpi: Add robust bounds-checking for GPIO pin resources
gpiolib: acpi: Prevent out-of-bounds pin access in OperationRegion handler
Mario Limonciello (1):
gpiolib: acpi: Only trigger ActiveBoth interrupts on boot
Pengpeng Hou (1):
gpio: mlxbf3: fail probe if gpiochip registration fails
Qingshuang Fu (1):
gpio: davinci: fix IRQ domain leak on devm_kzalloc failure
Rob Herring (Arm) (1):
gpio: pisosr: Read "ngpios" as u32
Runyu Xiao (3):
gpio: sch: use raw_spinlock_t in the irq startup path
gpio: eic-sprd: use raw_spinlock_t in the irq startup path
gpio: tegra: do not call pinctrl for GPIO direction
Ruoyu Wang (1):
gpiolib: initialize return value in gpiochip_set_multiple()
arch/x86/Kconfig | 10 +++---
arch/x86/platform/geode/geode-common.c | 12 +++----
drivers/gpio/gpio-davinci.c | 4 ++-
drivers/gpio/gpio-eic-sprd.c | 8 ++---
drivers/gpio/gpio-mlxbf3.c | 3 +-
drivers/gpio/gpio-pisosr.c | 4 ++-
drivers/gpio/gpio-sch.c | 32 +++++++++----------
drivers/gpio/gpio-tb10x.c | 1 +
drivers/gpio/gpio-tegra.c | 18 ++---------
drivers/gpio/gpiolib-acpi-core.c | 57 +++++++++++++++++++++++++++-------
drivers/gpio/gpiolib.c | 2 +-
11 files changed, 87 insertions(+), 64 deletions(-)
^ permalink raw reply
* Re: [PATCH] pinctrl: imx1: fix device_node leak in dt_is_flat_functions()
From: Linus Walleij @ 2026-06-25 8:04 UTC (permalink / raw)
To: Felix Gu
Cc: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Sascha Hauer,
linux-gpio, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <20260523-pinctrl-imx-v1-1-73b7cb731351@gmail.com>
On Sat, May 23, 2026 at 12:27 PM Felix Gu <ustc.gu@gmail.com> wrote:
> for_each_child_of_node() holds a reference on the iterator node that
> must be released on early return. imx1_pinctrl_dt_is_flat_functions()
> has two early return paths inside the loop that skip this cleanup.
>
> Replace both loops with the scoped variant so that the reference is
> automatically dropped when the iterator goes out of scope.
>
> Fixes: 63d2059cd665 ("pinctrl: imx1: Allow parsing DT without function nodes")
> Signed-off-by: Felix Gu <ustc.gu@gmail.com>
Patch applied for v7.3!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3] pinctrl: qcom: Unconditionally mark gpio as wakeup enable
From: Konrad Dybcio @ 2026-06-25 7:59 UTC (permalink / raw)
To: Sneh Mankad, Bjorn Andersson, Linus Walleij, Neil Armstrong,
Krzysztof Kozlowski
Cc: linux-arm-msm, linux-gpio, linux-kernel, stable, Maulik Shah
In-Reply-To: <37f34aff-c68f-43ca-b23c-500cc9bb119e@oss.qualcomm.com>
On 6/25/26 6:33 AM, Sneh Mankad wrote:
>
>
> [...]
>>
>> This is a much better commit message, thank you!
>>
>> One question remains - should we set skip_wake_irqs for MPM too?
>>
>> My understanding is that no, since the MPM HW is simpler and doesn't
>> have a register for acking IRQs, so we need to do it from the recipient
>> (TLMM). Is that right?
>>
> Yes that is correct. skip_wake_irqs is set for PDC since PDC can handle interrupts
> during active time and SoC sleep time both, so any wakeup capable interrupt source can
> be handled via PDC at all times. However MPM can only handle interrupts when
> SoC is in low power mode, it does not have the functionality to detect them when SoC
> is active. skip_wake_irqs differentiates this behaviour.
Thank you!
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [RFC] pinctrl: ingenic: impossible MACH_* guards can drop OF match data
From: H. Nikolaus Schaller @ 2026-06-25 6:28 UTC (permalink / raw)
To: Pengpeng Hou
Cc: Paul Cercueil, Linus Walleij, linux-mips, linux-gpio,
linux-kernel, Discussions about the Letux Kernel
In-Reply-To: <20260625060959.17290-1-pengpeng@iscas.ac.cn>
Hi,
Since I am just these days working to extend the ingenic-pinctrl driver for x2600
support, I can comment from a distribution kernel perspective.
> Am 25.06.2026 um 08:09 schrieb Pengpeng Hou <pengpeng@iscas.ac.cn>:
>
> Hi,
>
> while auditing conditional data-provider paths, I noticed that
> drivers/pinctrl/pinctrl-ingenic.c still derives some SoC descriptor exposure
> from IS_ENABLED(CONFIG_MACH_*) style conditions whose corresponding Kconfig
> symbols do not appear to exist in the current Ingenic Kconfig universe.
>
> This looks like a data-symbol legality issue rather than a simple cleanup:
> the OF match table .data entries carry SoC-specific pinctrl descriptors. If
The idea is that you can choose through CONFIG_MACH_* which records are
included in the match table at all to be able to shrink the driver to a bare
minimum for embedded use (e.g. X1600 with just 32 MB RAM).
Or have a full driver for a distribution kernel which supports all options by a
full driver (module).
Currently we have in the LetuxOS kernel:
grep -e "CONFIG_MACH_JZ" -e "CONFIG_MACH_X" .config
CONFIG_MACH_JZ4725B=y
CONFIG_MACH_JZ4730=y
CONFIG_MACH_JZ4740=y
CONFIG_MACH_JZ4770=y
CONFIG_MACH_JZ4780=y
CONFIG_MACH_X1000=y
CONFIG_MACH_X1600=y
CONFIG_MACH_X1830=y
CONFIG_MACH_X2000=y
CONFIG_MACH_X2600=y
> the guard can never be true, a compatible string can lose the intended
> descriptor provider even though the descriptor is still present in source.
>
> I am not sending a patch yet because the correct policy is not obvious. The
> possible directions include:
>
> 1. remove impossible MACH_* gates from the OF match data;
> 2. restore current Kconfig symbols for the intended SoC families;
> 3. split unsupported legacy SoCs from supported descriptor exposure; or
> 4. keep the gates and document that these descriptors are intentionally not
> exposed.
5. keep it as is and wait until we can upstream some missing SoC families.
(BTW: can you list what you think is unsupported legacy or impossible please?)
>
> Could you confirm which direction matches the current Ingenic pinctrl support
> policy?
>
> This is static source/Kconfig analysis only. I have not tested the affected
> hardware.
>
> Thanks,
> Pengpeng
Hope this helps the maintainers to decide.
BR,
Nikolaus
^ permalink raw reply
* [RFC] pinctrl: ingenic: impossible MACH_* guards can drop OF match data
From: Pengpeng Hou @ 2026-06-25 6:09 UTC (permalink / raw)
To: Paul Cercueil, Linus Walleij
Cc: linux-mips, linux-gpio, linux-kernel, Pengpeng Hou
Hi,
while auditing conditional data-provider paths, I noticed that
drivers/pinctrl/pinctrl-ingenic.c still derives some SoC descriptor exposure
from IS_ENABLED(CONFIG_MACH_*) style conditions whose corresponding Kconfig
symbols do not appear to exist in the current Ingenic Kconfig universe.
This looks like a data-symbol legality issue rather than a simple cleanup:
the OF match table .data entries carry SoC-specific pinctrl descriptors. If
the guard can never be true, a compatible string can lose the intended
descriptor provider even though the descriptor is still present in source.
I am not sending a patch yet because the correct policy is not obvious. The
possible directions include:
1. remove impossible MACH_* gates from the OF match data;
2. restore current Kconfig symbols for the intended SoC families;
3. split unsupported legacy SoCs from supported descriptor exposure; or
4. keep the gates and document that these descriptors are intentionally not
exposed.
Could you confirm which direction matches the current Ingenic pinctrl support
policy?
This is static source/Kconfig analysis only. I have not tested the affected
hardware.
Thanks,
Pengpeng
^ permalink raw reply
* Re: [PATCH v2 0/1] gpiolib: acpi: Add quirk for ASUS ROG Strix G16 G614 series
From: Andy Shevchenko @ 2026-06-25 6:08 UTC (permalink / raw)
To: Marco Scardovi
Cc: w_armin, bnatikar, brgl, johannes.goede, linusw, linux-acpi,
linux-gpio, linux-kernel, mario.limonciello, westeri
In-Reply-To: <fDMIXYjSRMSLJNqjRmWA7Q@disroot.org>
On Wed, Jun 24, 2026 at 07:49:21PM +0200, Marco Scardovi wrote:
> Hi guys,
>
> I'm feeling like a complete idiot right now and have to make a
> mea culpa for it.
>
> I didn't notice that [1] wasn't still merged into the 7.1 stable. I took it
> for granted as it was on linux-next since april and newer patches made by me
> were already merged on stable. It sounded strange that a patch made that
> was working 2 months ago to stop working suddenly and now I know why.
>
> I'm truly sorry for all the noise: you can skip on it.
Okay, so this thread clarified that Mario's patch fixed your issue and any
other model that is affected.
Hence, no patch from _this_ thread is going to be applied.
If it's not the case, speak that up!
> [1] https://lore.kernel.org/linux-gpio/20260429025247.1372984-1-mario.limonciello@amd.com/
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v3] pinctrl: qcom: Unconditionally mark gpio as wakeup enable
From: Sneh Mankad @ 2026-06-25 4:33 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Linus Walleij, Neil Armstrong,
Krzysztof Kozlowski
Cc: linux-arm-msm, linux-gpio, linux-kernel, stable, Maulik Shah
In-Reply-To: <d9e778ea-8a67-4576-9c96-9cfd859a266a@oss.qualcomm.com>
[...]
>
> This is a much better commit message, thank you!
>
> One question remains - should we set skip_wake_irqs for MPM too?
>
> My understanding is that no, since the MPM HW is simpler and doesn't
> have a register for acking IRQs, so we need to do it from the recipient
> (TLMM). Is that right?
>
Yes that is correct. skip_wake_irqs is set for PDC since PDC can handle interrupts
during active time and SoC sleep time both, so any wakeup capable interrupt source can
be handled via PDC at all times. However MPM can only handle interrupts when
SoC is in low power mode, it does not have the functionality to detect them when SoC
is active. skip_wake_irqs differentiates this behaviour.
Thanks,
Sneh
^ permalink raw reply
* Re: [PATCH v2 0/1] gpiolib: acpi: Add quirk for ASUS ROG Strix G16 G614 series
From: Marco Scardovi @ 2026-06-24 17:49 UTC (permalink / raw)
To: w_armin
Cc: andriy.shevchenko, bnatikar, brgl, johannes.goede, linusw,
linux-acpi, linux-gpio, linux-kernel, mario.limonciello,
scardracs, westeri
In-Reply-To: <f51df47c-0523-41ee-9e7d-0aa0177065e7@gmx.de>
Hi guys,
I'm feeling like a complete idiot right now and have to make a
mea culpa for it.
I didn't notice that [1] wasn't still merged into the 7.1 stable. I took it
for granted as it was on linux-next since april and newer patches made by me
were already merged on stable. It sounded strange that a patch made that
was working 2 months ago to stop working suddenly and now I know why.
I'm truly sorry for all the noise: you can skip on it.
[1] https://lore.kernel.org/linux-gpio/20260429025247.1372984-1-mario.limonciello@amd.com/
^ permalink raw reply
* Re: [PATCH 1/1] x86/vm86: fix vm86 struct leak on copy_from_user() failure
From: Borislav Petkov @ 2026-06-24 17:40 UTC (permalink / raw)
To: fffsqian
Cc: Thomas Gleixner, Ingo Molnar, Dave Hansen, x86, hpa, Kees Cook,
Andy Lutomirski, Brian Gerst, linux-gpio, Qingshuang Fu
In-Reply-To: <20260624092629.271618-1-fffsqian@163.com>
On Wed, Jun 24, 2026 at 05:26:29PM +0800, fffsqian@163.com wrote:
> diff --git a/arch/x86/kernel/vm86_32.c b/arch/x86/kernel/vm86_32.c
> index b4c1cabc7a4b..cde077f2c97e 100644
> --- a/arch/x86/kernel/vm86_32.c
> +++ b/arch/x86/kernel/vm86_32.c
> @@ -202,7 +202,8 @@ static long do_sys_vm86(struct vm86plus_struct __user *user_vm86, bool plus)
> struct vm86 *vm86 = tsk->thread.vm86;
> struct kernel_vm86_regs vm86regs;
> struct pt_regs *regs = current_pt_regs();
> - unsigned long err = 0;
> + bool newly_allocated = false;
What for?
Take a look at kfree()'s implementation.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
^ permalink raw reply
* Re: [PATCH libgpiod] build: fix dependencies for generated files
From: Bartosz Golaszewski @ 2026-06-24 15:22 UTC (permalink / raw)
To: Linus Walleij, Vincent Fazio, Kent Gibson, Luca Weiss,
Bartosz Golaszewski
Cc: linux-gpio, brgl
In-Reply-To: <20260623-dbus-meson-deps-v1-1-b37604ecce3f@oss.qualcomm.com>
On Tue, 23 Jun 2026 13:40:17 +0200, Bartosz Golaszewski wrote:
> Depending on the timing, we may try to build generated files that don't
> exist yet. Generated .c and .h files need to be included in the sources
> of the dependencies that need them so that they get generated before we
> try to build them. Fix issues observed in dbus and GLib bindings.
>
>
Applied, thanks!
[1/1] build: fix dependencies for generated files
https://git.kernel.org/brgl/c/7d7b07738885d051a28bdfb5025c8eb73cdf23f8
Best regards,
--
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH libgpiod 0/4] build: fix problems with meson build option guards
From: Bartosz Golaszewski @ 2026-06-24 15:22 UTC (permalink / raw)
To: Linus Walleij, Vincent Fazio, Kent Gibson, Bartosz Golaszewski
Cc: brgl, linux-gpio
In-Reply-To: <20260622-build-catch2-issue-v1-0-be95e28f310b@oss.qualcomm.com>
On Mon, 22 Jun 2026 15:58:06 +0200, Bartosz Golaszewski wrote:
> This series fixes several issues with how meson handles build options
> for libgpiod. Most notably: the problem with catch2 becoming a
> hard-dependency if tests and C++ bindings are merely "allowed".
>
>
Applied, thanks!
[1/4] build: don't make catch2 mandatory when C++ bindings and tests are enabled
https://git.kernel.org/brgl/c/7edfd6b7746c612195765649523ef6618b9eb37f
[2/4] build: include all test dependencies in the tests_enabled gate
https://git.kernel.org/brgl/c/372a5da1d8fc408bdac362d22eb7396e74519eab
[3/4] build: fix incomplete dependency gate for glib bindings
https://git.kernel.org/brgl/c/829eebf6a085141314bb80522b6678df58fc9d4b
[4/4] build: fix incomplete dependency gate for introspection
https://git.kernel.org/brgl/c/1f38ba3928eb16acf85512ce1767226ce5413425
Best regards,
--
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v2 0/1] gpiolib: acpi: Add quirk for ASUS ROG Strix G16 G614 series
From: Armin Wolf @ 2026-06-24 14:42 UTC (permalink / raw)
To: Hans de Goede, Marco Scardovi, bnatikar
Cc: andriy.shevchenko, brgl, linusw, linux-acpi, linux-gpio,
linux-kernel, mario.limonciello, westeri
In-Reply-To: <9237988a-2f5a-4c4e-8586-12899957bfea@oss.qualcomm.com>
Am 21.06.26 um 13:00 schrieb Hans de Goede:
> Hi Marco,
>
> On 17-Jun-26 20:50, Marco Scardovi wrote:
>> Hi Basavaraj,
>>
>> Thank you for your review: this is the v2 with the rewording as requested.
>>
>> Changes in v2:
>> - Reworded the commit message and the code comment to explain the actual
>> boot-time replay mechanism as suggested by Basavaraj.
>> - Explicitly noted that the touchpad itself is driven by i2c-hid and functions
>> normally, and that the ACPI event handler is preserved for post-boot events.
>> - Rebased against linux-next-20260616
>>
>> Marco Scardovi (1):
>> gpiolib: acpi: Add quirk for ASUS ROG Strix G16 G614 series
> Have you tried adding this patch to your kernel instead of adding a quirk? :
>
> https://lore.kernel.org/linux-gpio/20260429025247.1372984-1-mario.limonciello@amd.com/
>
> This modifies the code which does an initial sync of edge-run ACPI GPIO
> interrupt event handlers to match Windows and to skip it in certain
> circumstances.
>
> If that does not help, we should wait for Armin to get a chance to check
> your DSDT to see if the magic _DSM which inverts the polarity check for
> the initial sync run is there.
I checked the ACPI tables, and the _DSM is missing. However i think that the
affected GPIO is actually declared as being edge-triggered, so the aforementioned
patch from mario should fix the problem without requiring another quirk entry.
Thanks,
Armin Wolf
>
> By matching what Windows this we can hopefully fix this for a whole bunch
> of devices rather then having to rely on per model quirks.
>
> Regards,
>
> Hans
>
>
^ permalink raw reply
* Re: [PATCH v2] pinctrl: qcom: Avoid assigning unused private context in test cases
From: Linus Walleij @ 2026-06-24 13:28 UTC (permalink / raw)
To: Sneh Mankad, Bartosz Golaszewski
Cc: Bjorn Andersson, Yuanjie Yang, linux-arm-msm, linux-gpio,
linux-kernel
In-Reply-To: <20260610-tlmm_test_changes-v2-1-f34536da4717@oss.qualcomm.com>
On Wed, Jun 10, 2026 at 8:17 AM Sneh Mankad
<sneh.mankad@oss.qualcomm.com> wrote:
> tlmm_test_rising_while_disabled() sets thread_op_remain to 10, but this
> variable is only used by the threaded IRQ handler to control the number
> of GPIO pin toggles. Since tlmm_test_rising_while_disabled() does not
> register a threaded IRQ handler, the assignment is never used.
>
> Similarly, tlmm_test_high() and tlmm_test_low() set intr_op_remain to 9,
> but the variable is used to denote the IRQ handler the number of times
> GPIO signal has to be toggled from the hard IRQ handler.
>
> Since tlmm_test_high() and tlmm_test_low() themselves toggle the
> signal and do not require the hard IRQ handler to do it, the assignment is
> never used.
>
> Remove the thread_op_remain assignment from
> tlmm_test_rising_while_disabled() and intr_op_remain assignment from
> tlmm_test_high() and tlmm_test_low() test cases.
>
> This does not cause any change in functionality.
>
> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
I don't understand this patch, qcom pinctrl maintainer Bartosz will
decide about it.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v3] gpio: htc-egpio: use managed gpiochip registration
From: Pengpeng Hou @ 2026-06-24 13:18 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski
Cc: Russell King, Philipp Zabel, linux-gpio, linux-kernel,
Pengpeng Hou
egpio_probe() registers each nested gpio_chip with gpiochip_add_data()
but ignores the return value. If one registration fails, probe still
returns success even though one of the chips was not published to
gpiolib.
Use devm_gpiochip_add_data() and fail probe if any chip registration
fails. This lets devres unwind already registered chips and prevents
the driver from publishing a partially initialized device.
Fixes: a1635b8fe59d ("[ARM] 4947/1: htc-egpio, a driver for GPIO/IRQ expanders with fixed input/output pins")
Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn>
---
Changes since v2:
https://lore.kernel.org/all/20260622153204.72071-1-pengpeng@iscas.ac.cn/
- Add the Fixes tag requested by Bartosz Golaszewski.
drivers/gpio/gpio-htc-egpio.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-htc-egpio.c b/drivers/gpio/gpio-htc-egpio.c
index d15423c718d0..25a4d4494f3c 100644
--- a/drivers/gpio/gpio-htc-egpio.c
+++ b/drivers/gpio/gpio-htc-egpio.c
@@ -268,6 +268,7 @@ static int __init egpio_probe(struct platform_device *pdev)
struct gpio_chip *chip;
unsigned int irq, irq_end;
int i;
+ int ret;
/* Initialize ei data structure. */
ei = devm_kzalloc(&pdev->dev, struct_size(ei, chip, pdata->num_chips), GFP_KERNEL);
@@ -326,7 +327,10 @@ static int __init egpio_probe(struct platform_device *pdev)
chip->base = pdata->chip[i].gpio_base;
chip->ngpio = pdata->chip[i].num_gpios;
- gpiochip_add_data(chip, &ei->chip[i]);
+ ret = devm_gpiochip_add_data(&pdev->dev, chip, &ei->chip[i]);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to register gpiochip %d\n", i);
}
/* Set initial pin values */
--
2.50.1 (Apple Git-155)
^ permalink raw reply related
* [PATCH v3] gpio: mvebu: fail probe if gpiochip registration fails
From: Pengpeng Hou @ 2026-06-24 13:16 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski
Cc: Arnd Bergmann, Thomas Petazzoni, Jason Cooper, linux-gpio,
linux-kernel, Pengpeng Hou
mvebu_gpio_probe() registers the GPIO chip with
devm_gpiochip_add_data() but ignores the return value. If registration
fails, probe continues and leaves later code operating on a GPIO chip
that was never published to gpiolib.
Return the registration error so the device fails probe cleanly.
Fixes: fefe7b092345 ("gpio: introduce gpio-mvebu driver for Marvell SoCs")
Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn>
---
Changes since v2:
https://lore.kernel.org/all/20260622153137.69065-1-pengpeng@iscas.ac.cn/
- Add the Fixes tag requested by Bartosz Golaszewski.
drivers/gpio/gpio-mvebu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index c030d1f00abc..689dc6354c2d 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -1221,7 +1221,10 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
BUG();
}
- devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
+ err = devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
+ if (err)
+ return dev_err_probe(&pdev->dev, err,
+ "failed to register gpiochip\n");
/* Some MVEBU SoCs have simple PWM support for GPIO lines */
if (IS_REACHABLE(CONFIG_PWM)) {
--
2.50.1 (Apple Git-155)
^ permalink raw reply related
* [PATCH v11] PCI: Add support for PCIe WAKE# interrupt
From: Krishna Chaitanya Chundru @ 2026-06-24 11:25 UTC (permalink / raw)
To: Rafael J. Wysocki, Len Brown, Pavel Machek, Greg Kroah-Hartman,
Danilo Krummrich, Bjorn Helgaas, Bartosz Golaszewski,
Linus Walleij, Bartosz Golaszewski, Rob Herring, Saravana Kannan,
Linus Walleij
Cc: linux-pm, linux-kernel, linux-pci, linux-gpio, quic_vbadigan,
sherry.sun, driver-core, devicetree, Manivannan Sadhasivam,
Krishna Chaitanya Chundru
According to the PCI Express specification (PCIe r7.0, Section 5.3.3.2),
two link wakeup mechanisms are defined: Beacon and WAKE#. Beacon is a
hardware-only mechanism and is invisible to software (PCIe r7.0,
Section 4.2.7.8.1). This change adds support for the WAKE# mechanism
in the PCI core.
According to the PCIe specification, multiple WAKE# signals can exist in
a system or each component in the hierarchy could share a single WAKE#
signal. In configurations involving a PCIe switch, each downstream port
(DSP) of the switch may be connected to a separate WAKE# line, allowing
each endpoint to signal WAKE# independently. From figure 5.4 in sec
5.3.3.2, WAKE# can also be terminated at the switch itself. Such topologies
are typically not described in Device Tree, therefore it is out of scope
for this series.
To support this, the WAKE# should be described in the device tree node of
the endpoint/bridge. If all endpoints share a single WAKE# line, then each
endpoint node shall describe the same WAKE# signal or a single WAKE# in
the Root Port node.
In pci_device_add(), PCI framework will search for the WAKE# in device
node. Once found, register for the wake IRQ through
dev_pm_set_dedicated_wake_irq() associates a wakeup IRQ with a device
and requests it, but the PM core keeps the IRQ disabled by default. The
IRQ is enabled by the PM core, only when the device is permitted to wake
the system, i.e. during system suspend and after runtime suspend, and
only when device wakeup is enabled.
If the same WAKE# GPIO is described in multiple device tree nodes, only the
first device that successfully registers the wake IRQ will succeed, while
subsequent registrations may fail. This limitation does not affect
functional correctness, since WAKE# is only used to bring the link to D0,
and endpoint-specific wakeup handling is resolved later through
PME detection (PME_EN is set in suspend path by PCI core by default).
When the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume() to
bring the device back to an active power state, such as transitioning from
D3cold to D0. Once the device is active and the link is usable, the
endpoint may generate a PME, which is then handled by the PCI core through
PME polling or the PCIe PME service driver to complete the wakeup of the
endpoint.
WAKE# is added in dts schema and merged based on below links.
Link: https://lore.kernel.org/all/20250515090517.3506772-1-krishna.chundru@oss.qualcomm.com/
Link: https://github.com/devicetree-org/dt-schema/pull/170
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
PCIe WAKE# interrupt is needed for bringing back PCIe device state from
D3cold to D0.
This is pending from long time, there was two attempts done previously to
add WAKE# support[1], [2]. Those series tried to add support for legacy
interrupts along with WAKE#. Legacy interrupts are already available in
the latest kernel and we can ignore them. For the wake IRQ the series is
trying to use interrupts property define in the device tree.
WAKE# is added in dts schema and merged based on this patch.
https://lore.kernel.org/all/20250515090517.3506772-1-krishna.chundru@oss.qualcomm.com/
[1]: https://lore.kernel.org/all/b2b91240-95fe-145d-502c-d52225497a34@nvidia.com/T/
[2]: https://lore.kernel.org/all/20171226023646.17722-1-jeffy.chen@rock-chips.com/
---
Changes in v11:
- Add device_init_wakeup() as client driver is not expected to enable
bridge dev wakeup capability.
- Link to v10: https://patch.msgid.link/20260511-wakeirq_support-v10-0-c10af9c9eb8c@oss.qualcomm.com
Changes in v10:
- As sashiko pointed, shared irq has plenty of race conditions.
- So we are moving away from the shared IRQ patch and registering with
dedicated wake irq only, as part of wake irq the link will come to D0
as the parent controller driver will be runtime resume first and then
pme service will kick in wake up correct endpoint driver.
- Removed device_init_wakeup() since it enabling wakeup explicitly,
which is not intended as this should be set by endpoint driver only.
- Link to v9: https://lore.kernel.org/r/20260403-wakeirq_support-v9-0-1cbecf3b58d7@oss.qualcomm.com
Changes in v9:
- Call device_init_wakeup() only if
dev_pm_set_dedicated_shared_wake_irq() succeeds (Mani).
- Change the IRQ_TYPE from IRQ_TYPE_EDGE_FALLING to IRQ_TYPE_LEVEL_LOW (Mani).
- Link to v8: https://lore.kernel.org/r/20260313-wakeirq_support-v8-0-48a0a702518a@oss.qualcomm.com
Changes in v8:
- Moved the stub functions under CONFIG_OF_IRQ(mani).
- Added the description of how dev_pm_set_dedicated_shared_wake_irq()
works.
- Link to v7: https://lore.kernel.org/r/20260218-wakeirq_support-v7-0-0d4689830207@oss.qualcomm.com
Changes in v7:
- Updated the commit text (Mani).
- Couple of nits like using pci_err instead of dev_err,
use platform_pci_configure_wake(), platform_pci_remove_wake() instead
of calling directly calling pci_configure_of_wake_gpio() & pci_remove_of_wake_gpio() etc (Mani).
- Add a new fwnode_gpiod_get() API that wraps fwnode_gpiod_get_index(..0..), similar to
devm_fwnode_gpiod_get() (Mani).
- Link to v6: https://lore.kernel.org/r/20251127-wakeirq_support-v6-0-60f581f94205@oss.qualcomm.com
Changes in v6:
- Change the name to dev_pm_set_dedicated_shared_wake_irq() and make the
changes pointed by (Rafael).
- Link to v5: https://lore.kernel.org/r/20251107-wakeirq_support-v5-0-464e17f2c20c@oss.qualcomm.com
Changes in v5:
- Enable WAKE# irq only when there is wake -gpios defined in its device
tree node (Bjorn).
- For legacy bindings for direct atach check in root port if we haven't
find the wake in the endpoint node.
- Instead of hooking wake in driver bound case, do it in the framework
irrespective of the driver state (Bjorn).
- Link to v4: https://lore.kernel.org/r/20250801-wake_irq_support-v4-0-6b6639013a1a@oss.qualcomm.com
Changes in v4:
- Move wake from portdrv to core framework to endpoint (Bjorn).
- Added support for multiple WAKE# case (Bjorn). But traverse from
endpoint upstream port to root port till you get WAKE#. And use
IRQF_SHARED flag for requesting interrupts.
- Link to v3: https://lore.kernel.org/r/20250605-wake_irq_support-v3-0-7ba56dc909a5@oss.qualcomm.com
Changes in v3:
- Update the commit messages, function names etc as suggested by Mani.
- return wake_irq if returns error (Neil).
- Link to v2: https://lore.kernel.org/r/20250419-wake_irq_support-v2-0-06baed9a87a1@oss.qualcomm.com
Changes in v2:
- Move the wake irq teardown after pcie_port_device_remove
and move of_pci_setup_wake_irq before pcie_link_rcec (Lukas)
- teardown wake irq in shutdown also.
- Link to v1: https://lore.kernel.org/r/20250401-wake_irq_support-v1-0-d2e22f4a0efd@oss.qualcomm.com
To: Bjorn Helgaas <bhelgaas@google.com>
To: Rob Herring <robh@kernel.org>
To: Saravana Kannan <saravanak@kernel.org>
Cc: linux-pci@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/pci/of.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/pci/pci.c | 11 ++++++++
drivers/pci/pci.h | 2 ++
drivers/pci/probe.c | 2 ++
drivers/pci/remove.c | 1 +
include/linux/of_pci.h | 6 ++++
include/linux/pci.h | 2 ++
7 files changed, 100 insertions(+)
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index 8b18c4ba845c..0f5effe1d702 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -7,6 +7,7 @@
#define pr_fmt(fmt) "PCI: OF: " fmt
#include <linux/cleanup.h>
+#include <linux/gpio/consumer.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/pci.h>
@@ -15,6 +16,7 @@
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/platform_device.h>
+#include <linux/pm_wakeirq.h>
#include "pci.h"
#ifdef CONFIG_PCI
@@ -586,6 +588,80 @@ int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)
return irq_create_of_mapping(&oirq);
}
EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci);
+
+static void pci_configure_wake_irq(struct pci_dev *pdev, struct gpio_desc *wake)
+{
+ int ret, wake_irq;
+
+ wake_irq = gpiod_to_irq(wake);
+ if (wake_irq < 0) {
+ pci_err(pdev, "Failed to get wake irq: %d\n", wake_irq);
+ return;
+ }
+
+ /*
+ * dev_pm_set_dedicated_wake_irq() associates a wakeup IRQ with the
+ * device and requests it, but the PM core keeps it disabled by default.
+ * The IRQ is enabled only when the device is allowed to wake the system
+ * (during system suspend and after runtime suspend), and only if device
+ * wakeup is enabled.
+ *
+ * When the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume()
+ * to bring the device back to an active power state (e.g. from D3cold to D0).
+ * Once the device is active and the link is usable, the endpoint may signal
+ * a PME, which is then handled by the PCI core (either via PME polling or the
+ * PCIe PME service driver) to wakeup particular endpoint.
+ */
+ ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, wake_irq);
+ if (ret < 0) {
+ pci_err(pdev, "Failed to set WAKE# IRQ: %d\n", ret);
+ return;
+ }
+
+ ret = irq_set_irq_type(wake_irq, IRQ_TYPE_LEVEL_LOW);
+ if (ret < 0) {
+ dev_pm_clear_wake_irq(&pdev->dev);
+ pci_err(pdev, "Failed to set irq_type: %d\n", ret);
+ return;
+ }
+
+ device_init_wakeup(&pdev->dev, true);
+}
+
+void pci_configure_of_wake_gpio(struct pci_dev *dev)
+{
+ struct device_node *dn = pci_device_to_OF_node(dev);
+ struct gpio_desc *gpio;
+
+ if (!dn)
+ return;
+ /*
+ * fwnode_gpiod_get() may fail with -EBUSY (e.g. shared WAKE#), but the
+ * actual WAKE# trigger from the device would still work and the host
+ * controller driver will enable power to the topology.
+ *
+ * -EPROBE_DEFER cannot be propagated here since pci_device_add() has no
+ * retry mechanism.
+ */
+ gpio = fwnode_gpiod_get(of_fwnode_handle(dn), "wake", GPIOD_IN, NULL);
+ if (!IS_ERR(gpio)) {
+ dev->wake = gpio;
+ pci_configure_wake_irq(dev, gpio);
+ }
+}
+
+void pci_remove_of_wake_gpio(struct pci_dev *dev)
+{
+ struct device_node *dn = pci_device_to_OF_node(dev);
+
+ if (!dn)
+ return;
+
+ device_init_wakeup(&dev->dev, false);
+ dev_pm_clear_wake_irq(&dev->dev);
+ gpiod_put(dev->wake);
+ dev->wake = NULL;
+}
#endif /* CONFIG_OF_IRQ */
static int pci_parse_request_of_pci_ranges(struct device *dev,
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index d34266651ad0..9d9777fe099a 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -17,6 +17,7 @@
#include <linux/lockdep.h>
#include <linux/msi.h>
#include <linux/of.h>
+#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/pm.h>
#include <linux/slab.h>
@@ -1123,6 +1124,16 @@ static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
return acpi_pci_bridge_d3(dev);
}
+void platform_pci_configure_wake(struct pci_dev *dev)
+{
+ pci_configure_of_wake_gpio(dev);
+}
+
+void platform_pci_remove_wake(struct pci_dev *dev)
+{
+ pci_remove_of_wake_gpio(dev);
+}
+
/**
* pci_update_current_state - Read power state of given device and cache it
* @dev: PCI device to handle.
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index e8ad27abb1cf..8633c093385c 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -284,6 +284,8 @@ void pci_msix_init(struct pci_dev *dev);
bool pci_bridge_d3_possible(struct pci_dev *dev);
void pci_bridge_d3_update(struct pci_dev *dev);
int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
+void platform_pci_configure_wake(struct pci_dev *dev);
+void platform_pci_remove_wake(struct pci_dev *dev);
static inline bool pci_bus_rrs_vendor_id(u32 l)
{
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index b63cd0c310bc..143b0bd35b3c 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2775,6 +2775,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
/* Establish pdev->tsm for newly added (e.g. new SR-IOV VFs) */
pci_tsm_init(dev);
+ platform_pci_configure_wake(dev);
+
pci_npem_create(dev);
pci_doe_sysfs_init(dev);
diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c
index e9d519993853..d781b41e57c4 100644
--- a/drivers/pci/remove.c
+++ b/drivers/pci/remove.c
@@ -35,6 +35,7 @@ static void pci_destroy_dev(struct pci_dev *dev)
if (pci_dev_test_and_set_removed(dev))
return;
+ platform_pci_remove_wake(dev);
pci_doe_sysfs_teardown(dev);
pci_npem_remove(dev);
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index 29658c0ee71f..649fe8eafcfa 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -30,12 +30,18 @@ static inline void of_pci_check_probe_only(void) { }
#if IS_ENABLED(CONFIG_OF_IRQ)
int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin);
+void pci_configure_of_wake_gpio(struct pci_dev *dev);
+void pci_remove_of_wake_gpio(struct pci_dev *dev);
#else
static inline int
of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)
{
return 0;
}
+
+static inline void pci_configure_of_wake_gpio(struct pci_dev *dev) { }
+
+static inline void pci_remove_of_wake_gpio(struct pci_dev *dev) { }
#endif
#endif
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 2c4454583c11..4289b60dcc83 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -588,6 +588,8 @@ struct pci_dev {
/* These methods index pci_reset_fn_methods[] */
u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
+ struct gpio_desc *wake; /* Holds WAKE# gpio */
+
#ifdef CONFIG_PCIE_TPH
u16 tph_cap; /* TPH capability offset */
u8 tph_mode; /* TPH mode */
---
base-commit: 840ef6c78e6a2f694b578ecb9063241c992aaa9e
change-id: 20251104-wakeirq_support-f54c4baa18c5
Best regards,
--
Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
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