* [PATCH v6 09/17] pinctrl: airoha: an7581: remove en7581 prefix from variable names
From: Mikhail Kshevetskiy @ 2026-06-28 14:37 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260628143733.273651-1-mikhail.kshevetskiy@iopsys.eu>
We have only an7581 specific code in the pinctrl-an7581 kernel module,
so 'en7581_' prefix is not necessary anymore. Remove it.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/pinctrl-an7581.c | 398 ++++++++++++------------
1 file changed, 199 insertions(+), 199 deletions(-)
diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
index 522b35bbaa12..6e53143e91d7 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
@@ -316,7 +316,7 @@
.regmap_size = 2, \
}
-static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
+static struct pinctrl_pin_desc pinctrl_pins[] = {
PINCTRL_PIN(0, "uart1_txd"),
PINCTRL_PIN(1, "uart1_rxd"),
PINCTRL_PIN(2, "i2c_scl"),
@@ -377,184 +377,184 @@ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
PINCTRL_PIN(62, "pcie_reset2"),
};
-static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
-static const int en7581_pon_tod_1pps_pins[] = { 46 };
-static const int en7581_gsw_tod_1pps_pins[] = { 46 };
-static const int en7581_sipo_pins[] = { 16, 17 };
-static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
-static const int en7581_mdio_pins[] = { 14, 15 };
-static const int en7581_uart2_pins[] = { 48, 55 };
-static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
-static const int en7581_hsuart_pins[] = { 28, 29 };
-static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
-static const int en7581_uart4_pins[] = { 38, 39 };
-static const int en7581_uart5_pins[] = { 18, 19 };
-static const int en7581_i2c0_pins[] = { 2, 3 };
-static const int en7581_i2c1_pins[] = { 14, 15 };
-static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
-static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
-static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
-static const int en7581_spi_quad_pins[] = { 32, 33 };
-static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
-static const int en7581_spi_cs1_pins[] = { 34 };
-static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
-static const int en7581_pcm_spi_int_pins[] = { 14 };
-static const int en7581_pcm_spi_rst_pins[] = { 15 };
-static const int en7581_pcm_spi_cs1_pins[] = { 43 };
-static const int en7581_pcm_spi_cs2_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
-static const int en7581_pcm_spi_cs3_pins[] = { 41 };
-static const int en7581_pcm_spi_cs4_pins[] = { 42 };
-static const int en7581_emmc_pins[] = {
+static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+static const int pon_tod_1pps_pins[] = { 46 };
+static const int gsw_tod_1pps_pins[] = { 46 };
+static const int sipo_pins[] = { 16, 17 };
+static const int sipo_rclk_pins[] = { 16, 17, 43 };
+static const int mdio_pins[] = { 14, 15 };
+static const int uart2_pins[] = { 48, 55 };
+static const int uart2_cts_rts_pins[] = { 46, 47 };
+static const int hsuart_pins[] = { 28, 29 };
+static const int hsuart_cts_rts_pins[] = { 26, 27 };
+static const int uart4_pins[] = { 38, 39 };
+static const int uart5_pins[] = { 18, 19 };
+static const int i2c0_pins[] = { 2, 3 };
+static const int i2c1_pins[] = { 14, 15 };
+static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
+static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
+static const int i2s_pins[] = { 26, 27, 28, 29 };
+static const int pcm1_pins[] = { 22, 23, 24, 25 };
+static const int pcm2_pins[] = { 18, 19, 20, 21 };
+static const int spi_quad_pins[] = { 32, 33 };
+static const int spi_pins[] = { 4, 5, 6, 7 };
+static const int spi_cs1_pins[] = { 34 };
+static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
+static const int pcm_spi_int_pins[] = { 14 };
+static const int pcm_spi_rst_pins[] = { 15 };
+static const int pcm_spi_cs1_pins[] = { 43 };
+static const int pcm_spi_cs2_pins[] = { 40 };
+static const int pcm_spi_cs2_p128_pins[] = { 40 };
+static const int pcm_spi_cs2_p156_pins[] = { 40 };
+static const int pcm_spi_cs3_pins[] = { 41 };
+static const int pcm_spi_cs4_pins[] = { 42 };
+static const int emmc_pins[] = {
4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
};
-static const int en7581_pnand_pins[] = {
+static const int pnand_pins[] = {
4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
};
-static const int en7581_gpio0_pins[] = { 13 };
-static const int en7581_gpio1_pins[] = { 14 };
-static const int en7581_gpio2_pins[] = { 15 };
-static const int en7581_gpio3_pins[] = { 16 };
-static const int en7581_gpio4_pins[] = { 17 };
-static const int en7581_gpio5_pins[] = { 18 };
-static const int en7581_gpio6_pins[] = { 19 };
-static const int en7581_gpio7_pins[] = { 20 };
-static const int en7581_gpio8_pins[] = { 21 };
-static const int en7581_gpio9_pins[] = { 22 };
-static const int en7581_gpio10_pins[] = { 23 };
-static const int en7581_gpio11_pins[] = { 24 };
-static const int en7581_gpio12_pins[] = { 25 };
-static const int en7581_gpio13_pins[] = { 26 };
-static const int en7581_gpio14_pins[] = { 27 };
-static const int en7581_gpio15_pins[] = { 28 };
-static const int en7581_gpio16_pins[] = { 29 };
-static const int en7581_gpio17_pins[] = { 30 };
-static const int en7581_gpio18_pins[] = { 31 };
-static const int en7581_gpio19_pins[] = { 32 };
-static const int en7581_gpio20_pins[] = { 33 };
-static const int en7581_gpio21_pins[] = { 34 };
-static const int en7581_gpio22_pins[] = { 35 };
-static const int en7581_gpio23_pins[] = { 36 };
-static const int en7581_gpio24_pins[] = { 37 };
-static const int en7581_gpio25_pins[] = { 38 };
-static const int en7581_gpio26_pins[] = { 39 };
-static const int en7581_gpio27_pins[] = { 40 };
-static const int en7581_gpio28_pins[] = { 41 };
-static const int en7581_gpio29_pins[] = { 42 };
-static const int en7581_gpio30_pins[] = { 43 };
-static const int en7581_gpio31_pins[] = { 44 };
-static const int en7581_gpio32_pins[] = { 45 };
-static const int en7581_gpio33_pins[] = { 46 };
-static const int en7581_gpio34_pins[] = { 47 };
-static const int en7581_gpio35_pins[] = { 48 };
-static const int en7581_gpio36_pins[] = { 49 };
-static const int en7581_gpio37_pins[] = { 50 };
-static const int en7581_gpio38_pins[] = { 51 };
-static const int en7581_gpio39_pins[] = { 52 };
-static const int en7581_gpio40_pins[] = { 53 };
-static const int en7581_gpio41_pins[] = { 54 };
-static const int en7581_gpio42_pins[] = { 55 };
-static const int en7581_gpio43_pins[] = { 56 };
-static const int en7581_gpio44_pins[] = { 57 };
-static const int en7581_gpio45_pins[] = { 58 };
-static const int en7581_gpio46_pins[] = { 59 };
-static const int en7581_gpio47_pins[] = { 60 };
-static const int en7581_gpio48_pins[] = { 61 };
-static const int en7581_gpio49_pins[] = { 62 };
-static const int en7581_pcie_reset0_pins[] = { 60 };
-static const int en7581_pcie_reset1_pins[] = { 61 };
-static const int en7581_pcie_reset2_pins[] = { 62 };
-
-static const struct pingroup en7581_pinctrl_groups[] = {
- PINCTRL_PIN_GROUP("pon", en7581_pon),
- PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
- PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
- PINCTRL_PIN_GROUP("sipo", en7581_sipo),
- PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
- PINCTRL_PIN_GROUP("mdio", en7581_mdio),
- PINCTRL_PIN_GROUP("uart2", en7581_uart2),
- PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
- PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
- PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
- PINCTRL_PIN_GROUP("uart4", en7581_uart4),
- PINCTRL_PIN_GROUP("uart5", en7581_uart5),
- PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
- PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
- PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
- PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
- PINCTRL_PIN_GROUP("i2s", en7581_i2s),
- PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
- PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
- PINCTRL_PIN_GROUP("spi", en7581_spi),
- PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
- PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
- PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
- PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
- PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
- PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
- PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
- PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
- PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
- PINCTRL_PIN_GROUP("emmc", en7581_emmc),
- PINCTRL_PIN_GROUP("pnand", en7581_pnand),
- PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
- PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
- PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
- PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
- PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
- PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
- PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
- PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
- PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
- PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
- PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
- PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
- PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
- PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
- PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
- PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
- PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
- PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
- PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
- PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
- PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
- PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
- PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
- PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
- PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
- PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
- PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
- PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
- PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
- PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
- PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
- PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
- PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
- PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
- PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
- PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
- PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
- PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
- PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
- PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
- PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
- PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
- PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
- PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
- PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
- PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
- PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
- PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
- PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
- PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
- PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
- PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
- PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
+static const int gpio0_pins[] = { 13 };
+static const int gpio1_pins[] = { 14 };
+static const int gpio2_pins[] = { 15 };
+static const int gpio3_pins[] = { 16 };
+static const int gpio4_pins[] = { 17 };
+static const int gpio5_pins[] = { 18 };
+static const int gpio6_pins[] = { 19 };
+static const int gpio7_pins[] = { 20 };
+static const int gpio8_pins[] = { 21 };
+static const int gpio9_pins[] = { 22 };
+static const int gpio10_pins[] = { 23 };
+static const int gpio11_pins[] = { 24 };
+static const int gpio12_pins[] = { 25 };
+static const int gpio13_pins[] = { 26 };
+static const int gpio14_pins[] = { 27 };
+static const int gpio15_pins[] = { 28 };
+static const int gpio16_pins[] = { 29 };
+static const int gpio17_pins[] = { 30 };
+static const int gpio18_pins[] = { 31 };
+static const int gpio19_pins[] = { 32 };
+static const int gpio20_pins[] = { 33 };
+static const int gpio21_pins[] = { 34 };
+static const int gpio22_pins[] = { 35 };
+static const int gpio23_pins[] = { 36 };
+static const int gpio24_pins[] = { 37 };
+static const int gpio25_pins[] = { 38 };
+static const int gpio26_pins[] = { 39 };
+static const int gpio27_pins[] = { 40 };
+static const int gpio28_pins[] = { 41 };
+static const int gpio29_pins[] = { 42 };
+static const int gpio30_pins[] = { 43 };
+static const int gpio31_pins[] = { 44 };
+static const int gpio32_pins[] = { 45 };
+static const int gpio33_pins[] = { 46 };
+static const int gpio34_pins[] = { 47 };
+static const int gpio35_pins[] = { 48 };
+static const int gpio36_pins[] = { 49 };
+static const int gpio37_pins[] = { 50 };
+static const int gpio38_pins[] = { 51 };
+static const int gpio39_pins[] = { 52 };
+static const int gpio40_pins[] = { 53 };
+static const int gpio41_pins[] = { 54 };
+static const int gpio42_pins[] = { 55 };
+static const int gpio43_pins[] = { 56 };
+static const int gpio44_pins[] = { 57 };
+static const int gpio45_pins[] = { 58 };
+static const int gpio46_pins[] = { 59 };
+static const int gpio47_pins[] = { 60 };
+static const int gpio48_pins[] = { 61 };
+static const int gpio49_pins[] = { 62 };
+static const int pcie_reset0_pins[] = { 60 };
+static const int pcie_reset1_pins[] = { 61 };
+static const int pcie_reset2_pins[] = { 62 };
+
+static const struct pingroup pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", mdio),
+ PINCTRL_PIN_GROUP("uart2", uart2),
+ PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts),
+ PINCTRL_PIN_GROUP("hsuart", hsuart),
+ PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
+ PINCTRL_PIN_GROUP("uart4", uart4),
+ PINCTRL_PIN_GROUP("uart5", uart5),
+ PINCTRL_PIN_GROUP("i2c0", i2c0),
+ PINCTRL_PIN_GROUP("i2c1", i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+ PINCTRL_PIN_GROUP("i2s", i2s),
+ PINCTRL_PIN_GROUP("pcm1", pcm1),
+ PINCTRL_PIN_GROUP("pcm2", pcm2),
+ PINCTRL_PIN_GROUP("spi", spi),
+ PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2),
+ PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3),
+ PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4),
+ PINCTRL_PIN_GROUP("emmc", emmc),
+ PINCTRL_PIN_GROUP("pnand", pnand),
+ PINCTRL_PIN_GROUP("gpio0", gpio0),
+ PINCTRL_PIN_GROUP("gpio1", gpio1),
+ PINCTRL_PIN_GROUP("gpio2", gpio2),
+ PINCTRL_PIN_GROUP("gpio3", gpio3),
+ PINCTRL_PIN_GROUP("gpio4", gpio4),
+ PINCTRL_PIN_GROUP("gpio5", gpio5),
+ PINCTRL_PIN_GROUP("gpio6", gpio6),
+ PINCTRL_PIN_GROUP("gpio7", gpio7),
+ PINCTRL_PIN_GROUP("gpio8", gpio8),
+ PINCTRL_PIN_GROUP("gpio9", gpio9),
+ PINCTRL_PIN_GROUP("gpio10", gpio10),
+ PINCTRL_PIN_GROUP("gpio11", gpio11),
+ PINCTRL_PIN_GROUP("gpio12", gpio12),
+ PINCTRL_PIN_GROUP("gpio13", gpio13),
+ PINCTRL_PIN_GROUP("gpio14", gpio14),
+ PINCTRL_PIN_GROUP("gpio15", gpio15),
+ PINCTRL_PIN_GROUP("gpio16", gpio16),
+ PINCTRL_PIN_GROUP("gpio17", gpio17),
+ PINCTRL_PIN_GROUP("gpio18", gpio18),
+ PINCTRL_PIN_GROUP("gpio19", gpio19),
+ PINCTRL_PIN_GROUP("gpio20", gpio20),
+ PINCTRL_PIN_GROUP("gpio21", gpio21),
+ PINCTRL_PIN_GROUP("gpio22", gpio22),
+ PINCTRL_PIN_GROUP("gpio23", gpio23),
+ PINCTRL_PIN_GROUP("gpio24", gpio24),
+ PINCTRL_PIN_GROUP("gpio25", gpio25),
+ PINCTRL_PIN_GROUP("gpio26", gpio26),
+ PINCTRL_PIN_GROUP("gpio27", gpio27),
+ PINCTRL_PIN_GROUP("gpio28", gpio28),
+ PINCTRL_PIN_GROUP("gpio29", gpio29),
+ PINCTRL_PIN_GROUP("gpio30", gpio30),
+ PINCTRL_PIN_GROUP("gpio31", gpio31),
+ PINCTRL_PIN_GROUP("gpio32", gpio32),
+ PINCTRL_PIN_GROUP("gpio33", gpio33),
+ PINCTRL_PIN_GROUP("gpio34", gpio34),
+ PINCTRL_PIN_GROUP("gpio35", gpio35),
+ PINCTRL_PIN_GROUP("gpio36", gpio36),
+ PINCTRL_PIN_GROUP("gpio37", gpio37),
+ PINCTRL_PIN_GROUP("gpio38", gpio38),
+ PINCTRL_PIN_GROUP("gpio39", gpio39),
+ PINCTRL_PIN_GROUP("gpio40", gpio40),
+ PINCTRL_PIN_GROUP("gpio41", gpio41),
+ PINCTRL_PIN_GROUP("gpio42", gpio42),
+ PINCTRL_PIN_GROUP("gpio43", gpio43),
+ PINCTRL_PIN_GROUP("gpio44", gpio44),
+ PINCTRL_PIN_GROUP("gpio45", gpio45),
+ PINCTRL_PIN_GROUP("gpio46", gpio46),
+ PINCTRL_PIN_GROUP("gpio47", gpio47),
+ PINCTRL_PIN_GROUP("gpio48", gpio48),
+ PINCTRL_PIN_GROUP("gpio49", gpio49),
+ PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+ PINCTRL_PIN_GROUP("pcie_reset2", pcie_reset2),
};
static const char *const pon_groups[] = { "pon" };
@@ -1154,7 +1154,7 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
-static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("pon", pon),
PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
PINCTRL_FUNC_DESC("sipo", sipo),
@@ -1181,7 +1181,7 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
@@ -1242,7 +1242,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
@@ -1303,7 +1303,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
@@ -1364,7 +1364,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
@@ -1425,47 +1425,47 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
};
-static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
.pinctrl_name = KBUILD_MODNAME,
.pinctrl_owner = THIS_MODULE,
- .pins = en7581_pinctrl_pins,
- .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
- .grps = en7581_pinctrl_groups,
- .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
- .funcs = en7581_pinctrl_funcs,
- .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
+ .pins = pinctrl_pins,
+ .num_pins = ARRAY_SIZE(pinctrl_pins),
+ .grps = pinctrl_groups,
+ .num_grps = ARRAY_SIZE(pinctrl_groups),
+ .funcs = pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(pinctrl_funcs),
.confs_info = {
[AIROHA_PINCTRL_CONFS_PULLUP] = {
- .confs = en7581_pinctrl_pullup_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
+ .confs = pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
},
[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
- .confs = en7581_pinctrl_pulldown_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
+ .confs = pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
- .confs = en7581_pinctrl_drive_e2_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
+ .confs = pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
- .confs = en7581_pinctrl_drive_e4_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
+ .confs = pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
},
[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
- .confs = en7581_pinctrl_pcie_rst_od_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
+ .confs = pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
},
},
};
static const struct of_device_id airoha_pinctrl_of_match[] = {
- { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
+ { .compatible = "airoha,en7581-pinctrl", .data = &pinctrl_match_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
--
2.53.0
^ permalink raw reply related
* [PATCH v6 08/17] pinctrl: airoha: split driver on shared code and SoC specific drivers
From: Mikhail Kshevetskiy @ 2026-06-28 14:37 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260628143733.273651-1-mikhail.kshevetskiy@iopsys.eu>
Split combined an7581/an7583 source file on a
* shared pinctrl code (pinctrl-airoha.c)
* an7581 specific pinctrl driver (pinctrl-an7581.c)
* an7583 specific pinctrl driver (pinctrl-an7583.c)
Ininialization code was adapted a bit to work properly for shared
and SoC specific cases.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/Kconfig | 18 +-
drivers/pinctrl/airoha/Makefile | 5 +
drivers/pinctrl/airoha/airoha-common.h | 5 +
drivers/pinctrl/airoha/pinctrl-airoha.c | 2396 +----------------------
drivers/pinctrl/airoha/pinctrl-an7581.c | 1486 ++++++++++++++
drivers/pinctrl/airoha/pinctrl-an7583.c | 1456 ++++++++++++++
6 files changed, 2983 insertions(+), 2383 deletions(-)
create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c
create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c
diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
index 03adaeae8fc3..08038a5b11c6 100644
--- a/drivers/pinctrl/airoha/Kconfig
+++ b/drivers/pinctrl/airoha/Kconfig
@@ -3,9 +3,9 @@ menu "Airoha pinctrl drivers"
depends on ARCH_AIROHA || COMPILE_TEST
config PINCTRL_AIROHA
- tristate "Airoha EN7581 pin control"
+ tristate "Airoha pin control"
depends on OF
- depends on ARM64 || COMPILE_TEST
+ depends on ARCH_AIROHA || COMPILE_TEST
select PINMUX
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
@@ -13,8 +13,20 @@ config PINCTRL_AIROHA
select GPIOLIB
select GPIOLIB_IRQCHIP
select REGMAP_MMIO
+ imply PINCTRL_AIROHA_AN7581
+ imply PINCTRL_AIROHA_AN7583
help
Say yes here to support pin controller and gpio driver
- on Airoha EN7581 SoC.
+ on Airoha SoC.
+
+config PINCTRL_AIROHA_AN7581
+ tristate "AN7581 pinctrl"
+ depends on ARM64 || COMPILE_TEST
+ depends on PINCTRL_AIROHA
+
+config PINCTRL_AIROHA_AN7583
+ tristate "AN7583 pinctrl"
+ depends on ARM64 || COMPILE_TEST
+ depends on PINCTRL_AIROHA
endmenu
diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
index a25b744dd7a8..cfd68c45ae0f 100644
--- a/drivers/pinctrl/airoha/Makefile
+++ b/drivers/pinctrl/airoha/Makefile
@@ -1,3 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
+# shared code
obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
+
+# SoC drivers
+obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o
+obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o
diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
index bff162062b06..9a202d5bb4b1 100644
--- a/drivers/pinctrl/airoha/airoha-common.h
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -150,9 +150,12 @@ struct airoha_pinctrl {
struct regmap *regmap;
struct airoha_pinctrl_gpiochip gpiochip;
+ struct irq_chip gpio_irq_chip;
};
struct airoha_pinctrl_match_data {
+ const char *pinctrl_name;
+ struct module *pinctrl_owner;
const struct pinctrl_pin_desc *pins;
const unsigned int num_pins;
const struct pingroup *grps;
@@ -162,4 +165,6 @@ struct airoha_pinctrl_match_data {
const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
};
+int airoha_pinctrl_probe(struct platform_device *pdev);
+
#endif
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index e67c19df9f45..543475d23fde 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -7,365 +7,6 @@
#include "airoha-common.h"
-/* MUX */
-#define REG_GPIO_2ND_I2C_MODE 0x0214
-#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14)
-#define GPIO_I2C_MASTER_MODE_MODE BIT(13)
-#define GPIO_I2S_MODE_MASK BIT(12)
-#define GPIO_I2C_SLAVE_MODE_MODE BIT(11)
-#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
-#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
-#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
-#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
-#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
-#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
-#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
-#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
-#define PON_TOD_1PPS_MODE_MASK BIT(2)
-#define GSW_TOD_1PPS_MODE_MASK BIT(1)
-#define GPIO_2ND_I2C_MODE_MASK BIT(0)
-
-#define REG_GPIO_SPI_CS1_MODE 0x0218
-#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
-#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
-#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
-#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
-#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
-#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
-#define GPIO_PCM_SPI_MODE_MASK BIT(16)
-#define GPIO_PCM2_MODE_MASK BIT(13)
-#define GPIO_PCM1_MODE_MASK BIT(12)
-#define GPIO_PCM_INT_MODE_MASK BIT(9)
-#define GPIO_PCM_RESET_MODE_MASK BIT(8)
-#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
-#define GPIO_SPI_CS4_MODE_MASK BIT(3)
-#define GPIO_SPI_CS3_MODE_MASK BIT(2)
-#define GPIO_SPI_CS2_MODE_MASK BIT(1)
-#define GPIO_SPI_CS1_MODE_MASK BIT(0)
-
-#define REG_GPIO_PON_MODE 0x021c
-#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26)
-#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25)
-#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24)
-#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23)
-#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22)
-#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21)
-#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20)
-#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19)
-#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18)
-#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17)
-#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16)
-#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15)
-#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
-#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
-#define GPIO_PCIE_RESET2_MASK BIT(12)
-#define SIPO_RCLK_MODE_MASK BIT(11)
-#define GPIO_PCIE_RESET1_MASK BIT(10)
-#define GPIO_PCIE_RESET0_MASK BIT(9)
-#define GPIO_UART5_MODE_MASK BIT(8)
-#define GPIO_UART4_MODE_MASK BIT(7)
-#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6)
-#define GPIO_HSUART_MODE_MASK BIT(5)
-#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4)
-#define GPIO_UART2_MODE_MASK BIT(3)
-#define GPIO_SIPO_MODE_MASK BIT(2)
-#define GPIO_EMMC_MODE_MASK BIT(1)
-#define GPIO_PON_MODE_MASK BIT(0)
-
-#define REG_NPU_UART_EN 0x0224
-#define JTAG_UDI_EN_MASK BIT(4)
-#define JTAG_DFD_EN_MASK BIT(3)
-
-#define REG_FORCE_GPIO_EN 0x0228
-#define FORCE_GPIO_EN(n) BIT(n)
-
-/* LED MAP */
-#define REG_LAN_LED0_MAPPING 0x027c
-#define REG_LAN_LED1_MAPPING 0x0280
-
-#define LAN4_LED_MAPPING_MASK GENMASK(18, 16)
-#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
-
-#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
-#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
-
-#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
-#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
-
-#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
-#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
-
-#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
-#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
-
-/* CONF */
-#define REG_I2C_SDA_E2 0x001c
-#define AN7583_I2C1_SCL_E2_MASK BIT(16)
-#define AN7583_I2C1_SDA_E2_MASK BIT(15)
-#define SPI_MISO_E2_MASK BIT(14)
-#define SPI_MOSI_E2_MASK BIT(13)
-#define SPI_CLK_E2_MASK BIT(12)
-#define SPI_CS0_E2_MASK BIT(11)
-#define PCIE2_RESET_E2_MASK BIT(10)
-#define PCIE1_RESET_E2_MASK BIT(9)
-#define PCIE0_RESET_E2_MASK BIT(8)
-#define AN7583_MDIO_0_E2_MASK BIT(5)
-#define AN7583_MDC_0_E2_MASK BIT(4)
-#define UART1_RXD_E2_MASK BIT(3)
-#define UART1_TXD_E2_MASK BIT(2)
-#define I2C_SCL_E2_MASK BIT(1)
-#define I2C_SDA_E2_MASK BIT(0)
-
-#define REG_I2C_SDA_E4 0x0020
-#define AN7583_I2C1_SCL_E4_MASK BIT(16)
-#define AN7583_I2C1_SDA_E4_MASK BIT(15)
-#define SPI_MISO_E4_MASK BIT(14)
-#define SPI_MOSI_E4_MASK BIT(13)
-#define SPI_CLK_E4_MASK BIT(12)
-#define SPI_CS0_E4_MASK BIT(11)
-#define PCIE2_RESET_E4_MASK BIT(10)
-#define PCIE1_RESET_E4_MASK BIT(9)
-#define PCIE0_RESET_E4_MASK BIT(8)
-#define AN7583_MDIO_0_E4_MASK BIT(5)
-#define AN7583_MDC_0_E4_MASK BIT(4)
-#define UART1_RXD_E4_MASK BIT(3)
-#define UART1_TXD_E4_MASK BIT(2)
-#define I2C_SCL_E4_MASK BIT(1)
-#define I2C_SDA_E4_MASK BIT(0)
-
-#define REG_GPIO_L_E2 0x0024
-#define REG_GPIO_L_E4 0x0028
-#define REG_GPIO_H_E2 0x002c
-#define REG_GPIO_H_E4 0x0030
-
-#define REG_I2C_SDA_PU 0x0044
-#define AN7583_I2C1_SCL_PU_MASK BIT(16)
-#define AN7583_I2C1_SDA_PU_MASK BIT(15)
-#define SPI_MISO_PU_MASK BIT(14)
-#define SPI_MOSI_PU_MASK BIT(13)
-#define SPI_CLK_PU_MASK BIT(12)
-#define SPI_CS0_PU_MASK BIT(11)
-#define PCIE2_RESET_PU_MASK BIT(10)
-#define PCIE1_RESET_PU_MASK BIT(9)
-#define PCIE0_RESET_PU_MASK BIT(8)
-#define AN7583_MDIO_0_PU_MASK BIT(5)
-#define AN7583_MDC_0_PU_MASK BIT(4)
-#define UART1_RXD_PU_MASK BIT(3)
-#define UART1_TXD_PU_MASK BIT(2)
-#define I2C_SCL_PU_MASK BIT(1)
-#define I2C_SDA_PU_MASK BIT(0)
-
-#define REG_I2C_SDA_PD 0x0048
-#define AN7583_I2C1_SCL_PD_MASK BIT(16)
-#define AN7583_I2C1_SDA_PD_MASK BIT(15)
-#define SPI_MISO_PD_MASK BIT(14)
-#define SPI_MOSI_PD_MASK BIT(13)
-#define SPI_CLK_PD_MASK BIT(12)
-#define SPI_CS0_PD_MASK BIT(11)
-#define PCIE2_RESET_PD_MASK BIT(10)
-#define PCIE1_RESET_PD_MASK BIT(9)
-#define PCIE0_RESET_PD_MASK BIT(8)
-#define AN7583_MDIO_0_PD_MASK BIT(5)
-#define AN7583_MDC_0_PD_MASK BIT(4)
-#define UART1_RXD_PD_MASK BIT(3)
-#define UART1_TXD_PD_MASK BIT(2)
-#define I2C_SCL_PD_MASK BIT(1)
-#define I2C_SDA_PD_MASK BIT(0)
-
-#define REG_GPIO_L_PU 0x004c
-#define REG_GPIO_L_PD 0x0050
-#define REG_GPIO_H_PU 0x0054
-#define REG_GPIO_H_PD 0x0058
-
-#define REG_PCIE_RESET_OD 0x018c
-#define PCIE2_RESET_OD_MASK BIT(2)
-#define PCIE1_RESET_OD_MASK BIT(1)
-#define PCIE0_RESET_OD_MASK BIT(0)
-
-/* GPIOs */
-#define REG_GPIO_CTRL 0x0000
-#define REG_GPIO_DATA 0x0004
-#define REG_GPIO_INT 0x0008
-#define REG_GPIO_INT_EDGE 0x000c
-#define REG_GPIO_INT_LEVEL 0x0010
-#define REG_GPIO_OE 0x0014
-#define REG_GPIO_CTRL1 0x0020
-#define REG_GPIO_CTRL2 0x0060
-#define REG_GPIO_CTRL3 0x0064
-
-/* PWM MODE CONF */
-#define REG_GPIO_FLASH_MODE_CFG 0x0034
-#define GPIO15_FLASH_MODE_CFG BIT(15)
-#define GPIO14_FLASH_MODE_CFG BIT(14)
-#define GPIO13_FLASH_MODE_CFG BIT(13)
-#define GPIO12_FLASH_MODE_CFG BIT(12)
-#define GPIO11_FLASH_MODE_CFG BIT(11)
-#define GPIO10_FLASH_MODE_CFG BIT(10)
-#define GPIO9_FLASH_MODE_CFG BIT(9)
-#define GPIO8_FLASH_MODE_CFG BIT(8)
-#define GPIO7_FLASH_MODE_CFG BIT(7)
-#define GPIO6_FLASH_MODE_CFG BIT(6)
-#define GPIO5_FLASH_MODE_CFG BIT(5)
-#define GPIO4_FLASH_MODE_CFG BIT(4)
-#define GPIO3_FLASH_MODE_CFG BIT(3)
-#define GPIO2_FLASH_MODE_CFG BIT(2)
-#define GPIO1_FLASH_MODE_CFG BIT(1)
-#define GPIO0_FLASH_MODE_CFG BIT(0)
-
-/* PWM MODE CONF EXT */
-#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
-#define GPIO51_FLASH_MODE_CFG BIT(31)
-#define GPIO50_FLASH_MODE_CFG BIT(30)
-#define GPIO49_FLASH_MODE_CFG BIT(29)
-#define GPIO48_FLASH_MODE_CFG BIT(28)
-#define GPIO47_FLASH_MODE_CFG BIT(27)
-#define GPIO46_FLASH_MODE_CFG BIT(26)
-#define GPIO45_FLASH_MODE_CFG BIT(25)
-#define GPIO44_FLASH_MODE_CFG BIT(24)
-#define GPIO43_FLASH_MODE_CFG BIT(23)
-#define GPIO42_FLASH_MODE_CFG BIT(22)
-#define GPIO41_FLASH_MODE_CFG BIT(21)
-#define GPIO40_FLASH_MODE_CFG BIT(20)
-#define GPIO39_FLASH_MODE_CFG BIT(19)
-#define GPIO38_FLASH_MODE_CFG BIT(18)
-#define GPIO37_FLASH_MODE_CFG BIT(17)
-#define GPIO36_FLASH_MODE_CFG BIT(16)
-#define GPIO31_FLASH_MODE_CFG BIT(15)
-#define GPIO30_FLASH_MODE_CFG BIT(14)
-#define GPIO29_FLASH_MODE_CFG BIT(13)
-#define GPIO28_FLASH_MODE_CFG BIT(12)
-#define GPIO27_FLASH_MODE_CFG BIT(11)
-#define GPIO26_FLASH_MODE_CFG BIT(10)
-#define GPIO25_FLASH_MODE_CFG BIT(9)
-#define GPIO24_FLASH_MODE_CFG BIT(8)
-#define GPIO23_FLASH_MODE_CFG BIT(7)
-#define GPIO22_FLASH_MODE_CFG BIT(6)
-#define GPIO21_FLASH_MODE_CFG BIT(5)
-#define GPIO20_FLASH_MODE_CFG BIT(4)
-#define GPIO19_FLASH_MODE_CFG BIT(3)
-#define GPIO18_FLASH_MODE_CFG BIT(2)
-#define GPIO17_FLASH_MODE_CFG BIT(1)
-#define GPIO16_FLASH_MODE_CFG BIT(0)
-
-#define REG_GPIO_DATA1 0x0070
-#define REG_GPIO_OE1 0x0078
-#define REG_GPIO_INT1 0x007c
-#define REG_GPIO_INT_EDGE1 0x0080
-#define REG_GPIO_INT_EDGE2 0x0084
-#define REG_GPIO_INT_EDGE3 0x0088
-#define REG_GPIO_INT_LEVEL1 0x008c
-#define REG_GPIO_INT_LEVEL2 0x0090
-#define REG_GPIO_INT_LEVEL3 0x0094
-
-#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_PON_MODE, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap_size = 1, \
- }
-
-#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_EXT_MUX, \
- REG_GPIO_FLASH_MODE_CFG_EXT, \
- (mux_val), \
- 0 \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_PON_MODE, \
- (smux_val), \
- (smux_val) \
- }, \
- .regmap_size = 2, \
- }
-
-/* PWM */
-#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_MUX, \
- REG_GPIO_FLASH_MODE_CFG, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap_size = 1, \
- }
-
-#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_EXT_MUX, \
- REG_GPIO_FLASH_MODE_CFG_EXT, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap_size = 1, \
- }
-
-#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_EXT_MUX, \
- REG_GPIO_FLASH_MODE_CFG_EXT, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_PON_MODE, \
- (smux_val), \
- (smux_val) \
- }, \
- .regmap_size = 2, \
- }
-
-#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
- (mux_val), \
- (mux_val), \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_LAN_LED0_MAPPING, \
- (map_mask), \
- (map_val), \
- }, \
- .regmap_size = 2, \
- }
-
-#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
- (mux_val), \
- (mux_val), \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_LAN_LED1_MAPPING, \
- (map_mask), \
- (map_val), \
- }, \
- .regmap_size = 2, \
- }
-
#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
(pin), (val))
@@ -433,1935 +74,6 @@ static const u32 irq_edge_regs[] = {
REG_GPIO_INT_EDGE3
};
-static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
- PINCTRL_PIN(0, "uart1_txd"),
- PINCTRL_PIN(1, "uart1_rxd"),
- PINCTRL_PIN(2, "i2c_scl"),
- PINCTRL_PIN(3, "i2c_sda"),
- PINCTRL_PIN(4, "spi_cs0"),
- PINCTRL_PIN(5, "spi_clk"),
- PINCTRL_PIN(6, "spi_mosi"),
- PINCTRL_PIN(7, "spi_miso"),
- PINCTRL_PIN(13, "gpio0"),
- PINCTRL_PIN(14, "gpio1"),
- PINCTRL_PIN(15, "gpio2"),
- PINCTRL_PIN(16, "gpio3"),
- PINCTRL_PIN(17, "gpio4"),
- PINCTRL_PIN(18, "gpio5"),
- PINCTRL_PIN(19, "gpio6"),
- PINCTRL_PIN(20, "gpio7"),
- PINCTRL_PIN(21, "gpio8"),
- PINCTRL_PIN(22, "gpio9"),
- PINCTRL_PIN(23, "gpio10"),
- PINCTRL_PIN(24, "gpio11"),
- PINCTRL_PIN(25, "gpio12"),
- PINCTRL_PIN(26, "gpio13"),
- PINCTRL_PIN(27, "gpio14"),
- PINCTRL_PIN(28, "gpio15"),
- PINCTRL_PIN(29, "gpio16"),
- PINCTRL_PIN(30, "gpio17"),
- PINCTRL_PIN(31, "gpio18"),
- PINCTRL_PIN(32, "gpio19"),
- PINCTRL_PIN(33, "gpio20"),
- PINCTRL_PIN(34, "gpio21"),
- PINCTRL_PIN(35, "gpio22"),
- PINCTRL_PIN(36, "gpio23"),
- PINCTRL_PIN(37, "gpio24"),
- PINCTRL_PIN(38, "gpio25"),
- PINCTRL_PIN(39, "gpio26"),
- PINCTRL_PIN(40, "gpio27"),
- PINCTRL_PIN(41, "gpio28"),
- PINCTRL_PIN(42, "gpio29"),
- PINCTRL_PIN(43, "gpio30"),
- PINCTRL_PIN(44, "gpio31"),
- PINCTRL_PIN(45, "gpio32"),
- PINCTRL_PIN(46, "gpio33"),
- PINCTRL_PIN(47, "gpio34"),
- PINCTRL_PIN(48, "gpio35"),
- PINCTRL_PIN(49, "gpio36"),
- PINCTRL_PIN(50, "gpio37"),
- PINCTRL_PIN(51, "gpio38"),
- PINCTRL_PIN(52, "gpio39"),
- PINCTRL_PIN(53, "gpio40"),
- PINCTRL_PIN(54, "gpio41"),
- PINCTRL_PIN(55, "gpio42"),
- PINCTRL_PIN(56, "gpio43"),
- PINCTRL_PIN(57, "gpio44"),
- PINCTRL_PIN(58, "gpio45"),
- PINCTRL_PIN(59, "gpio46"),
- PINCTRL_PIN(60, "pcie_reset0"),
- PINCTRL_PIN(61, "pcie_reset1"),
- PINCTRL_PIN(62, "pcie_reset2"),
-};
-
-static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
-static const int en7581_pon_tod_1pps_pins[] = { 46 };
-static const int en7581_gsw_tod_1pps_pins[] = { 46 };
-static const int en7581_sipo_pins[] = { 16, 17 };
-static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
-static const int en7581_mdio_pins[] = { 14, 15 };
-static const int en7581_uart2_pins[] = { 48, 55 };
-static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
-static const int en7581_hsuart_pins[] = { 28, 29 };
-static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
-static const int en7581_uart4_pins[] = { 38, 39 };
-static const int en7581_uart5_pins[] = { 18, 19 };
-static const int en7581_i2c0_pins[] = { 2, 3 };
-static const int en7581_i2c1_pins[] = { 14, 15 };
-static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
-static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
-static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
-static const int en7581_spi_quad_pins[] = { 32, 33 };
-static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
-static const int en7581_spi_cs1_pins[] = { 34 };
-static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
-static const int en7581_pcm_spi_int_pins[] = { 14 };
-static const int en7581_pcm_spi_rst_pins[] = { 15 };
-static const int en7581_pcm_spi_cs1_pins[] = { 43 };
-static const int en7581_pcm_spi_cs2_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
-static const int en7581_pcm_spi_cs3_pins[] = { 41 };
-static const int en7581_pcm_spi_cs4_pins[] = { 42 };
-static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
-static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
-static const int en7581_gpio0_pins[] = { 13 };
-static const int en7581_gpio1_pins[] = { 14 };
-static const int en7581_gpio2_pins[] = { 15 };
-static const int en7581_gpio3_pins[] = { 16 };
-static const int en7581_gpio4_pins[] = { 17 };
-static const int en7581_gpio5_pins[] = { 18 };
-static const int en7581_gpio6_pins[] = { 19 };
-static const int en7581_gpio7_pins[] = { 20 };
-static const int en7581_gpio8_pins[] = { 21 };
-static const int en7581_gpio9_pins[] = { 22 };
-static const int en7581_gpio10_pins[] = { 23 };
-static const int en7581_gpio11_pins[] = { 24 };
-static const int en7581_gpio12_pins[] = { 25 };
-static const int en7581_gpio13_pins[] = { 26 };
-static const int en7581_gpio14_pins[] = { 27 };
-static const int en7581_gpio15_pins[] = { 28 };
-static const int en7581_gpio16_pins[] = { 29 };
-static const int en7581_gpio17_pins[] = { 30 };
-static const int en7581_gpio18_pins[] = { 31 };
-static const int en7581_gpio19_pins[] = { 32 };
-static const int en7581_gpio20_pins[] = { 33 };
-static const int en7581_gpio21_pins[] = { 34 };
-static const int en7581_gpio22_pins[] = { 35 };
-static const int en7581_gpio23_pins[] = { 36 };
-static const int en7581_gpio24_pins[] = { 37 };
-static const int en7581_gpio25_pins[] = { 38 };
-static const int en7581_gpio26_pins[] = { 39 };
-static const int en7581_gpio27_pins[] = { 40 };
-static const int en7581_gpio28_pins[] = { 41 };
-static const int en7581_gpio29_pins[] = { 42 };
-static const int en7581_gpio30_pins[] = { 43 };
-static const int en7581_gpio31_pins[] = { 44 };
-static const int en7581_gpio32_pins[] = { 45 };
-static const int en7581_gpio33_pins[] = { 46 };
-static const int en7581_gpio34_pins[] = { 47 };
-static const int en7581_gpio35_pins[] = { 48 };
-static const int en7581_gpio36_pins[] = { 49 };
-static const int en7581_gpio37_pins[] = { 50 };
-static const int en7581_gpio38_pins[] = { 51 };
-static const int en7581_gpio39_pins[] = { 52 };
-static const int en7581_gpio40_pins[] = { 53 };
-static const int en7581_gpio41_pins[] = { 54 };
-static const int en7581_gpio42_pins[] = { 55 };
-static const int en7581_gpio43_pins[] = { 56 };
-static const int en7581_gpio44_pins[] = { 57 };
-static const int en7581_gpio45_pins[] = { 58 };
-static const int en7581_gpio46_pins[] = { 59 };
-static const int en7581_gpio47_pins[] = { 60 };
-static const int en7581_gpio48_pins[] = { 61 };
-static const int en7581_gpio49_pins[] = { 62 };
-static const int en7581_pcie_reset0_pins[] = { 60 };
-static const int en7581_pcie_reset1_pins[] = { 61 };
-static const int en7581_pcie_reset2_pins[] = { 62 };
-
-static const struct pingroup en7581_pinctrl_groups[] = {
- PINCTRL_PIN_GROUP("pon", en7581_pon),
- PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
- PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
- PINCTRL_PIN_GROUP("sipo", en7581_sipo),
- PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
- PINCTRL_PIN_GROUP("mdio", en7581_mdio),
- PINCTRL_PIN_GROUP("uart2", en7581_uart2),
- PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
- PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
- PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
- PINCTRL_PIN_GROUP("uart4", en7581_uart4),
- PINCTRL_PIN_GROUP("uart5", en7581_uart5),
- PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
- PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
- PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
- PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
- PINCTRL_PIN_GROUP("i2s", en7581_i2s),
- PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
- PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
- PINCTRL_PIN_GROUP("spi", en7581_spi),
- PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
- PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
- PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
- PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
- PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
- PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
- PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
- PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
- PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
- PINCTRL_PIN_GROUP("emmc", en7581_emmc),
- PINCTRL_PIN_GROUP("pnand", en7581_pnand),
- PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
- PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
- PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
- PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
- PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
- PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
- PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
- PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
- PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
- PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
- PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
- PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
- PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
- PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
- PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
- PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
- PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
- PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
- PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
- PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
- PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
- PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
- PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
- PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
- PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
- PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
- PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
- PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
- PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
- PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
- PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
- PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
- PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
- PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
- PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
- PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
- PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
- PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
- PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
- PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
- PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
- PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
- PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
- PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
- PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
- PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
- PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
- PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
- PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
- PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
- PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
- PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
- PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
-};
-
-static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
- PINCTRL_PIN(2, "gpio0"),
- PINCTRL_PIN(3, "gpio1"),
- PINCTRL_PIN(4, "gpio2"),
- PINCTRL_PIN(5, "gpio3"),
- PINCTRL_PIN(6, "gpio4"),
- PINCTRL_PIN(7, "gpio5"),
- PINCTRL_PIN(8, "gpio6"),
- PINCTRL_PIN(9, "gpio7"),
- PINCTRL_PIN(10, "gpio8"),
- PINCTRL_PIN(11, "gpio9"),
- PINCTRL_PIN(12, "gpio10"),
- PINCTRL_PIN(13, "gpio11"),
- PINCTRL_PIN(14, "gpio12"),
- PINCTRL_PIN(15, "gpio13"),
- PINCTRL_PIN(16, "gpio14"),
- PINCTRL_PIN(17, "gpio15"),
- PINCTRL_PIN(18, "gpio16"),
- PINCTRL_PIN(19, "gpio17"),
- PINCTRL_PIN(20, "gpio18"),
- PINCTRL_PIN(21, "gpio19"),
- PINCTRL_PIN(22, "gpio20"),
- PINCTRL_PIN(23, "gpio21"),
- PINCTRL_PIN(24, "gpio22"),
- PINCTRL_PIN(25, "gpio23"),
- PINCTRL_PIN(26, "gpio24"),
- PINCTRL_PIN(27, "gpio25"),
- PINCTRL_PIN(28, "gpio26"),
- PINCTRL_PIN(29, "gpio27"),
- PINCTRL_PIN(30, "gpio28"),
- PINCTRL_PIN(31, "gpio29"),
- PINCTRL_PIN(32, "gpio30"),
- PINCTRL_PIN(33, "gpio31"),
- PINCTRL_PIN(34, "gpio32"),
- PINCTRL_PIN(35, "gpio33"),
- PINCTRL_PIN(36, "gpio34"),
- PINCTRL_PIN(37, "gpio35"),
- PINCTRL_PIN(38, "gpio36"),
- PINCTRL_PIN(39, "gpio37"),
- PINCTRL_PIN(40, "gpio38"),
- PINCTRL_PIN(41, "i2c0_scl"),
- PINCTRL_PIN(42, "i2c0_sda"),
- PINCTRL_PIN(43, "i2c1_scl"),
- PINCTRL_PIN(44, "i2c1_sda"),
- PINCTRL_PIN(45, "spi_clk"),
- PINCTRL_PIN(46, "spi_cs"),
- PINCTRL_PIN(47, "spi_mosi"),
- PINCTRL_PIN(48, "spi_miso"),
- PINCTRL_PIN(49, "uart_txd"),
- PINCTRL_PIN(50, "uart_rxd"),
- PINCTRL_PIN(51, "pcie_reset0"),
- PINCTRL_PIN(52, "pcie_reset1"),
- PINCTRL_PIN(53, "mdc_0"),
- PINCTRL_PIN(54, "mdio_0"),
-};
-
-static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
-static const int an7583_pon_tod_1pps_pins[] = { 32 };
-static const int an7583_gsw_tod_1pps_pins[] = { 32 };
-static const int an7583_sipo_pins[] = { 34, 35 };
-static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
-static const int an7583_mdio_pins[] = { 43, 44 };
-static const int an7583_uart2_pins[] = { 34, 35 };
-static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
-static const int an7583_hsuart_pins[] = { 30, 31 };
-static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
-static const int an7583_npu_uart_pins[] = { 7, 8 };
-static const int an7583_uart4_pins[] = { 7, 8 };
-static const int an7583_uart5_pins[] = { 23, 24 };
-static const int an7583_i2c0_pins[] = { 41, 42 };
-static const int an7583_i2c1_pins[] = { 43, 44 };
-static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
-static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
-static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
-static const int an7583_spi_quad_pins[] = { 25, 26 };
-static const int an7583_spi_cs1_pins[] = { 27 };
-static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
-static const int an7583_pcm_spi_rst_pins[] = { 14 };
-static const int an7583_pcm_spi_cs1_pins[] = { 24 };
-static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
-static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
-static const int an7583_gpio0_pins[] = { 2 };
-static const int an7583_gpio1_pins[] = { 3 };
-static const int an7583_gpio2_pins[] = { 4 };
-static const int an7583_gpio3_pins[] = { 5 };
-static const int an7583_gpio4_pins[] = { 6 };
-static const int an7583_gpio5_pins[] = { 7 };
-static const int an7583_gpio6_pins[] = { 8 };
-static const int an7583_gpio7_pins[] = { 9 };
-static const int an7583_gpio8_pins[] = { 10 };
-static const int an7583_gpio9_pins[] = { 11 };
-static const int an7583_gpio10_pins[] = { 12 };
-static const int an7583_gpio11_pins[] = { 13 };
-static const int an7583_gpio12_pins[] = { 14 };
-static const int an7583_gpio13_pins[] = { 15 };
-static const int an7583_gpio14_pins[] = { 16 };
-static const int an7583_gpio15_pins[] = { 17 };
-static const int an7583_gpio16_pins[] = { 18 };
-static const int an7583_gpio17_pins[] = { 19 };
-static const int an7583_gpio18_pins[] = { 20 };
-static const int an7583_gpio19_pins[] = { 21 };
-static const int an7583_gpio20_pins[] = { 22 };
-static const int an7583_gpio21_pins[] = { 23 };
-static const int an7583_gpio22_pins[] = { 24 };
-static const int an7583_gpio23_pins[] = { 25 };
-static const int an7583_gpio24_pins[] = { 26 };
-static const int an7583_gpio25_pins[] = { 27 };
-static const int an7583_gpio26_pins[] = { 28 };
-static const int an7583_gpio27_pins[] = { 29 };
-static const int an7583_gpio28_pins[] = { 30 };
-static const int an7583_gpio29_pins[] = { 31 };
-static const int an7583_gpio30_pins[] = { 32 };
-static const int an7583_gpio31_pins[] = { 33 };
-static const int an7583_gpio32_pins[] = { 34 };
-static const int an7583_gpio33_pins[] = { 35 };
-static const int an7583_gpio34_pins[] = { 36 };
-static const int an7583_gpio35_pins[] = { 37 };
-static const int an7583_gpio36_pins[] = { 38 };
-static const int an7583_gpio37_pins[] = { 39 };
-static const int an7583_gpio38_pins[] = { 40 };
-static const int an7583_gpio39_pins[] = { 41 };
-static const int an7583_gpio40_pins[] = { 42 };
-static const int an7583_gpio41_pins[] = { 43 };
-static const int an7583_gpio42_pins[] = { 44 };
-static const int an7583_gpio43_pins[] = { 45 };
-static const int an7583_gpio44_pins[] = { 46 };
-static const int an7583_gpio45_pins[] = { 47 };
-static const int an7583_gpio46_pins[] = { 48 };
-static const int an7583_gpio47_pins[] = { 49 };
-static const int an7583_gpio48_pins[] = { 50 };
-static const int an7583_gpio49_pins[] = { 51 };
-static const int an7583_gpio50_pins[] = { 52 };
-static const int an7583_gpio51_pins[] = { 53 };
-static const int an7583_gpio52_pins[] = { 54 };
-static const int an7583_pcie_reset0_pins[] = { 51 };
-static const int an7583_pcie_reset1_pins[] = { 52 };
-
-static const struct pingroup an7583_pinctrl_groups[] = {
- PINCTRL_PIN_GROUP("pon", an7583_pon),
- PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
- PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
- PINCTRL_PIN_GROUP("sipo", an7583_sipo),
- PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
- PINCTRL_PIN_GROUP("mdio", an7583_mdio),
- PINCTRL_PIN_GROUP("uart2", an7583_uart2),
- PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
- PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
- PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
- PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
- PINCTRL_PIN_GROUP("uart4", an7583_uart4),
- PINCTRL_PIN_GROUP("uart5", an7583_uart5),
- PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
- PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
- PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
- PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
- PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
- PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
- PINCTRL_PIN_GROUP("spi", an7583_spi),
- PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
- PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
- PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
- PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
- PINCTRL_PIN_GROUP("emmc", an7583_emmc),
- PINCTRL_PIN_GROUP("pnand", an7583_pnand),
- PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
- PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
- PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
- PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
- PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
- PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
- PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
- PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
- PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
- PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
- PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
- PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
- PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
- PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
- PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
- PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
- PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
- PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
- PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
- PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
- PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
- PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
- PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
- PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
- PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
- PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
- PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
- PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
- PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
- PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
- PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
- PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
- PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
- PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
- PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
- PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
- PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
- PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
- PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
- PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
- PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
- PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
- PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
- PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
- PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
- PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
- PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
- PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
- PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
- PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
- PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
- PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
- PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
- PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
- PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
-};
-
-static const char *const pon_groups[] = { "pon" };
-static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
-static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
-static const char *const mdio_groups[] = { "mdio" };
-static const char *const an7583_mdio_groups[] = { "mdio" };
-static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
- "hsuart_cts_rts", "uart4",
- "uart5" };
-static const char *const i2c_groups[] = { "i2c1" };
-static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
-static const char *const pcm_groups[] = { "pcm1", "pcm2" };
-static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
-static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
- "pcm_spi_rst", "pcm_spi_cs1",
- "pcm_spi_cs2_p156",
- "pcm_spi_cs2_p128",
- "pcm_spi_cs3", "pcm_spi_cs4" };
-static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
- "pcm_spi_rst", "pcm_spi_cs1" };
-static const char *const i2s_groups[] = { "i2s" };
-static const char *const emmc_groups[] = { "emmc" };
-static const char *const pnand_groups[] = { "pnand" };
-static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
-static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
- "pcie_reset2" };
-static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
- "gpio42", "gpio43", "gpio44",
- "gpio45", "gpio46", "gpio47",
- "gpio48", "gpio49", "gpio50",
- "gpio51", "gpio52" };
-static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
-static const char *const pwm_groups[] = { "gpio0", "gpio1",
- "gpio2", "gpio3",
- "gpio4", "gpio5",
- "gpio6", "gpio7",
- "gpio8", "gpio9",
- "gpio10", "gpio11",
- "gpio12", "gpio13",
- "gpio14", "gpio15",
- "gpio16", "gpio17",
- "gpio18", "gpio19",
- "gpio20", "gpio21",
- "gpio22", "gpio23",
- "gpio24", "gpio25",
- "gpio26", "gpio27",
- "gpio28", "gpio29",
- "gpio30", "gpio31",
- "gpio36", "gpio37",
- "gpio38", "gpio39",
- "gpio40", "gpio41",
- "gpio42", "gpio43",
- "gpio44", "gpio45",
- "gpio46", "gpio47",
- "gpio48", "gpio49" };
-static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
- "gpio2", "gpio3",
- "gpio4", "gpio5",
- "gpio6", "gpio7",
- "gpio8", "gpio9",
- "gpio10", "gpio11",
- "gpio12", "gpio13",
- "gpio14", "gpio15",
- "gpio16", "gpio17",
- "gpio18", "gpio19",
- "gpio20", "gpio21",
- "gpio22", "gpio23",
- "gpio24", "gpio25",
- "gpio26", "gpio27",
- "gpio28", "gpio29",
- "gpio30", "gpio31",
- "gpio36", "gpio37",
- "gpio38", "gpio39",
- "gpio40", "gpio41",
- "gpio42", "gpio43",
- "gpio44", "gpio45",
- "gpio46", "gpio47",
- "gpio48", "gpio49",
- "gpio50", "gpio51" };
-static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
- "gpio35", "gpio42" };
-static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
- "gpio35", "gpio42" };
-static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
- "gpio35", "gpio42" };
-static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
- "gpio35", "gpio42" };
-static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
- "gpio45", "gpio46" };
-static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
- "gpio45", "gpio46" };
-static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
- "gpio45", "gpio46" };
-static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
- "gpio45", "gpio46" };
-static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
- "gpio3", "gpio4" };
-static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
- "gpio3", "gpio4" };
-static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
- "gpio3", "gpio4" };
-static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
- "gpio3", "gpio4" };
-static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
- "gpio10", "gpio11" };
-static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
- "gpio10", "gpio11" };
-static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
- "gpio10", "gpio11" };
-static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
- "gpio10", "gpio11" };
-
-static const struct airoha_pinctrl_func_group pon_func_group[] = {
- {
- .name = "pon",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PON_MODE_MASK,
- GPIO_PON_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
- {
- .name = "pon_tod_1pps",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
- PON_TOD_1PPS_MODE_MASK,
- PON_TOD_1PPS_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "gsw_tod_1pps",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
- GSW_TOD_1PPS_MODE_MASK,
- GSW_TOD_1PPS_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group sipo_func_group[] = {
- {
- .name = "sipo",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
- GPIO_SIPO_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "sipo_rclk",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
- GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group mdio_func_group[] = {
- {
- .name = "mdio",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
- GPIO_MDC_IO_MASTER_MODE_MASK,
- GPIO_MDC_IO_MASTER_MODE_MASK
- },
- .regmap[1] = {
- AIROHA_FUNC_MUX,
- REG_FORCE_GPIO_EN,
- FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
- FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
- },
- .regmap_size = 2,
- },
-};
-
-static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
- {
- .name = "mdio",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_SGMII_MDIO_MODE_MASK,
- GPIO_SGMII_MDIO_MODE_MASK
- },
- .regmap[1] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_MDC_IO_MASTER_MODE_MASK,
- GPIO_MDC_IO_MASTER_MODE_MASK
- },
- .regmap_size = 2,
- },
-};
-
-static const struct airoha_pinctrl_func_group uart_func_group[] = {
- {
- .name = "uart2",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_UART2_MODE_MASK,
- GPIO_UART2_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "uart2_cts_rts",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
- GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "hsuart",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
- GPIO_HSUART_MODE_MASK
- },
- .regmap_size = 1,
- },
- {
- .name = "hsuart_cts_rts",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
- GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "uart4",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_UART4_MODE_MASK,
- GPIO_UART4_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "uart5",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_UART5_MODE_MASK,
- GPIO_UART5_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group i2c_func_group[] = {
- {
- .name = "i2c1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
- GPIO_2ND_I2C_MODE_MASK,
- GPIO_2ND_I2C_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group jtag_func_group[] = {
- {
- .name = "jtag_udi",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_NPU_UART_EN,
- JTAG_UDI_EN_MASK,
- JTAG_UDI_EN_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "jtag_dfd",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_NPU_UART_EN,
- JTAG_DFD_EN_MASK,
- JTAG_DFD_EN_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group pcm_func_group[] = {
- {
- .name = "pcm1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM1_MODE_MASK,
- GPIO_PCM1_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm2",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM2_MODE_MASK,
- GPIO_PCM2_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group spi_func_group[] = {
- {
- .name = "spi_quad",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_SPI_QUAD_MODE_MASK,
- GPIO_SPI_QUAD_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "spi_cs1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_SPI_CS1_MODE_MASK,
- GPIO_SPI_CS1_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "spi_cs2",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_SPI_CS2_MODE_MASK,
- GPIO_SPI_CS2_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "spi_cs3",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_SPI_CS3_MODE_MASK,
- GPIO_SPI_CS3_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "spi_cs4",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_SPI_CS4_MODE_MASK,
- GPIO_SPI_CS4_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
- {
- .name = "pcm_spi",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_MODE_MASK,
- GPIO_PCM_SPI_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_int",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_INT_MODE_MASK,
- GPIO_PCM_INT_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_rst",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_RESET_MODE_MASK,
- GPIO_PCM_RESET_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS1_MODE_MASK,
- GPIO_PCM_SPI_CS1_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs2_p128",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS2_MODE_P128_MASK,
- GPIO_PCM_SPI_CS2_MODE_P128_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs2_p156",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS2_MODE_P156_MASK,
- GPIO_PCM_SPI_CS2_MODE_P156_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs3",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS3_MODE_MASK,
- GPIO_PCM_SPI_CS3_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs4",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS4_MODE_MASK,
- GPIO_PCM_SPI_CS4_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
- {
- .name = "pcm_spi",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_MODE_MASK,
- GPIO_PCM_SPI_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_int",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_INT_MODE_MASK,
- GPIO_PCM_INT_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_rst",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_RESET_MODE_MASK,
- GPIO_PCM_RESET_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS1_MODE_MASK,
- GPIO_PCM_SPI_CS1_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs2",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
- AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs3",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS3_MODE_MASK,
- GPIO_PCM_SPI_CS3_MODE_MASK
- },
- .regmap_size = 1,
- }, {
- .name = "pcm_spi_cs4",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
- GPIO_PCM_SPI_CS4_MODE_MASK,
- GPIO_PCM_SPI_CS4_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group i2s_func_group[] = {
- {
- .name = "i2s",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
- GPIO_I2S_MODE_MASK,
- GPIO_I2S_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group emmc_func_group[] = {
- {
- .name = "emmc",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_EMMC_MODE_MASK,
- GPIO_EMMC_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group pnand_func_group[] = {
- {
- .name = "pnand",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PARALLEL_NAND_MODE_MASK,
- GPIO_PARALLEL_NAND_MODE_MASK
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group gpio_func_group[] = {
- AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
- GPIO_PCIE_RESET0_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
- GPIO_PCIE_RESET1_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
- GPIO_PCIE_RESET2_MASK),
-};
-
-static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
- {
- .name = "pcie_reset0",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PCIE_RESET0_MASK,
- 0
- },
- .regmap_size = 1,
- }, {
- .name = "pcie_reset1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PCIE_RESET1_MASK,
- 0
- },
- .regmap_size = 1,
- }, {
- .name = "pcie_reset2",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PCIE_RESET2_MASK,
- 0
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
- AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
- AN7583_I2C0_SCL_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
- AN7583_I2C0_SDA_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
- AN7583_I2C1_SCL_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
- AN7583_I2C1_SDA_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
- AN7583_SPI_CLK_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
- AN7583_SPI_CS_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
- AN7583_SPI_MOSI_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
- AN7583_SPI_MISO_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
- AN7583_UART_TXD_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
- AN7583_UART_RXD_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
- GPIO_PCIE_RESET0_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
- GPIO_PCIE_RESET1_MASK),
- AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
- AN7583_MDC_0_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
-};
-
-static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
- {
- .name = "pcie_reset0",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PCIE_RESET0_MASK,
- 0
- },
- .regmap_size = 1,
- }, {
- .name = "pcie_reset1",
- .regmap[0] = {
- AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
- GPIO_PCIE_RESET1_MASK,
- 0
- },
- .regmap_size = 1,
- },
-};
-
-static const struct airoha_pinctrl_func_group pwm_func_group[] = {
- AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
- GPIO_PCIE_RESET0_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
- GPIO_PCIE_RESET1_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
- GPIO_PCIE_RESET2_MASK),
-};
-
-static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
- AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
- AN7583_I2C0_SCL_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
- AN7583_I2C0_SDA_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
- AN7583_I2C1_SCL_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
- AN7583_I2C1_SDA_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
- AN7583_SPI_CLK_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
- AN7583_SPI_CS_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
- AN7583_SPI_MOSI_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
- AN7583_SPI_MISO_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
- AN7583_UART_TXD_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
- AN7583_UART_RXD_GPIO_MODE_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
- GPIO_PCIE_RESET0_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
- GPIO_PCIE_RESET1_MASK),
- AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
- AN7583_MDC_0_GPIO_MODE_MASK),
-};
-
-static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
-};
-
-static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
- LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
- LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
- LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
-};
-
-static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
- PINCTRL_FUNC_DESC("pon", pon),
- PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
- PINCTRL_FUNC_DESC("sipo", sipo),
- PINCTRL_FUNC_DESC("mdio", mdio),
- PINCTRL_FUNC_DESC("uart", uart),
- PINCTRL_FUNC_DESC("i2c", i2c),
- PINCTRL_FUNC_DESC("jtag", jtag),
- PINCTRL_FUNC_DESC("pcm", pcm),
- PINCTRL_FUNC_DESC("spi", spi),
- PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
- PINCTRL_FUNC_DESC("i2s", i2s),
- PINCTRL_FUNC_DESC("emmc", emmc),
- PINCTRL_FUNC_DESC("pnand", pnand),
- PINCTRL_FUNC_DESC("gpio", gpio),
- PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
- PINCTRL_FUNC_DESC("pwm", pwm),
- PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
- PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
- PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
- PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
- PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
- PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
- PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
- PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
-};
-
-static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
- PINCTRL_FUNC_DESC("pon", pon),
- PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
- PINCTRL_FUNC_DESC("sipo", sipo),
- PINCTRL_FUNC_DESC("mdio", an7583_mdio),
- PINCTRL_FUNC_DESC("uart", uart),
- PINCTRL_FUNC_DESC("jtag", jtag),
- PINCTRL_FUNC_DESC("pcm", pcm),
- PINCTRL_FUNC_DESC("spi", spi),
- PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
- PINCTRL_FUNC_DESC("emmc", emmc),
- PINCTRL_FUNC_DESC("pnand", pnand),
- PINCTRL_FUNC_DESC("gpio", an7583_gpio),
- PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
- PINCTRL_FUNC_DESC("pwm", an7583_pwm),
- PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
- PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
- PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
- PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
- PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
- PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
- PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
- PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
- PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
- PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
- PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
- PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
- PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
- PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
- PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
- PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
- PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
- PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
- PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
- PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
- PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
- PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
- PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
- PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
- PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
- PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
- PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
- PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
- PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
- PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
- PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
- PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
- PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
- PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
- PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
- PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
- PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
- PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
- PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
- PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
- PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
- PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
- PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
- PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
- PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
- PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
- PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
- PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
- PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
- PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
- PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
- PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
- PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
- PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
- PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
- PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
- PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
- PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
- PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
- PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
- PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
- PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
- PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
- PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
- PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
- PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
- PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
- PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
- PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
- PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
- PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
- PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
- PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
- PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
- PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
- PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
- PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
- PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
- PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
- PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
- PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
- PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
- PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
- PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
- PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
- PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
- PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
- PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
- PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
- PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
- PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
- PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
- PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
- PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
- PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
- PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
- PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
- PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
- PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
- PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
- PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
- PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
- PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
- PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
- PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
- PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
- PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
- PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
- PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
- PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
- PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
- PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
- PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
- PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
- PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
- PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
- PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
- PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
- PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
- PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
- PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
- PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
- PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
- PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
- PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
- PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
- PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
- PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
- PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
- PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
- PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
- PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
- PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
- PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
- PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
- PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
- PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
- PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
- PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
- PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
- PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
- PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
- PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
- PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
- PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
- PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
- PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
- PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
- PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
- PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
- PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
- PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
- PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
- PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
- PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
- PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
- PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
- PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
- PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
- PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
- PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
- PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
- PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
- PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
- PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
- PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
- PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
- PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
- PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
- PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
- PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
- PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
- PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
- PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
- PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
- PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
- PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
- PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
- PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
- PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
- PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
- PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
- PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
- PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
- PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
- PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
- PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
- PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
- PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
- PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
- PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
- PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
- PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
- PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
- PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
- PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
- PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
- PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
- PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
- PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
- PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
- PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
- PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
- PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
- PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
- PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
- PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
- PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
- PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
- PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
- PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
- PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
- PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
- PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
- PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
- PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
- PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
- PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
- PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
- PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
- PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
- PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
- PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
- PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
- PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
- PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
- PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
- PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
- PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
- PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
- PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
- PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
- PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
- PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
- PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
- PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
- PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
- PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
- PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
- PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
- PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
- PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
- PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
- PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
- PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
- PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
- PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
- PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
- PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
- PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
- PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
- PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
- PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
- PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
- PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
- PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
- PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
- PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
- PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
- PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
- PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
- PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
- PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
- PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
- PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
- PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
- PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
- PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
- PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
- PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
- PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
- PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
- PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
- PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
- PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
- PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
- PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
- PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
- PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
- PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
-};
-
-static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
- PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
- PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
- PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
-};
-
-static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
- PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
- PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
-};
-
static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
struct pinctrl_gpio_range *range,
int pin)
@@ -2516,19 +228,11 @@ static irqreturn_t airoha_irq_handler(int irq, void *data)
return handled ? IRQ_HANDLED : IRQ_NONE;
}
-static const struct irq_chip airoha_gpio_irq_chip = {
- .name = "airoha-gpio-irq",
- .irq_unmask = airoha_irq_unmask,
- .irq_mask = airoha_irq_mask,
- .irq_mask_ack = airoha_irq_mask,
- .irq_set_type = airoha_irq_type,
- .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
-};
-
static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
struct platform_device *pdev)
{
struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
+ struct irq_chip *irq_chip = &pinctrl->gpio_irq_chip;
struct gpio_chip *gc = &chip->chip;
struct gpio_irq_chip *girq = &gc->irq;
struct device *dev = &pdev->dev;
@@ -2552,9 +256,16 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
gc->base = -1;
gc->ngpio = AIROHA_NUM_PINS;
+ irq_chip->name = "airoha-gpio-irq";
+ irq_chip->irq_unmask = airoha_irq_unmask;
+ irq_chip->irq_mask = airoha_irq_mask;
+ irq_chip->irq_mask_ack = airoha_irq_mask;
+ irq_chip->irq_set_type = airoha_irq_type;
+ irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE;
+
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
- gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
+ gpio_irq_chip_set_chip(girq, irq_chip);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
@@ -2952,7 +663,7 @@ static const struct pinctrl_ops airoha_pctlops = {
.dt_free_map = pinconf_generic_dt_free_map,
};
-static int airoha_pinctrl_probe(struct platform_device *pdev)
+int airoha_pinctrl_probe(struct platform_device *pdev)
{
const struct airoha_pinctrl_match_data *data;
struct device *dev = &pdev->dev;
@@ -2961,6 +672,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
int err, i;
data = device_get_match_data(dev);
+ if (!data)
+ return -EINVAL;
pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
if (!pinctrl)
@@ -2977,8 +690,8 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
pinctrl->chip_scu = map;
/* Init pinctrl desc struct */
- pinctrl->desc.name = KBUILD_MODNAME;
- pinctrl->desc.owner = THIS_MODULE;
+ pinctrl->desc.name = data->pinctrl_name;
+ pinctrl->desc.owner = data->pinctrl_owner;
pinctrl->desc.pctlops = &airoha_pctlops;
pinctrl->desc.pmxops = &airoha_pmxops;
pinctrl->desc.confops = &airoha_confops;
@@ -3030,87 +743,10 @@ static int airoha_pinctrl_probe(struct platform_device *pdev)
/* build gpio-chip */
return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
}
-
-static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
- .pins = en7581_pinctrl_pins,
- .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
- .grps = en7581_pinctrl_groups,
- .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
- .funcs = en7581_pinctrl_funcs,
- .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
- .confs_info = {
- [AIROHA_PINCTRL_CONFS_PULLUP] = {
- .confs = en7581_pinctrl_pullup_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
- },
- [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
- .confs = en7581_pinctrl_pulldown_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
- },
- [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
- .confs = en7581_pinctrl_drive_e2_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
- },
- [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
- .confs = en7581_pinctrl_drive_e4_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
- },
- [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
- .confs = en7581_pinctrl_pcie_rst_od_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
- },
- },
-};
-
-static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
- .pins = an7583_pinctrl_pins,
- .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
- .grps = an7583_pinctrl_groups,
- .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
- .funcs = an7583_pinctrl_funcs,
- .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
- .confs_info = {
- [AIROHA_PINCTRL_CONFS_PULLUP] = {
- .confs = an7583_pinctrl_pullup_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
- },
- [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
- .confs = an7583_pinctrl_pulldown_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
- },
- [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
- .confs = an7583_pinctrl_drive_e2_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
- },
- [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
- .confs = an7583_pinctrl_drive_e4_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
- },
- [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
- .confs = an7583_pinctrl_pcie_rst_od_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
- },
- },
-};
-
-static const struct of_device_id airoha_pinctrl_of_match[] = {
- { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
- { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
-
-static struct platform_driver airoha_pinctrl_driver = {
- .probe = airoha_pinctrl_probe,
- .driver = {
- .name = "pinctrl-airoha",
- .of_match_table = airoha_pinctrl_of_match,
- },
-};
-module_platform_driver(airoha_pinctrl_driver);
+EXPORT_SYMBOL_GPL(airoha_pinctrl_probe);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
-MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");
+MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC");
diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
new file mode 100644
index 000000000000..522b35bbaa12
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
@@ -0,0 +1,1486 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ */
+
+#include "airoha-common.h"
+
+/* MUX */
+#define REG_GPIO_2ND_I2C_MODE 0x0214
+#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14)
+#define GPIO_I2C_MASTER_MODE_MODE BIT(13)
+#define GPIO_I2S_MODE_MASK BIT(12)
+#define GPIO_I2C_SLAVE_MODE_MODE BIT(11)
+#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
+#define PON_TOD_1PPS_MODE_MASK BIT(2)
+#define GSW_TOD_1PPS_MODE_MASK BIT(1)
+#define GPIO_2ND_I2C_MODE_MASK BIT(0)
+
+#define REG_GPIO_SPI_CS1_MODE 0x0218
+#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
+#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
+#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK BIT(16)
+#define GPIO_PCM2_MODE_MASK BIT(13)
+#define GPIO_PCM1_MODE_MASK BIT(12)
+#define GPIO_PCM_INT_MODE_MASK BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
+#define GPIO_SPI_CS4_MODE_MASK BIT(3)
+#define GPIO_SPI_CS3_MODE_MASK BIT(2)
+#define GPIO_SPI_CS2_MODE_MASK BIT(1)
+#define GPIO_SPI_CS1_MODE_MASK BIT(0)
+
+#define REG_GPIO_PON_MODE 0x021c
+#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
+#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
+#define GPIO_PCIE_RESET2_MASK BIT(12)
+#define SIPO_RCLK_MODE_MASK BIT(11)
+#define GPIO_PCIE_RESET1_MASK BIT(10)
+#define GPIO_PCIE_RESET0_MASK BIT(9)
+#define GPIO_UART5_MODE_MASK BIT(8)
+#define GPIO_UART4_MODE_MASK BIT(7)
+#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6)
+#define GPIO_HSUART_MODE_MASK BIT(5)
+#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4)
+#define GPIO_UART2_MODE_MASK BIT(3)
+#define GPIO_SIPO_MODE_MASK BIT(2)
+#define GPIO_EMMC_MODE_MASK BIT(1)
+#define GPIO_PON_MODE_MASK BIT(0)
+
+#define REG_NPU_UART_EN 0x0224
+#define JTAG_UDI_EN_MASK BIT(4)
+#define JTAG_DFD_EN_MASK BIT(3)
+
+#define REG_FORCE_GPIO_EN 0x0228
+#define FORCE_GPIO_EN(n) BIT(n)
+
+/* LED MAP */
+#define REG_LAN_LED0_MAPPING 0x027c
+#define REG_LAN_LED1_MAPPING 0x0280
+
+#define LAN4_LED_MAPPING_MASK GENMASK(18, 16)
+#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
+
+#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/* CONF */
+#define REG_I2C_SDA_E2 0x001c
+#define SPI_MISO_E2_MASK BIT(14)
+#define SPI_MOSI_E2_MASK BIT(13)
+#define SPI_CLK_E2_MASK BIT(12)
+#define SPI_CS0_E2_MASK BIT(11)
+#define PCIE2_RESET_E2_MASK BIT(10)
+#define PCIE1_RESET_E2_MASK BIT(9)
+#define PCIE0_RESET_E2_MASK BIT(8)
+#define UART1_RXD_E2_MASK BIT(3)
+#define UART1_TXD_E2_MASK BIT(2)
+#define I2C_SCL_E2_MASK BIT(1)
+#define I2C_SDA_E2_MASK BIT(0)
+
+#define REG_I2C_SDA_E4 0x0020
+#define SPI_MISO_E4_MASK BIT(14)
+#define SPI_MOSI_E4_MASK BIT(13)
+#define SPI_CLK_E4_MASK BIT(12)
+#define SPI_CS0_E4_MASK BIT(11)
+#define PCIE2_RESET_E4_MASK BIT(10)
+#define PCIE1_RESET_E4_MASK BIT(9)
+#define PCIE0_RESET_E4_MASK BIT(8)
+#define UART1_RXD_E4_MASK BIT(3)
+#define UART1_TXD_E4_MASK BIT(2)
+#define I2C_SCL_E4_MASK BIT(1)
+#define I2C_SDA_E4_MASK BIT(0)
+
+#define REG_GPIO_L_E2 0x0024
+#define REG_GPIO_L_E4 0x0028
+#define REG_GPIO_H_E2 0x002c
+#define REG_GPIO_H_E4 0x0030
+
+#define REG_I2C_SDA_PU 0x0044
+#define SPI_MISO_PU_MASK BIT(14)
+#define SPI_MOSI_PU_MASK BIT(13)
+#define SPI_CLK_PU_MASK BIT(12)
+#define SPI_CS0_PU_MASK BIT(11)
+#define PCIE2_RESET_PU_MASK BIT(10)
+#define PCIE1_RESET_PU_MASK BIT(9)
+#define PCIE0_RESET_PU_MASK BIT(8)
+#define UART1_RXD_PU_MASK BIT(3)
+#define UART1_TXD_PU_MASK BIT(2)
+#define I2C_SCL_PU_MASK BIT(1)
+#define I2C_SDA_PU_MASK BIT(0)
+
+#define REG_I2C_SDA_PD 0x0048
+#define SPI_MISO_PD_MASK BIT(14)
+#define SPI_MOSI_PD_MASK BIT(13)
+#define SPI_CLK_PD_MASK BIT(12)
+#define SPI_CS0_PD_MASK BIT(11)
+#define PCIE2_RESET_PD_MASK BIT(10)
+#define PCIE1_RESET_PD_MASK BIT(9)
+#define PCIE0_RESET_PD_MASK BIT(8)
+#define UART1_RXD_PD_MASK BIT(3)
+#define UART1_TXD_PD_MASK BIT(2)
+#define I2C_SCL_PD_MASK BIT(1)
+#define I2C_SDA_PD_MASK BIT(0)
+
+#define REG_GPIO_L_PU 0x004c
+#define REG_GPIO_L_PD 0x0050
+#define REG_GPIO_H_PU 0x0054
+#define REG_GPIO_H_PD 0x0058
+
+#define REG_PCIE_RESET_OD 0x018c
+#define PCIE2_RESET_OD_MASK BIT(2)
+#define PCIE1_RESET_OD_MASK BIT(1)
+#define PCIE0_RESET_OD_MASK BIT(0)
+
+/* PWM MODE CONF */
+#define REG_GPIO_FLASH_MODE_CFG 0x0034
+#define GPIO15_FLASH_MODE_CFG BIT(15)
+#define GPIO14_FLASH_MODE_CFG BIT(14)
+#define GPIO13_FLASH_MODE_CFG BIT(13)
+#define GPIO12_FLASH_MODE_CFG BIT(12)
+#define GPIO11_FLASH_MODE_CFG BIT(11)
+#define GPIO10_FLASH_MODE_CFG BIT(10)
+#define GPIO9_FLASH_MODE_CFG BIT(9)
+#define GPIO8_FLASH_MODE_CFG BIT(8)
+#define GPIO7_FLASH_MODE_CFG BIT(7)
+#define GPIO6_FLASH_MODE_CFG BIT(6)
+#define GPIO5_FLASH_MODE_CFG BIT(5)
+#define GPIO4_FLASH_MODE_CFG BIT(4)
+#define GPIO3_FLASH_MODE_CFG BIT(3)
+#define GPIO2_FLASH_MODE_CFG BIT(2)
+#define GPIO1_FLASH_MODE_CFG BIT(1)
+#define GPIO0_FLASH_MODE_CFG BIT(0)
+
+/* PWM MODE CONF EXT */
+#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
+#define GPIO51_FLASH_MODE_CFG BIT(31)
+#define GPIO50_FLASH_MODE_CFG BIT(30)
+#define GPIO49_FLASH_MODE_CFG BIT(29)
+#define GPIO48_FLASH_MODE_CFG BIT(28)
+#define GPIO47_FLASH_MODE_CFG BIT(27)
+#define GPIO46_FLASH_MODE_CFG BIT(26)
+#define GPIO45_FLASH_MODE_CFG BIT(25)
+#define GPIO44_FLASH_MODE_CFG BIT(24)
+#define GPIO43_FLASH_MODE_CFG BIT(23)
+#define GPIO42_FLASH_MODE_CFG BIT(22)
+#define GPIO41_FLASH_MODE_CFG BIT(21)
+#define GPIO40_FLASH_MODE_CFG BIT(20)
+#define GPIO39_FLASH_MODE_CFG BIT(19)
+#define GPIO38_FLASH_MODE_CFG BIT(18)
+#define GPIO37_FLASH_MODE_CFG BIT(17)
+#define GPIO36_FLASH_MODE_CFG BIT(16)
+#define GPIO31_FLASH_MODE_CFG BIT(15)
+#define GPIO30_FLASH_MODE_CFG BIT(14)
+#define GPIO29_FLASH_MODE_CFG BIT(13)
+#define GPIO28_FLASH_MODE_CFG BIT(12)
+#define GPIO27_FLASH_MODE_CFG BIT(11)
+#define GPIO26_FLASH_MODE_CFG BIT(10)
+#define GPIO25_FLASH_MODE_CFG BIT(9)
+#define GPIO24_FLASH_MODE_CFG BIT(8)
+#define GPIO23_FLASH_MODE_CFG BIT(7)
+#define GPIO22_FLASH_MODE_CFG BIT(6)
+#define GPIO21_FLASH_MODE_CFG BIT(5)
+#define GPIO20_FLASH_MODE_CFG BIT(4)
+#define GPIO19_FLASH_MODE_CFG BIT(3)
+#define GPIO18_FLASH_MODE_CFG BIT(2)
+#define GPIO17_FLASH_MODE_CFG BIT(1)
+#define GPIO16_FLASH_MODE_CFG BIT(0)
+
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ 0 \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_MUX, \
+ REG_GPIO_FLASH_MODE_CFG, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED0_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED1_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
+ PINCTRL_PIN(0, "uart1_txd"),
+ PINCTRL_PIN(1, "uart1_rxd"),
+ PINCTRL_PIN(2, "i2c_scl"),
+ PINCTRL_PIN(3, "i2c_sda"),
+ PINCTRL_PIN(4, "spi_cs0"),
+ PINCTRL_PIN(5, "spi_clk"),
+ PINCTRL_PIN(6, "spi_mosi"),
+ PINCTRL_PIN(7, "spi_miso"),
+ PINCTRL_PIN(13, "gpio0"),
+ PINCTRL_PIN(14, "gpio1"),
+ PINCTRL_PIN(15, "gpio2"),
+ PINCTRL_PIN(16, "gpio3"),
+ PINCTRL_PIN(17, "gpio4"),
+ PINCTRL_PIN(18, "gpio5"),
+ PINCTRL_PIN(19, "gpio6"),
+ PINCTRL_PIN(20, "gpio7"),
+ PINCTRL_PIN(21, "gpio8"),
+ PINCTRL_PIN(22, "gpio9"),
+ PINCTRL_PIN(23, "gpio10"),
+ PINCTRL_PIN(24, "gpio11"),
+ PINCTRL_PIN(25, "gpio12"),
+ PINCTRL_PIN(26, "gpio13"),
+ PINCTRL_PIN(27, "gpio14"),
+ PINCTRL_PIN(28, "gpio15"),
+ PINCTRL_PIN(29, "gpio16"),
+ PINCTRL_PIN(30, "gpio17"),
+ PINCTRL_PIN(31, "gpio18"),
+ PINCTRL_PIN(32, "gpio19"),
+ PINCTRL_PIN(33, "gpio20"),
+ PINCTRL_PIN(34, "gpio21"),
+ PINCTRL_PIN(35, "gpio22"),
+ PINCTRL_PIN(36, "gpio23"),
+ PINCTRL_PIN(37, "gpio24"),
+ PINCTRL_PIN(38, "gpio25"),
+ PINCTRL_PIN(39, "gpio26"),
+ PINCTRL_PIN(40, "gpio27"),
+ PINCTRL_PIN(41, "gpio28"),
+ PINCTRL_PIN(42, "gpio29"),
+ PINCTRL_PIN(43, "gpio30"),
+ PINCTRL_PIN(44, "gpio31"),
+ PINCTRL_PIN(45, "gpio32"),
+ PINCTRL_PIN(46, "gpio33"),
+ PINCTRL_PIN(47, "gpio34"),
+ PINCTRL_PIN(48, "gpio35"),
+ PINCTRL_PIN(49, "gpio36"),
+ PINCTRL_PIN(50, "gpio37"),
+ PINCTRL_PIN(51, "gpio38"),
+ PINCTRL_PIN(52, "gpio39"),
+ PINCTRL_PIN(53, "gpio40"),
+ PINCTRL_PIN(54, "gpio41"),
+ PINCTRL_PIN(55, "gpio42"),
+ PINCTRL_PIN(56, "gpio43"),
+ PINCTRL_PIN(57, "gpio44"),
+ PINCTRL_PIN(58, "gpio45"),
+ PINCTRL_PIN(59, "gpio46"),
+ PINCTRL_PIN(60, "pcie_reset0"),
+ PINCTRL_PIN(61, "pcie_reset1"),
+ PINCTRL_PIN(62, "pcie_reset2"),
+};
+
+static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+static const int en7581_pon_tod_1pps_pins[] = { 46 };
+static const int en7581_gsw_tod_1pps_pins[] = { 46 };
+static const int en7581_sipo_pins[] = { 16, 17 };
+static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
+static const int en7581_mdio_pins[] = { 14, 15 };
+static const int en7581_uart2_pins[] = { 48, 55 };
+static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
+static const int en7581_hsuart_pins[] = { 28, 29 };
+static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
+static const int en7581_uart4_pins[] = { 38, 39 };
+static const int en7581_uart5_pins[] = { 18, 19 };
+static const int en7581_i2c0_pins[] = { 2, 3 };
+static const int en7581_i2c1_pins[] = { 14, 15 };
+static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
+static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
+static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
+static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
+static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
+static const int en7581_spi_quad_pins[] = { 32, 33 };
+static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
+static const int en7581_spi_cs1_pins[] = { 34 };
+static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
+static const int en7581_pcm_spi_int_pins[] = { 14 };
+static const int en7581_pcm_spi_rst_pins[] = { 15 };
+static const int en7581_pcm_spi_cs1_pins[] = { 43 };
+static const int en7581_pcm_spi_cs2_pins[] = { 40 };
+static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
+static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
+static const int en7581_pcm_spi_cs3_pins[] = { 41 };
+static const int en7581_pcm_spi_cs4_pins[] = { 42 };
+static const int en7581_emmc_pins[] = {
+ 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
+};
+static const int en7581_pnand_pins[] = {
+ 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
+};
+static const int en7581_gpio0_pins[] = { 13 };
+static const int en7581_gpio1_pins[] = { 14 };
+static const int en7581_gpio2_pins[] = { 15 };
+static const int en7581_gpio3_pins[] = { 16 };
+static const int en7581_gpio4_pins[] = { 17 };
+static const int en7581_gpio5_pins[] = { 18 };
+static const int en7581_gpio6_pins[] = { 19 };
+static const int en7581_gpio7_pins[] = { 20 };
+static const int en7581_gpio8_pins[] = { 21 };
+static const int en7581_gpio9_pins[] = { 22 };
+static const int en7581_gpio10_pins[] = { 23 };
+static const int en7581_gpio11_pins[] = { 24 };
+static const int en7581_gpio12_pins[] = { 25 };
+static const int en7581_gpio13_pins[] = { 26 };
+static const int en7581_gpio14_pins[] = { 27 };
+static const int en7581_gpio15_pins[] = { 28 };
+static const int en7581_gpio16_pins[] = { 29 };
+static const int en7581_gpio17_pins[] = { 30 };
+static const int en7581_gpio18_pins[] = { 31 };
+static const int en7581_gpio19_pins[] = { 32 };
+static const int en7581_gpio20_pins[] = { 33 };
+static const int en7581_gpio21_pins[] = { 34 };
+static const int en7581_gpio22_pins[] = { 35 };
+static const int en7581_gpio23_pins[] = { 36 };
+static const int en7581_gpio24_pins[] = { 37 };
+static const int en7581_gpio25_pins[] = { 38 };
+static const int en7581_gpio26_pins[] = { 39 };
+static const int en7581_gpio27_pins[] = { 40 };
+static const int en7581_gpio28_pins[] = { 41 };
+static const int en7581_gpio29_pins[] = { 42 };
+static const int en7581_gpio30_pins[] = { 43 };
+static const int en7581_gpio31_pins[] = { 44 };
+static const int en7581_gpio32_pins[] = { 45 };
+static const int en7581_gpio33_pins[] = { 46 };
+static const int en7581_gpio34_pins[] = { 47 };
+static const int en7581_gpio35_pins[] = { 48 };
+static const int en7581_gpio36_pins[] = { 49 };
+static const int en7581_gpio37_pins[] = { 50 };
+static const int en7581_gpio38_pins[] = { 51 };
+static const int en7581_gpio39_pins[] = { 52 };
+static const int en7581_gpio40_pins[] = { 53 };
+static const int en7581_gpio41_pins[] = { 54 };
+static const int en7581_gpio42_pins[] = { 55 };
+static const int en7581_gpio43_pins[] = { 56 };
+static const int en7581_gpio44_pins[] = { 57 };
+static const int en7581_gpio45_pins[] = { 58 };
+static const int en7581_gpio46_pins[] = { 59 };
+static const int en7581_gpio47_pins[] = { 60 };
+static const int en7581_gpio48_pins[] = { 61 };
+static const int en7581_gpio49_pins[] = { 62 };
+static const int en7581_pcie_reset0_pins[] = { 60 };
+static const int en7581_pcie_reset1_pins[] = { 61 };
+static const int en7581_pcie_reset2_pins[] = { 62 };
+
+static const struct pingroup en7581_pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", en7581_pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", en7581_sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", en7581_mdio),
+ PINCTRL_PIN_GROUP("uart2", en7581_uart2),
+ PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
+ PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
+ PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
+ PINCTRL_PIN_GROUP("uart4", en7581_uart4),
+ PINCTRL_PIN_GROUP("uart5", en7581_uart5),
+ PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
+ PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
+ PINCTRL_PIN_GROUP("i2s", en7581_i2s),
+ PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
+ PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
+ PINCTRL_PIN_GROUP("spi", en7581_spi),
+ PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
+ PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
+ PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
+ PINCTRL_PIN_GROUP("emmc", en7581_emmc),
+ PINCTRL_PIN_GROUP("pnand", en7581_pnand),
+ PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
+ PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
+ PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
+ PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
+ PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
+ PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
+ PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
+ PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
+ PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
+ PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
+ PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
+ PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
+ PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
+ PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
+ PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
+ PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
+ PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
+ PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
+ PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
+ PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
+ PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
+ PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
+ PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
+ PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
+ PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
+ PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
+ PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
+ PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
+ PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
+ PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
+ PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
+ PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
+ PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
+ PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
+ PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
+ PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
+ PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
+ PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
+ PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
+ PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
+ PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
+ PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
+ PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
+ PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
+ PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
+ PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
+ PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
+ PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
+ PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
+ PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
+ PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
+ PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
+};
+
+static const char *const pon_groups[] = { "pon" };
+static const char *const tod_1pps_groups[] = {
+ "pon_tod_1pps", "gsw_tod_1pps"
+};
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const mdio_groups[] = { "mdio" };
+static const char *const uart_groups[] = {
+ "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
+ "uart4", "uart5"
+};
+static const char *const i2c_groups[] = { "i2c1" };
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const pcm_spi_groups[] = {
+ "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
+ "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3",
+ "pcm_spi_cs4"
+};
+static const char *const i2s_groups[] = { "i2s" };
+static const char *const emmc_groups[] = { "emmc" };
+static const char *const pnand_groups[] = { "pnand" };
+static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
+static const char *const pcie_reset_groups[] = {
+ "pcie_reset0", "pcie_reset1", "pcie_reset2"
+};
+static const char *const pwm_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+ "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47", "gpio48", "gpio49"
+};
+static const char *const phy1_led0_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy2_led0_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy3_led0_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy4_led0_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio42"
+};
+static const char *const phy1_led1_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46"
+};
+static const char *const phy2_led1_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46"
+};
+static const char *const phy3_led1_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46"
+};
+static const char *const phy4_led1_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46"
+};
+
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+ {
+ .name = "pon",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PON_MODE_MASK,
+ GPIO_PON_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+ {
+ .name = "pon_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ PON_TOD_1PPS_MODE_MASK,
+ PON_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "gsw_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GSW_TOD_1PPS_MODE_MASK,
+ GSW_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+ {
+ .name = "sipo",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "sipo_rclk",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
+ {
+ .name = "mdio",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GPIO_MDC_IO_MASTER_MODE_MASK,
+ GPIO_MDC_IO_MASTER_MODE_MASK
+ },
+ .regmap[1] = {
+ AIROHA_FUNC_MUX,
+ REG_FORCE_GPIO_EN,
+ FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
+ FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
+ },
+ .regmap_size = 2,
+ },
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+ {
+ .name = "uart2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK,
+ GPIO_UART2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart2_cts_rts",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
+ GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "hsuart",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+ GPIO_HSUART_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+ {
+ .name = "hsuart_cts_rts",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART4_MODE_MASK,
+ GPIO_UART4_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart5",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART5_MODE_MASK,
+ GPIO_UART5_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group i2c_func_group[] = {
+ {
+ .name = "i2c1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GPIO_2ND_I2C_MODE_MASK,
+ GPIO_2ND_I2C_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+ {
+ .name = "jtag_udi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_UDI_EN_MASK,
+ JTAG_UDI_EN_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "jtag_dfd",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_DFD_EN_MASK,
+ JTAG_DFD_EN_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+ {
+ .name = "pcm1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM1_MODE_MASK,
+ GPIO_PCM1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM2_MODE_MASK,
+ GPIO_PCM2_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+ {
+ .name = "spi_quad",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_QUAD_MODE_MASK,
+ GPIO_SPI_QUAD_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS1_MODE_MASK,
+ GPIO_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS2_MODE_MASK,
+ GPIO_SPI_CS2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS3_MODE_MASK,
+ GPIO_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS4_MODE_MASK,
+ GPIO_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
+ {
+ .name = "pcm_spi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_MODE_MASK,
+ GPIO_PCM_SPI_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_int",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_INT_MODE_MASK,
+ GPIO_PCM_INT_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_rst",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_RESET_MODE_MASK,
+ GPIO_PCM_RESET_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS1_MODE_MASK,
+ GPIO_PCM_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs2_p128",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS2_MODE_P128_MASK,
+ GPIO_PCM_SPI_CS2_MODE_P128_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs2_p156",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS2_MODE_P156_MASK,
+ GPIO_PCM_SPI_CS2_MODE_P156_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS3_MODE_MASK,
+ GPIO_PCM_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS4_MODE_MASK,
+ GPIO_PCM_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group i2s_func_group[] = {
+ {
+ .name = "i2s",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GPIO_I2S_MODE_MASK,
+ GPIO_I2S_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group emmc_func_group[] = {
+ {
+ .name = "emmc",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_EMMC_MODE_MASK,
+ GPIO_EMMC_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pnand_func_group[] = {
+ {
+ .name = "pnand",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PARALLEL_NAND_MODE_MASK,
+ GPIO_PARALLEL_NAND_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+ AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET2_MASK),
+};
+
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+ {
+ .name = "pcie_reset0",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET0_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcie_reset1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET1_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcie_reset2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET2_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+ AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET2_MASK),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
+ PINCTRL_FUNC_DESC("pon", pon),
+ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+ PINCTRL_FUNC_DESC("sipo", sipo),
+ PINCTRL_FUNC_DESC("mdio", mdio),
+ PINCTRL_FUNC_DESC("uart", uart),
+ PINCTRL_FUNC_DESC("i2c", i2c),
+ PINCTRL_FUNC_DESC("jtag", jtag),
+ PINCTRL_FUNC_DESC("pcm", pcm),
+ PINCTRL_FUNC_DESC("spi", spi),
+ PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
+ PINCTRL_FUNC_DESC("i2s", i2s),
+ PINCTRL_FUNC_DESC("emmc", emmc),
+ PINCTRL_FUNC_DESC("pnand", pnand),
+ PINCTRL_FUNC_DESC("gpio", gpio),
+ PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+ PINCTRL_FUNC_DESC("pwm", pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+ PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+ PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+ PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
+ PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
+ PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
+ PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
+ PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
+ PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
+ PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
+ PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
+ PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
+ PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
+ PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
+ PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
+ PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
+ PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
+ PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
+ PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
+ PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
+ PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
+ PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
+ PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+ PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+ PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
+ PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
+ PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
+ PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
+ PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
+ PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
+ PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
+ PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
+ PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
+ PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
+ PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
+ PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
+ PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
+ PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
+ PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
+ PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
+ PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
+ PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
+ PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
+ PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+ PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+ PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
+ PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
+ PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
+ PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
+ PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
+ PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
+ PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
+ PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
+ PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
+ PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
+ PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
+ PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
+ PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
+ PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
+ PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
+ PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
+ PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
+ PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
+ PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
+ PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+ PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+ PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+ PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+ PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+ PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+ PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+ PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+ PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+ PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
+ PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
+ PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
+ PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
+ PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
+ PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
+ PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
+ PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
+ PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
+ PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
+ PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
+ PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
+ PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
+ PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
+ PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
+ PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
+ PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
+ PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
+ PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
+ PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+ PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+ PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
+};
+
+static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
+ PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
+};
+
+static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
+ .pinctrl_name = KBUILD_MODNAME,
+ .pinctrl_owner = THIS_MODULE,
+ .pins = en7581_pinctrl_pins,
+ .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
+ .grps = en7581_pinctrl_groups,
+ .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
+ .funcs = en7581_pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
+ .confs_info = {
+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
+ .confs = en7581_pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+ .confs = en7581_pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+ .confs = en7581_pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+ .confs = en7581_pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+ .confs = en7581_pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
+ },
+ },
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+ { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+ .probe = airoha_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-airoha-an7581",
+ .of_match_table = airoha_pinctrl_of_match,
+ },
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC");
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
new file mode 100644
index 000000000000..b9d8dd94de5f
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -0,0 +1,1456 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ */
+
+#include "airoha-common.h"
+
+/* MUX */
+#define REG_GPIO_2ND_I2C_MODE 0x0214
+#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
+#define PON_TOD_1PPS_MODE_MASK BIT(2)
+#define GSW_TOD_1PPS_MODE_MASK BIT(1)
+
+#define REG_GPIO_SPI_CS1_MODE 0x0218
+#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(22)
+#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
+#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK BIT(16)
+#define GPIO_PCM2_MODE_MASK BIT(13)
+#define GPIO_PCM1_MODE_MASK BIT(12)
+#define GPIO_PCM_INT_MODE_MASK BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
+#define GPIO_SPI_CS4_MODE_MASK BIT(3)
+#define GPIO_SPI_CS3_MODE_MASK BIT(2)
+#define GPIO_SPI_CS2_MODE_MASK BIT(1)
+#define GPIO_SPI_CS1_MODE_MASK BIT(0)
+
+#define REG_GPIO_PON_MODE 0x021c
+#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26)
+#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25)
+#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24)
+#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23)
+#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22)
+#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21)
+#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20)
+#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19)
+#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18)
+#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17)
+#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16)
+#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15)
+#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
+#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
+#define SIPO_RCLK_MODE_MASK BIT(11)
+#define GPIO_PCIE_RESET1_MASK BIT(10)
+#define GPIO_PCIE_RESET0_MASK BIT(9)
+#define GPIO_UART5_MODE_MASK BIT(8)
+#define GPIO_UART4_MODE_MASK BIT(7)
+#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6)
+#define GPIO_HSUART_MODE_MASK BIT(5)
+#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4)
+#define GPIO_UART2_MODE_MASK BIT(3)
+#define GPIO_SIPO_MODE_MASK BIT(2)
+#define GPIO_EMMC_MODE_MASK BIT(1)
+#define GPIO_PON_MODE_MASK BIT(0)
+
+#define REG_NPU_UART_EN 0x0224
+#define JTAG_UDI_EN_MASK BIT(4)
+#define JTAG_DFD_EN_MASK BIT(3)
+
+#define REG_FORCE_GPIO_EN 0x0228
+#define FORCE_GPIO_EN(n) BIT(n)
+
+/* LED MAP */
+#define REG_LAN_LED0_MAPPING 0x027c
+#define REG_LAN_LED1_MAPPING 0x0280
+
+#define LAN4_LED_MAPPING_MASK GENMASK(18, 16)
+#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
+
+#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/* CONF */
+#define REG_I2C_SDA_E2 0x001c
+#define AN7583_I2C1_SCL_E2_MASK BIT(16)
+#define AN7583_I2C1_SDA_E2_MASK BIT(15)
+#define SPI_MISO_E2_MASK BIT(14)
+#define SPI_MOSI_E2_MASK BIT(13)
+#define SPI_CLK_E2_MASK BIT(12)
+#define SPI_CS0_E2_MASK BIT(11)
+#define PCIE1_RESET_E2_MASK BIT(9)
+#define PCIE0_RESET_E2_MASK BIT(8)
+#define AN7583_MDIO_0_E2_MASK BIT(5)
+#define AN7583_MDC_0_E2_MASK BIT(4)
+#define UART1_RXD_E2_MASK BIT(3)
+#define UART1_TXD_E2_MASK BIT(2)
+#define I2C_SCL_E2_MASK BIT(1)
+#define I2C_SDA_E2_MASK BIT(0)
+
+#define REG_I2C_SDA_E4 0x0020
+#define AN7583_I2C1_SCL_E4_MASK BIT(16)
+#define AN7583_I2C1_SDA_E4_MASK BIT(15)
+#define SPI_MISO_E4_MASK BIT(14)
+#define SPI_MOSI_E4_MASK BIT(13)
+#define SPI_CLK_E4_MASK BIT(12)
+#define SPI_CS0_E4_MASK BIT(11)
+#define PCIE1_RESET_E4_MASK BIT(9)
+#define PCIE0_RESET_E4_MASK BIT(8)
+#define AN7583_MDIO_0_E4_MASK BIT(5)
+#define AN7583_MDC_0_E4_MASK BIT(4)
+#define UART1_RXD_E4_MASK BIT(3)
+#define UART1_TXD_E4_MASK BIT(2)
+#define I2C_SCL_E4_MASK BIT(1)
+#define I2C_SDA_E4_MASK BIT(0)
+
+#define REG_GPIO_L_E2 0x0024
+#define REG_GPIO_L_E4 0x0028
+#define REG_GPIO_H_E2 0x002c
+#define REG_GPIO_H_E4 0x0030
+
+#define REG_I2C_SDA_PU 0x0044
+#define AN7583_I2C1_SCL_PU_MASK BIT(16)
+#define AN7583_I2C1_SDA_PU_MASK BIT(15)
+#define SPI_MISO_PU_MASK BIT(14)
+#define SPI_MOSI_PU_MASK BIT(13)
+#define SPI_CLK_PU_MASK BIT(12)
+#define SPI_CS0_PU_MASK BIT(11)
+#define PCIE1_RESET_PU_MASK BIT(9)
+#define PCIE0_RESET_PU_MASK BIT(8)
+#define AN7583_MDIO_0_PU_MASK BIT(5)
+#define AN7583_MDC_0_PU_MASK BIT(4)
+#define UART1_RXD_PU_MASK BIT(3)
+#define UART1_TXD_PU_MASK BIT(2)
+#define I2C_SCL_PU_MASK BIT(1)
+#define I2C_SDA_PU_MASK BIT(0)
+
+#define REG_I2C_SDA_PD 0x0048
+#define AN7583_I2C1_SCL_PD_MASK BIT(16)
+#define AN7583_I2C1_SDA_PD_MASK BIT(15)
+#define SPI_MISO_PD_MASK BIT(14)
+#define SPI_MOSI_PD_MASK BIT(13)
+#define SPI_CLK_PD_MASK BIT(12)
+#define SPI_CS0_PD_MASK BIT(11)
+#define PCIE1_RESET_PD_MASK BIT(9)
+#define PCIE0_RESET_PD_MASK BIT(8)
+#define AN7583_MDIO_0_PD_MASK BIT(5)
+#define AN7583_MDC_0_PD_MASK BIT(4)
+#define UART1_RXD_PD_MASK BIT(3)
+#define UART1_TXD_PD_MASK BIT(2)
+#define I2C_SCL_PD_MASK BIT(1)
+#define I2C_SDA_PD_MASK BIT(0)
+
+#define REG_GPIO_L_PU 0x004c
+#define REG_GPIO_L_PD 0x0050
+#define REG_GPIO_H_PU 0x0054
+#define REG_GPIO_H_PD 0x0058
+
+#define REG_PCIE_RESET_OD 0x018c
+#define PCIE1_RESET_OD_MASK BIT(1)
+#define PCIE0_RESET_OD_MASK BIT(0)
+
+/* PWM MODE CONF */
+#define REG_GPIO_FLASH_MODE_CFG 0x0034
+#define GPIO15_FLASH_MODE_CFG BIT(15)
+#define GPIO14_FLASH_MODE_CFG BIT(14)
+#define GPIO13_FLASH_MODE_CFG BIT(13)
+#define GPIO12_FLASH_MODE_CFG BIT(12)
+#define GPIO11_FLASH_MODE_CFG BIT(11)
+#define GPIO10_FLASH_MODE_CFG BIT(10)
+#define GPIO9_FLASH_MODE_CFG BIT(9)
+#define GPIO8_FLASH_MODE_CFG BIT(8)
+#define GPIO7_FLASH_MODE_CFG BIT(7)
+#define GPIO6_FLASH_MODE_CFG BIT(6)
+#define GPIO5_FLASH_MODE_CFG BIT(5)
+#define GPIO4_FLASH_MODE_CFG BIT(4)
+#define GPIO3_FLASH_MODE_CFG BIT(3)
+#define GPIO2_FLASH_MODE_CFG BIT(2)
+#define GPIO1_FLASH_MODE_CFG BIT(1)
+#define GPIO0_FLASH_MODE_CFG BIT(0)
+
+/* PWM MODE CONF EXT */
+#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
+#define GPIO51_FLASH_MODE_CFG BIT(31)
+#define GPIO50_FLASH_MODE_CFG BIT(30)
+#define GPIO49_FLASH_MODE_CFG BIT(29)
+#define GPIO48_FLASH_MODE_CFG BIT(28)
+#define GPIO47_FLASH_MODE_CFG BIT(27)
+#define GPIO46_FLASH_MODE_CFG BIT(26)
+#define GPIO45_FLASH_MODE_CFG BIT(25)
+#define GPIO44_FLASH_MODE_CFG BIT(24)
+#define GPIO43_FLASH_MODE_CFG BIT(23)
+#define GPIO42_FLASH_MODE_CFG BIT(22)
+#define GPIO41_FLASH_MODE_CFG BIT(21)
+#define GPIO40_FLASH_MODE_CFG BIT(20)
+#define GPIO39_FLASH_MODE_CFG BIT(19)
+#define GPIO38_FLASH_MODE_CFG BIT(18)
+#define GPIO37_FLASH_MODE_CFG BIT(17)
+#define GPIO36_FLASH_MODE_CFG BIT(16)
+#define GPIO31_FLASH_MODE_CFG BIT(15)
+#define GPIO30_FLASH_MODE_CFG BIT(14)
+#define GPIO29_FLASH_MODE_CFG BIT(13)
+#define GPIO28_FLASH_MODE_CFG BIT(12)
+#define GPIO27_FLASH_MODE_CFG BIT(11)
+#define GPIO26_FLASH_MODE_CFG BIT(10)
+#define GPIO25_FLASH_MODE_CFG BIT(9)
+#define GPIO24_FLASH_MODE_CFG BIT(8)
+#define GPIO23_FLASH_MODE_CFG BIT(7)
+#define GPIO22_FLASH_MODE_CFG BIT(6)
+#define GPIO21_FLASH_MODE_CFG BIT(5)
+#define GPIO20_FLASH_MODE_CFG BIT(4)
+#define GPIO19_FLASH_MODE_CFG BIT(3)
+#define GPIO18_FLASH_MODE_CFG BIT(2)
+#define GPIO17_FLASH_MODE_CFG BIT(1)
+#define GPIO16_FLASH_MODE_CFG BIT(0)
+
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ 0 \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_MUX, \
+ REG_GPIO_FLASH_MODE_CFG, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED0_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED1_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
+ PINCTRL_PIN(2, "gpio0"),
+ PINCTRL_PIN(3, "gpio1"),
+ PINCTRL_PIN(4, "gpio2"),
+ PINCTRL_PIN(5, "gpio3"),
+ PINCTRL_PIN(6, "gpio4"),
+ PINCTRL_PIN(7, "gpio5"),
+ PINCTRL_PIN(8, "gpio6"),
+ PINCTRL_PIN(9, "gpio7"),
+ PINCTRL_PIN(10, "gpio8"),
+ PINCTRL_PIN(11, "gpio9"),
+ PINCTRL_PIN(12, "gpio10"),
+ PINCTRL_PIN(13, "gpio11"),
+ PINCTRL_PIN(14, "gpio12"),
+ PINCTRL_PIN(15, "gpio13"),
+ PINCTRL_PIN(16, "gpio14"),
+ PINCTRL_PIN(17, "gpio15"),
+ PINCTRL_PIN(18, "gpio16"),
+ PINCTRL_PIN(19, "gpio17"),
+ PINCTRL_PIN(20, "gpio18"),
+ PINCTRL_PIN(21, "gpio19"),
+ PINCTRL_PIN(22, "gpio20"),
+ PINCTRL_PIN(23, "gpio21"),
+ PINCTRL_PIN(24, "gpio22"),
+ PINCTRL_PIN(25, "gpio23"),
+ PINCTRL_PIN(26, "gpio24"),
+ PINCTRL_PIN(27, "gpio25"),
+ PINCTRL_PIN(28, "gpio26"),
+ PINCTRL_PIN(29, "gpio27"),
+ PINCTRL_PIN(30, "gpio28"),
+ PINCTRL_PIN(31, "gpio29"),
+ PINCTRL_PIN(32, "gpio30"),
+ PINCTRL_PIN(33, "gpio31"),
+ PINCTRL_PIN(34, "gpio32"),
+ PINCTRL_PIN(35, "gpio33"),
+ PINCTRL_PIN(36, "gpio34"),
+ PINCTRL_PIN(37, "gpio35"),
+ PINCTRL_PIN(38, "gpio36"),
+ PINCTRL_PIN(39, "gpio37"),
+ PINCTRL_PIN(40, "gpio38"),
+ PINCTRL_PIN(41, "i2c0_scl"),
+ PINCTRL_PIN(42, "i2c0_sda"),
+ PINCTRL_PIN(43, "i2c1_scl"),
+ PINCTRL_PIN(44, "i2c1_sda"),
+ PINCTRL_PIN(45, "spi_clk"),
+ PINCTRL_PIN(46, "spi_cs"),
+ PINCTRL_PIN(47, "spi_mosi"),
+ PINCTRL_PIN(48, "spi_miso"),
+ PINCTRL_PIN(49, "uart_txd"),
+ PINCTRL_PIN(50, "uart_rxd"),
+ PINCTRL_PIN(51, "pcie_reset0"),
+ PINCTRL_PIN(52, "pcie_reset1"),
+ PINCTRL_PIN(53, "mdc_0"),
+ PINCTRL_PIN(54, "mdio_0"),
+};
+
+static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+static const int an7583_pon_tod_1pps_pins[] = { 32 };
+static const int an7583_gsw_tod_1pps_pins[] = { 32 };
+static const int an7583_sipo_pins[] = { 34, 35 };
+static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
+static const int an7583_mdio_pins[] = { 43, 44 };
+static const int an7583_uart2_pins[] = { 34, 35 };
+static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
+static const int an7583_hsuart_pins[] = { 30, 31 };
+static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
+static const int an7583_npu_uart_pins[] = { 7, 8 };
+static const int an7583_uart4_pins[] = { 7, 8 };
+static const int an7583_uart5_pins[] = { 23, 24 };
+static const int an7583_i2c0_pins[] = { 41, 42 };
+static const int an7583_i2c1_pins[] = { 43, 44 };
+static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
+static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
+static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
+static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
+static const int an7583_spi_quad_pins[] = { 25, 26 };
+static const int an7583_spi_cs1_pins[] = { 27 };
+static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
+static const int an7583_pcm_spi_rst_pins[] = { 14 };
+static const int an7583_pcm_spi_cs1_pins[] = { 24 };
+static const int an7583_emmc_pins[] = {
+ 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
+};
+static const int an7583_pnand_pins[] = {
+ 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
+};
+static const int an7583_gpio0_pins[] = { 2 };
+static const int an7583_gpio1_pins[] = { 3 };
+static const int an7583_gpio2_pins[] = { 4 };
+static const int an7583_gpio3_pins[] = { 5 };
+static const int an7583_gpio4_pins[] = { 6 };
+static const int an7583_gpio5_pins[] = { 7 };
+static const int an7583_gpio6_pins[] = { 8 };
+static const int an7583_gpio7_pins[] = { 9 };
+static const int an7583_gpio8_pins[] = { 10 };
+static const int an7583_gpio9_pins[] = { 11 };
+static const int an7583_gpio10_pins[] = { 12 };
+static const int an7583_gpio11_pins[] = { 13 };
+static const int an7583_gpio12_pins[] = { 14 };
+static const int an7583_gpio13_pins[] = { 15 };
+static const int an7583_gpio14_pins[] = { 16 };
+static const int an7583_gpio15_pins[] = { 17 };
+static const int an7583_gpio16_pins[] = { 18 };
+static const int an7583_gpio17_pins[] = { 19 };
+static const int an7583_gpio18_pins[] = { 20 };
+static const int an7583_gpio19_pins[] = { 21 };
+static const int an7583_gpio20_pins[] = { 22 };
+static const int an7583_gpio21_pins[] = { 23 };
+static const int an7583_gpio22_pins[] = { 24 };
+static const int an7583_gpio23_pins[] = { 25 };
+static const int an7583_gpio24_pins[] = { 26 };
+static const int an7583_gpio25_pins[] = { 27 };
+static const int an7583_gpio26_pins[] = { 28 };
+static const int an7583_gpio27_pins[] = { 29 };
+static const int an7583_gpio28_pins[] = { 30 };
+static const int an7583_gpio29_pins[] = { 31 };
+static const int an7583_gpio30_pins[] = { 32 };
+static const int an7583_gpio31_pins[] = { 33 };
+static const int an7583_gpio32_pins[] = { 34 };
+static const int an7583_gpio33_pins[] = { 35 };
+static const int an7583_gpio34_pins[] = { 36 };
+static const int an7583_gpio35_pins[] = { 37 };
+static const int an7583_gpio36_pins[] = { 38 };
+static const int an7583_gpio37_pins[] = { 39 };
+static const int an7583_gpio38_pins[] = { 40 };
+static const int an7583_gpio39_pins[] = { 41 };
+static const int an7583_gpio40_pins[] = { 42 };
+static const int an7583_gpio41_pins[] = { 43 };
+static const int an7583_gpio42_pins[] = { 44 };
+static const int an7583_gpio43_pins[] = { 45 };
+static const int an7583_gpio44_pins[] = { 46 };
+static const int an7583_gpio45_pins[] = { 47 };
+static const int an7583_gpio46_pins[] = { 48 };
+static const int an7583_gpio47_pins[] = { 49 };
+static const int an7583_gpio48_pins[] = { 50 };
+static const int an7583_gpio49_pins[] = { 51 };
+static const int an7583_gpio50_pins[] = { 52 };
+static const int an7583_gpio51_pins[] = { 53 };
+static const int an7583_gpio52_pins[] = { 54 };
+static const int an7583_pcie_reset0_pins[] = { 51 };
+static const int an7583_pcie_reset1_pins[] = { 52 };
+
+static const struct pingroup an7583_pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", an7583_pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", an7583_sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", an7583_mdio),
+ PINCTRL_PIN_GROUP("uart2", an7583_uart2),
+ PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
+ PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
+ PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
+ PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
+ PINCTRL_PIN_GROUP("uart4", an7583_uart4),
+ PINCTRL_PIN_GROUP("uart5", an7583_uart5),
+ PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
+ PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
+ PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
+ PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
+ PINCTRL_PIN_GROUP("spi", an7583_spi),
+ PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("emmc", an7583_emmc),
+ PINCTRL_PIN_GROUP("pnand", an7583_pnand),
+ PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
+ PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
+ PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
+ PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
+ PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
+ PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
+ PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
+ PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
+ PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
+ PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
+ PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
+ PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
+ PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
+ PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
+ PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
+ PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
+ PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
+ PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
+ PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
+ PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
+ PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
+ PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
+ PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
+ PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
+ PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
+ PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
+ PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
+ PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
+ PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
+ PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
+ PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
+ PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
+ PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
+ PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
+ PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
+ PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
+ PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
+ PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
+ PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
+ PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
+ PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
+ PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
+ PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
+ PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
+ PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
+ PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
+ PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
+ PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
+ PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
+ PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
+ PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
+ PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
+ PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
+ PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
+};
+
+static const char *const pon_groups[] = { "pon" };
+static const char *const tod_1pps_groups[] = {
+ "pon_tod_1pps", "gsw_tod_1pps"
+};
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const an7583_mdio_groups[] = { "mdio" };
+static const char *const uart_groups[] = {
+ "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
+ "uart4", "uart5"
+};
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const an7583_pcm_spi_groups[] = {
+ "pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
+};
+static const char *const emmc_groups[] = { "emmc" };
+static const char *const pnand_groups[] = { "pnand" };
+static const char *const an7583_gpio_groups[] = {
+ "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
+ "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
+ "gpio49", "gpio50", "gpio51", "gpio52"
+};
+static const char *const an7583_pcie_reset_groups[] = {
+ "pcie_reset0", "pcie_reset1"
+};
+static const char *const an7583_pwm_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+ "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
+};
+static const char *const an7583_phy1_led0_groups[] = {
+ "gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy2_led0_groups[] = {
+ "gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy3_led0_groups[] = {
+ "gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy4_led0_groups[] = {
+ "gpio1", "gpio2", "gpio3", "gpio4"
+};
+static const char *const an7583_phy1_led1_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const an7583_phy2_led1_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const an7583_phy3_led1_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const an7583_phy4_led1_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+ {
+ .name = "pon",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PON_MODE_MASK,
+ GPIO_PON_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+ {
+ .name = "pon_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ PON_TOD_1PPS_MODE_MASK,
+ PON_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "gsw_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GSW_TOD_1PPS_MODE_MASK,
+ GSW_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+ {
+ .name = "sipo",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "sipo_rclk",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
+ {
+ .name = "mdio",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SGMII_MDIO_MODE_MASK,
+ GPIO_SGMII_MDIO_MODE_MASK
+ },
+ .regmap[1] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_MDC_IO_MASTER_MODE_MASK,
+ GPIO_MDC_IO_MASTER_MODE_MASK
+ },
+ .regmap_size = 2,
+ },
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+ {
+ .name = "uart2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK,
+ GPIO_UART2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart2_cts_rts",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
+ GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "hsuart",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+ GPIO_HSUART_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+ {
+ .name = "hsuart_cts_rts",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART4_MODE_MASK,
+ GPIO_UART4_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "uart5",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART5_MODE_MASK,
+ GPIO_UART5_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+ {
+ .name = "jtag_udi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_UDI_EN_MASK,
+ JTAG_UDI_EN_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "jtag_dfd",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_DFD_EN_MASK,
+ JTAG_DFD_EN_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+ {
+ .name = "pcm1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM1_MODE_MASK,
+ GPIO_PCM1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM2_MODE_MASK,
+ GPIO_PCM2_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+ {
+ .name = "spi_quad",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_QUAD_MODE_MASK,
+ GPIO_SPI_QUAD_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS1_MODE_MASK,
+ GPIO_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS2_MODE_MASK,
+ GPIO_SPI_CS2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS3_MODE_MASK,
+ GPIO_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS4_MODE_MASK,
+ GPIO_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
+ {
+ .name = "pcm_spi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_MODE_MASK,
+ GPIO_PCM_SPI_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_int",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_INT_MODE_MASK,
+ GPIO_PCM_INT_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_rst",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_RESET_MODE_MASK,
+ GPIO_PCM_RESET_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS1_MODE_MASK,
+ GPIO_PCM_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
+ AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS3_MODE_MASK,
+ GPIO_PCM_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS4_MODE_MASK,
+ GPIO_PCM_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group emmc_func_group[] = {
+ {
+ .name = "emmc",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_EMMC_MODE_MASK,
+ GPIO_EMMC_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pnand_func_group[] = {
+ {
+ .name = "pnand",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PARALLEL_NAND_MODE_MASK,
+ GPIO_PARALLEL_NAND_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
+ AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
+ AN7583_I2C0_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
+ AN7583_I2C0_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
+ AN7583_I2C1_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
+ AN7583_I2C1_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
+ AN7583_SPI_CLK_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
+ AN7583_SPI_CS_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
+ AN7583_SPI_MOSI_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
+ AN7583_SPI_MISO_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+ AN7583_UART_TXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
+ AN7583_UART_RXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
+ AN7583_MDC_0_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
+};
+
+static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
+ {
+ .name = "pcie_reset0",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET0_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcie_reset1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET1_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
+ AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
+ AN7583_I2C0_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
+ AN7583_I2C0_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
+ AN7583_I2C1_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
+ AN7583_I2C1_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
+ AN7583_SPI_CLK_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
+ AN7583_SPI_CS_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
+ AN7583_SPI_MOSI_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
+ AN7583_SPI_MISO_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
+ AN7583_UART_TXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
+ AN7583_UART_RXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
+ AN7583_MDC_0_GPIO_MODE_MASK),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
+ PINCTRL_FUNC_DESC("pon", pon),
+ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+ PINCTRL_FUNC_DESC("sipo", sipo),
+ PINCTRL_FUNC_DESC("mdio", an7583_mdio),
+ PINCTRL_FUNC_DESC("uart", uart),
+ PINCTRL_FUNC_DESC("jtag", jtag),
+ PINCTRL_FUNC_DESC("pcm", pcm),
+ PINCTRL_FUNC_DESC("spi", spi),
+ PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
+ PINCTRL_FUNC_DESC("emmc", emmc),
+ PINCTRL_FUNC_DESC("pnand", pnand),
+ PINCTRL_FUNC_DESC("gpio", an7583_gpio),
+ PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
+ PINCTRL_FUNC_DESC("pwm", an7583_pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
+ PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
+ PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
+ PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
+ PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+ PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
+ PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+ PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+ PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+ PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
+ PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+ PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+ PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+ PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
+};
+
+static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
+ PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+};
+
+static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
+ .pinctrl_name = KBUILD_MODNAME,
+ .pinctrl_owner = THIS_MODULE,
+ .pins = an7583_pinctrl_pins,
+ .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
+ .grps = an7583_pinctrl_groups,
+ .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
+ .funcs = an7583_pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
+ .confs_info = {
+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
+ .confs = an7583_pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+ .confs = an7583_pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+ .confs = an7583_pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+ .confs = an7583_pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+ .confs = an7583_pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
+ },
+ },
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+ { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+ .probe = airoha_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-airoha-an7583",
+ .of_match_table = airoha_pinctrl_of_match,
+ },
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC");
--
2.53.0
^ permalink raw reply related
* [PATCH v6 17/17] pinctrl: airoha: add support of an7563 SoC
From: Mikhail Kshevetskiy @ 2026-06-28 14:37 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260628143733.273651-1-mikhail.kshevetskiy@iopsys.eu>
This patch adds support of Airoha an7563 SoC pin controller.
Also it adds corresponding device tree binding schema.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
.../pinctrl/airoha,an7563-pinctrl.yaml | 348 +++++
drivers/pinctrl/airoha/Kconfig | 6 +
drivers/pinctrl/airoha/Makefile | 1 +
drivers/pinctrl/airoha/pinctrl-an7563.c | 1115 +++++++++++++++++
4 files changed, 1470 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml
create mode 100644 drivers/pinctrl/airoha/pinctrl-an7563.c
diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml
new file mode 100644
index 000000000000..e626d3466128
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml
@@ -0,0 +1,348 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/airoha,an7563-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN7563 Pin Controller
+
+maintainers:
+ - Lorenzo Bianconi <lorenzo@kernel.org>
+
+description:
+ The Airoha's AN7563 Pin controller is used to control SoC pins.
+
+properties:
+ compatible:
+ const: airoha,an7563-pinctrl
+
+ interrupts:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+ - interrupts
+ - gpio-controller
+ - "#gpio-cells"
+ - interrupt-controller
+ - "#interrupt-cells"
+
+patternProperties:
+ '-pins$':
+ type: object
+
+ patternProperties:
+ '^mux(-|$)':
+ type: object
+
+ description:
+ pinmux configuration nodes.
+
+ $ref: /schemas/pinctrl/pinmux-node.yaml
+
+ properties:
+ function:
+ description:
+ A string containing the name of the function to mux to the group.
+ enum: [pon, sipo, mdio, uart, jtag, pcm, spi, pnand, gpio,
+ pcie_reset, pwm, phy1_led0, phy2_led0, phy3_led0,
+ phy4_led0, phy1_led1, phy2_led1, phy3_led1, phy4_led1]
+
+ groups:
+ description:
+ An array of strings. Each string contains the name of a group.
+
+ required:
+ - function
+ - groups
+
+ allOf:
+ - if:
+ properties:
+ function:
+ const: pon
+ then:
+ properties:
+ groups:
+ enum: [pon]
+ - if:
+ properties:
+ function:
+ const: sipo
+ then:
+ properties:
+ groups:
+ enum: [sipo, sipo_rclk]
+ - if:
+ properties:
+ function:
+ const: mdio
+ then:
+ properties:
+ groups:
+ enum: [mdio]
+ - if:
+ properties:
+ function:
+ const: uart
+ then:
+ properties:
+ groups:
+ items:
+ enum: [hsuart, hsuart_cts_rts]
+ maxItems: 2
+ - if:
+ properties:
+ function:
+ const: jtag
+ then:
+ properties:
+ groups:
+ enum: [jtag_udi, jtag_dfd]
+ - if:
+ properties:
+ function:
+ const: pcm
+ then:
+ properties:
+ groups:
+ enum: [pcm1, pcm2]
+ - if:
+ properties:
+ function:
+ const: spi
+ then:
+ properties:
+ groups:
+ items:
+ enum: [spi_quad, spi_cs1]
+ maxItems: 2
+ - if:
+ properties:
+ function:
+ const: pnand
+ then:
+ properties:
+ groups:
+ enum: [pnand]
+ - if:
+ properties:
+ function:
+ const: gpio
+ then:
+ properties:
+ groups:
+ enum: [gpio28, gpio29, gpio30, gpio31, gpio32,
+ gpio33, gpio34, gpio35, gpio36, gpio37]
+ - if:
+ properties:
+ function:
+ const: pcie_reset
+ then:
+ properties:
+ groups:
+ enum: [pcie_reset0, pcie_reset1]
+ - if:
+ properties:
+ function:
+ const: pwm
+ then:
+ properties:
+ groups:
+ enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6,
+ gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13,
+ gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+ gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
+ gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
+ gpio36, gpio37]
+ - if:
+ properties:
+ function:
+ const: phy1_led0
+ then:
+ properties:
+ groups:
+ enum: [gpio8, gpio9, gpio10, gpio11]
+ - if:
+ properties:
+ function:
+ const: phy2_led0
+ then:
+ properties:
+ groups:
+ enum: [gpio8, gpio9, gpio10, gpio11]
+ - if:
+ properties:
+ function:
+ const: phy3_led0
+ then:
+ properties:
+ groups:
+ enum: [gpio8, gpio9, gpio10, gpio11]
+ - if:
+ properties:
+ function:
+ const: phy4_led0
+ then:
+ properties:
+ groups:
+ enum: [gpio8, gpio9, gpio10, gpio11]
+ - if:
+ properties:
+ function:
+ const: phy1_led1
+ then:
+ properties:
+ groups:
+ enum: [gpio4, gpio5, gpio6, gpio7]
+ - if:
+ properties:
+ function:
+ const: phy2_led1
+ then:
+ properties:
+ groups:
+ enum: [gpio4, gpio5, gpio6, gpio7]
+ - if:
+ properties:
+ function:
+ const: phy3_led1
+ then:
+ properties:
+ groups:
+ enum: [gpio4, gpio5, gpio6, gpio7]
+ - if:
+ properties:
+ function:
+ const: phy4_led1
+ then:
+ properties:
+ groups:
+ enum: [gpio4, gpio5, gpio6, gpio7]
+
+ additionalProperties: false
+
+ '^conf(-|$)':
+ type: object
+
+ description:
+ pinconf configuration nodes.
+
+ $ref: /schemas/pinctrl/pincfg-node.yaml
+
+ properties:
+ pins:
+ description:
+ An array of strings. Each string contains the name of a pin.
+ items:
+ enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
+ gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
+ gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21,
+ gpio22, gpio23, gpio24, gpio25, gpio26, gpio27,
+ pcie_reset0, pcie_reset1, i2c_scl, i2c_sda, spi_clk,
+ spi_cs, spi_mosi, spi_miso, uart_txd, uart_rxd]
+ minItems: 1
+ maxItems: 38
+
+ bias-disable: true
+
+ bias-pull-up: true
+
+ bias-pull-down: true
+
+ input-enable: true
+
+ output-enable: true
+
+ output-low: true
+
+ output-high: true
+
+ drive-open-drain: true
+
+ drive-strength:
+ description:
+ Selects the drive strength for MIO pins, in mA.
+ enum: [2, 4, 6, 8]
+
+ required:
+ - pins
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pinctrl {
+ compatible = "airoha,an7563-pinctrl";
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ pcie1-rst-pins {
+ conf {
+ pins = "pcie_reset1";
+ drive-open-drain = <1>;
+ };
+ };
+
+ pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "gpio18";
+ };
+ };
+
+ spi-pins {
+ mux {
+ function = "spi";
+ groups = "spi_quad", "spi_cs1";
+ };
+ };
+
+ hsuart-pins {
+ mux {
+ function = "uart";
+ groups = "hsuart", "hsuart_cts_rts";
+ };
+ };
+
+ mdio-pins {
+ mux {
+ function = "mdio";
+ groups = "mdio";
+ };
+
+ conf {
+ pins = "gpio2";
+ output-enable;
+ };
+ };
+ };
diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
index 159b4496f64a..480ff2f26911 100644
--- a/drivers/pinctrl/airoha/Kconfig
+++ b/drivers/pinctrl/airoha/Kconfig
@@ -13,6 +13,7 @@ config PINCTRL_AIROHA
select GPIOLIB
select GPIOLIB_IRQCHIP
select REGMAP_MMIO
+ imply PINCTRL_AIROHA_AN7563
imply PINCTRL_AIROHA_AN7581
imply PINCTRL_AIROHA_AN7583
imply PINCTRL_AIROHA_EN7523
@@ -20,6 +21,11 @@ config PINCTRL_AIROHA
Say yes here to support pin controller and gpio driver
on Airoha SoC.
+config PINCTRL_AIROHA_AN7563
+ tristate "AN7563 pinctrl"
+ depends on ARM64 || COMPILE_TEST
+ depends on PINCTRL_AIROHA
+
config PINCTRL_AIROHA_AN7581
tristate "AN7581 pinctrl"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
index 8b9202321ba8..30e4bee57a4a 100644
--- a/drivers/pinctrl/airoha/Makefile
+++ b/drivers/pinctrl/airoha/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
# SoC drivers
+obj-$(CONFIG_PINCTRL_AIROHA_AN7563) += pinctrl-an7563.o
obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o
obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o
obj-$(CONFIG_PINCTRL_AIROHA_EN7523) += pinctrl-en7523.o
diff --git a/drivers/pinctrl/airoha/pinctrl-an7563.c b/drivers/pinctrl/airoha/pinctrl-an7563.c
new file mode 100644
index 000000000000..40cbbe90cc46
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-an7563.c
@@ -0,0 +1,1115 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * AN7563 SoC pinctrl data for the Airoha pinctrl driver (pinctrl-airoha.c).
+ *
+ * Sources: AN7563 Programming Guide chapter 2 (CHIP SCU, base 0x1fa20000),
+ * chapter 17 (GPIO controller, base 0x1fbf0200) and AN7563PT datasheet
+ * chapter 4.3 (pin sharing scheme).
+ *
+ * Pin numbering follows the GPIO line numbering of the SoC:
+ * pins 0-27 -> GPIO0-GPIO27 (dedicated GPIO pads)
+ * pins 28/29 -> PCIE_RESET0/PCIE_RESET1 pads (GPIO28/GPIO29)
+ * pins 30/31 -> I2C_SCL/I2C_SDA pads (GPIO30/GPIO31)
+ * pins 32-35 -> SPI_CLK/SPI_CS/SPI_MOSI/SPI_MISO pads (GPIO32-GPIO35)
+ * pins 36/37 -> UART_TXD/UART_RXD pads (GPIO36/GPIO37)
+ *
+ * Definitions marked "shared" are identical to the ones already present in
+ * pinctrl-airoha.c (EN7581/AN7583) and must be dropped when this data is
+ * merged there.
+ */
+
+#include "airoha-common.h"
+
+/*
+ * shared - named RG_SW_TOD_1PPS_MODE on AN7563. Only the LAN LED mode
+ * bits and GSW_TOD_1PPS exist on AN7563 (no 2nd I2C, I2S or PON 1PPS).
+ */
+#define REG_GPIO_2ND_I2C_MODE 0x0214
+#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
+#define GSW_TOD_1PPS_MODE_MASK BIT(1)
+
+/* shared */
+#define REG_GPIO_SPI_CS1_MODE 0x0218
+#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
+#define GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK BIT(16)
+#define GPIO_PCM2_MODE_MASK BIT(13)
+#define GPIO_PCM1_MODE_MASK BIT(12)
+#define GPIO_PCM_INT_MODE_MASK BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
+#define GPIO_SPI_CS4_MODE_MASK BIT(3)
+#define GPIO_SPI_CS3_MODE_MASK BIT(2)
+#define GPIO_SPI_CS2_MODE_MASK BIT(1)
+#define GPIO_SPI_CS1_MODE_MASK BIT(0)
+
+#define REG_GPIO_PON_MODE 0x021c
+/*
+ * AN7563 specific: route the standalone pads to their GPIO function.
+ * 0: pad keeps its base function, 1: pad is GPIO<n>.
+ */
+#define UART_RXD_GPIO_MODE_MASK BIT(22) /* GPIO37 */
+#define UART_TXD_GPIO_MODE_MASK BIT(21) /* GPIO36 */
+#define SPI_MISO_GPIO_MODE_MASK BIT(20) /* GPIO35 */
+#define SPI_MOSI_GPIO_MODE_MASK BIT(19) /* GPIO34 */
+#define SPI_CS_GPIO_MODE_MASK BIT(18) /* GPIO33 */
+#define SPI_CLK_GPIO_MODE_MASK BIT(17) /* GPIO32 */
+#define I2C_SDA_GPIO_MODE_MASK BIT(16) /* GPIO31 */
+#define I2C_SCL_GPIO_MODE_MASK BIT(15) /* GPIO30 */
+/* shared */
+#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
+#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
+#define SIPO_RCLK_MODE_MASK BIT(11)
+/*
+ * Note: on AN7563 GPIO_PCIE_RESET{0,1} select the GPIO function of the
+ * PCIE_RESET pads (0: PCIe reset, 1: GPIO28/GPIO29).
+ */
+#define GPIO_PCIE_RESET1_MASK BIT(10) /* GPIO29 */
+#define GPIO_PCIE_RESET0_MASK BIT(9) /* GPIO28 */
+#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6)
+#define GPIO_HSUART_MODE_MASK BIT(5)
+#define GPIO_SIPO_MODE_MASK BIT(2)
+#define GPIO_PON_MODE_MASK BIT(0)
+
+/* shared */
+#define REG_NPU_UART_EN 0x0224
+#define JTAG_UDI_EN_MASK BIT(4)
+#define JTAG_DFD_EN_MASK BIT(3)
+
+/* LED MAP - shared */
+#define REG_LAN_LED0_MAPPING 0x027c
+#define REG_LAN_LED1_MAPPING 0x0280
+
+#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/*
+ * CONF - shared.
+ * The AN7563 standalone IO conf registers use the same bit layout as
+ * EN7581 (UART1_TXD/RXD are named UART_TXD/RXD on AN7563).
+ */
+#define REG_I2C_SDA_E2 0x001c
+#define SPI_MISO_E2_MASK BIT(14)
+#define SPI_MOSI_E2_MASK BIT(13)
+#define SPI_CLK_E2_MASK BIT(12)
+#define SPI_CS0_E2_MASK BIT(11)
+#define PCIE1_RESET_E2_MASK BIT(9)
+#define PCIE0_RESET_E2_MASK BIT(8)
+#define UART1_RXD_E2_MASK BIT(3)
+#define UART1_TXD_E2_MASK BIT(2)
+#define I2C_SCL_E2_MASK BIT(1)
+#define I2C_SDA_E2_MASK BIT(0)
+
+#define REG_I2C_SDA_E4 0x0020
+#define SPI_MISO_E4_MASK BIT(14)
+#define SPI_MOSI_E4_MASK BIT(13)
+#define SPI_CLK_E4_MASK BIT(12)
+#define SPI_CS0_E4_MASK BIT(11)
+#define PCIE1_RESET_E4_MASK BIT(9)
+#define PCIE0_RESET_E4_MASK BIT(8)
+#define UART1_RXD_E4_MASK BIT(3)
+#define UART1_TXD_E4_MASK BIT(2)
+#define I2C_SCL_E4_MASK BIT(1)
+#define I2C_SDA_E4_MASK BIT(0)
+
+#define REG_GPIO_L_E2 0x0024
+#define REG_GPIO_L_E4 0x0028
+
+#define REG_I2C_SDA_PU 0x0044
+#define SPI_MISO_PU_MASK BIT(14)
+#define SPI_MOSI_PU_MASK BIT(13)
+#define SPI_CLK_PU_MASK BIT(12)
+#define SPI_CS0_PU_MASK BIT(11)
+#define PCIE1_RESET_PU_MASK BIT(9)
+#define PCIE0_RESET_PU_MASK BIT(8)
+#define UART1_RXD_PU_MASK BIT(3)
+#define UART1_TXD_PU_MASK BIT(2)
+#define I2C_SCL_PU_MASK BIT(1)
+#define I2C_SDA_PU_MASK BIT(0)
+
+#define REG_I2C_SDA_PD 0x0048
+#define SPI_MISO_PD_MASK BIT(14)
+#define SPI_MOSI_PD_MASK BIT(13)
+#define SPI_CLK_PD_MASK BIT(12)
+#define SPI_CS0_PD_MASK BIT(11)
+#define PCIE1_RESET_PD_MASK BIT(9)
+#define PCIE0_RESET_PD_MASK BIT(8)
+#define UART1_RXD_PD_MASK BIT(3)
+#define UART1_TXD_PD_MASK BIT(2)
+#define I2C_SCL_PD_MASK BIT(1)
+#define I2C_SDA_PD_MASK BIT(0)
+
+#define REG_GPIO_L_PU 0x004c
+#define REG_GPIO_L_PD 0x0050
+
+#define REG_PCIE_RESET_OD 0x018c
+#define PCIE1_RESET_OD_MASK BIT(1)
+#define PCIE0_RESET_OD_MASK BIT(0)
+
+/*
+ * PWM MODE CONF - shared.
+ * The AN7563 GPIO flash mode registers use the same layout as EN7581:
+ * REG_GPIO_FLASH_MODE_CFG covers GPIO0-15, REG_GPIO_FLASH_MODE_CFG_EXT
+ * covers GPIO16-31 (bits 0-15) and GPIO36+ (bits 16+). The SPI pads
+ * (GPIO32-35) have no flash mode configuration bit.
+ */
+#define REG_GPIO_FLASH_MODE_CFG 0x0034
+#define GPIO15_FLASH_MODE_CFG BIT(15)
+#define GPIO14_FLASH_MODE_CFG BIT(14)
+#define GPIO13_FLASH_MODE_CFG BIT(13)
+#define GPIO12_FLASH_MODE_CFG BIT(12)
+#define GPIO11_FLASH_MODE_CFG BIT(11)
+#define GPIO10_FLASH_MODE_CFG BIT(10)
+#define GPIO9_FLASH_MODE_CFG BIT(9)
+#define GPIO8_FLASH_MODE_CFG BIT(8)
+#define GPIO7_FLASH_MODE_CFG BIT(7)
+#define GPIO6_FLASH_MODE_CFG BIT(6)
+#define GPIO5_FLASH_MODE_CFG BIT(5)
+#define GPIO4_FLASH_MODE_CFG BIT(4)
+#define GPIO3_FLASH_MODE_CFG BIT(3)
+#define GPIO2_FLASH_MODE_CFG BIT(2)
+#define GPIO1_FLASH_MODE_CFG BIT(1)
+#define GPIO0_FLASH_MODE_CFG BIT(0)
+
+#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
+#define GPIO37_FLASH_MODE_CFG BIT(17)
+#define GPIO36_FLASH_MODE_CFG BIT(16)
+#define GPIO31_FLASH_MODE_CFG BIT(15)
+#define GPIO30_FLASH_MODE_CFG BIT(14)
+#define GPIO29_FLASH_MODE_CFG BIT(13)
+#define GPIO28_FLASH_MODE_CFG BIT(12)
+#define GPIO27_FLASH_MODE_CFG BIT(11)
+#define GPIO26_FLASH_MODE_CFG BIT(10)
+#define GPIO25_FLASH_MODE_CFG BIT(9)
+#define GPIO24_FLASH_MODE_CFG BIT(8)
+#define GPIO23_FLASH_MODE_CFG BIT(7)
+#define GPIO22_FLASH_MODE_CFG BIT(6)
+#define GPIO21_FLASH_MODE_CFG BIT(5)
+#define GPIO20_FLASH_MODE_CFG BIT(4)
+#define GPIO19_FLASH_MODE_CFG BIT(3)
+#define GPIO18_FLASH_MODE_CFG BIT(2)
+#define GPIO17_FLASH_MODE_CFG BIT(1)
+#define GPIO16_FLASH_MODE_CFG BIT(0)
+
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ 0 \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_MUX, \
+ REG_GPIO_FLASH_MODE_CFG, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED0_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED1_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+static const struct pinctrl_pin_desc pinctrl_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+ PINCTRL_PIN(14, "gpio14"),
+ PINCTRL_PIN(15, "gpio15"),
+ PINCTRL_PIN(16, "gpio16"),
+ PINCTRL_PIN(17, "gpio17"),
+ PINCTRL_PIN(18, "gpio18"),
+ PINCTRL_PIN(19, "gpio19"),
+ PINCTRL_PIN(20, "gpio20"),
+ PINCTRL_PIN(21, "gpio21"),
+ PINCTRL_PIN(22, "gpio22"),
+ PINCTRL_PIN(23, "gpio23"),
+ PINCTRL_PIN(24, "gpio24"),
+ PINCTRL_PIN(25, "gpio25"),
+ PINCTRL_PIN(26, "gpio26"),
+ PINCTRL_PIN(27, "gpio27"),
+ PINCTRL_PIN(28, "pcie_reset0"), /* GPIO28 */
+ PINCTRL_PIN(29, "pcie_reset1"), /* GPIO29 */
+ PINCTRL_PIN(30, "i2c_scl"), /* GPIO30 */
+ PINCTRL_PIN(31, "i2c_sda"), /* GPIO31 */
+ PINCTRL_PIN(32, "spi_clk"), /* GPIO32 */
+ PINCTRL_PIN(33, "spi_cs"), /* GPIO33 */
+ PINCTRL_PIN(34, "spi_mosi"), /* GPIO34 */
+ PINCTRL_PIN(35, "spi_miso"), /* GPIO35 */
+ PINCTRL_PIN(36, "uart_txd"), /* GPIO36 */
+ PINCTRL_PIN(37, "uart_rxd"), /* GPIO37 */
+};
+
+static const int pon_pins[] = { 14, 15, 16, 17, 18, 19 };
+static const int sipo_pins[] = { 20, 21 };
+static const int sipo_rclk_pins[] = { 20, 21, 26 };
+static const int mdio_pins[] = { 30, 31 };
+static const int hsuart_pins[] = { 16, 17 };
+static const int hsuart_cts_rts_pins[] = { 14, 15 };
+static const int i2c_pins[] = { 30, 31 };
+static const int jtag_udi_pins[] = { 7, 8, 9, 10, 11 };
+static const int jtag_dfd_pins[] = { 7, 8, 9, 10, 11 };
+static const int pcm1_pins[] = { 22, 23, 24, 25 };
+static const int pcm2_pins[] = { 1, 2, 3, 4 };
+static const int spi_pins[] = { 32, 33, 34, 35 };
+static const int spi_quad_pins[] = { 2, 3 };
+static const int spi_cs1_pins[] = { 4 };
+static const int pnand_pins[] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 32, 33, 34, 35
+};
+static const int gpio0_pins[] = { 0 };
+static const int gpio1_pins[] = { 1 };
+static const int gpio2_pins[] = { 2 };
+static const int gpio3_pins[] = { 3 };
+static const int gpio4_pins[] = { 4 };
+static const int gpio5_pins[] = { 5 };
+static const int gpio6_pins[] = { 6 };
+static const int gpio7_pins[] = { 7 };
+static const int gpio8_pins[] = { 8 };
+static const int gpio9_pins[] = { 9 };
+static const int gpio10_pins[] = { 10 };
+static const int gpio11_pins[] = { 11 };
+static const int gpio12_pins[] = { 12 };
+static const int gpio13_pins[] = { 13 };
+static const int gpio14_pins[] = { 14 };
+static const int gpio15_pins[] = { 15 };
+static const int gpio16_pins[] = { 16 };
+static const int gpio17_pins[] = { 17 };
+static const int gpio18_pins[] = { 18 };
+static const int gpio19_pins[] = { 19 };
+static const int gpio20_pins[] = { 20 };
+static const int gpio21_pins[] = { 21 };
+static const int gpio22_pins[] = { 22 };
+static const int gpio23_pins[] = { 23 };
+static const int gpio24_pins[] = { 24 };
+static const int gpio25_pins[] = { 25 };
+static const int gpio26_pins[] = { 26 };
+static const int gpio27_pins[] = { 27 };
+static const int gpio28_pins[] = { 28 };
+static const int gpio29_pins[] = { 29 };
+static const int gpio30_pins[] = { 30 };
+static const int gpio31_pins[] = { 31 };
+static const int gpio32_pins[] = { 32 };
+static const int gpio33_pins[] = { 33 };
+static const int gpio34_pins[] = { 34 };
+static const int gpio35_pins[] = { 35 };
+static const int gpio36_pins[] = { 36 };
+static const int gpio37_pins[] = { 37 };
+static const int pcie_reset0_pins[] = { 28 };
+static const int pcie_reset1_pins[] = { 29 };
+
+static const struct pingroup pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("sipo", sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", mdio),
+ PINCTRL_PIN_GROUP("hsuart", hsuart),
+ PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
+ PINCTRL_PIN_GROUP("i2c", i2c),
+ PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+ PINCTRL_PIN_GROUP("pcm1", pcm1),
+ PINCTRL_PIN_GROUP("pcm2", pcm2),
+ PINCTRL_PIN_GROUP("spi", spi),
+ PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+ PINCTRL_PIN_GROUP("pnand", pnand),
+ PINCTRL_PIN_GROUP("gpio0", gpio0),
+ PINCTRL_PIN_GROUP("gpio1", gpio1),
+ PINCTRL_PIN_GROUP("gpio2", gpio2),
+ PINCTRL_PIN_GROUP("gpio3", gpio3),
+ PINCTRL_PIN_GROUP("gpio4", gpio4),
+ PINCTRL_PIN_GROUP("gpio5", gpio5),
+ PINCTRL_PIN_GROUP("gpio6", gpio6),
+ PINCTRL_PIN_GROUP("gpio7", gpio7),
+ PINCTRL_PIN_GROUP("gpio8", gpio8),
+ PINCTRL_PIN_GROUP("gpio9", gpio9),
+ PINCTRL_PIN_GROUP("gpio10", gpio10),
+ PINCTRL_PIN_GROUP("gpio11", gpio11),
+ PINCTRL_PIN_GROUP("gpio12", gpio12),
+ PINCTRL_PIN_GROUP("gpio13", gpio13),
+ PINCTRL_PIN_GROUP("gpio14", gpio14),
+ PINCTRL_PIN_GROUP("gpio15", gpio15),
+ PINCTRL_PIN_GROUP("gpio16", gpio16),
+ PINCTRL_PIN_GROUP("gpio17", gpio17),
+ PINCTRL_PIN_GROUP("gpio18", gpio18),
+ PINCTRL_PIN_GROUP("gpio19", gpio19),
+ PINCTRL_PIN_GROUP("gpio20", gpio20),
+ PINCTRL_PIN_GROUP("gpio21", gpio21),
+ PINCTRL_PIN_GROUP("gpio22", gpio22),
+ PINCTRL_PIN_GROUP("gpio23", gpio23),
+ PINCTRL_PIN_GROUP("gpio24", gpio24),
+ PINCTRL_PIN_GROUP("gpio25", gpio25),
+ PINCTRL_PIN_GROUP("gpio26", gpio26),
+ PINCTRL_PIN_GROUP("gpio27", gpio27),
+ PINCTRL_PIN_GROUP("gpio28", gpio28),
+ PINCTRL_PIN_GROUP("gpio29", gpio29),
+ PINCTRL_PIN_GROUP("gpio30", gpio30),
+ PINCTRL_PIN_GROUP("gpio31", gpio31),
+ PINCTRL_PIN_GROUP("gpio32", gpio32),
+ PINCTRL_PIN_GROUP("gpio33", gpio33),
+ PINCTRL_PIN_GROUP("gpio34", gpio34),
+ PINCTRL_PIN_GROUP("gpio35", gpio35),
+ PINCTRL_PIN_GROUP("gpio36", gpio36),
+ PINCTRL_PIN_GROUP("gpio37", gpio37),
+ PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+};
+
+/* shared */
+static const char *const pon_groups[] = { "pon" };
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const mdio_groups[] = { "mdio" };
+static const char *const uart_groups[] = {
+ "hsuart", "hsuart_cts_rts"
+};
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const pnand_groups[] = { "pnand" };
+static const char *const gpio_groups[] = {
+ "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
+ "gpio33", "gpio34", "gpio35", "gpio36", "gpio37"
+};
+static const char *const pcie_reset_groups[] = {
+ "pcie_reset0", "pcie_reset1"
+};
+static const char *const pwm_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+ "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio36", "gpio37"
+};
+static const char *const phy1_led0_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const phy2_led0_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const phy3_led0_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const phy4_led0_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+static const char *const phy1_led1_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7"
+};
+static const char *const phy2_led1_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7"
+};
+static const char *const phy3_led1_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7"
+};
+static const char *const phy4_led1_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7"
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+ {
+ .name = "pon",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PON_MODE_MASK,
+ GPIO_PON_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+ {
+ .name = "sipo",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "sipo_rclk",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+/*
+ * On AN7563 the SMI master (MDC/MDIO) is shared with the I2C_SCL/I2C_SDA
+ * pads and selected via the SGMII MDIO mode bit. I2C is the default pad
+ * function (no mux bit).
+ */
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
+ {
+ .name = "mdio",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SGMII_MDIO_MODE_MASK,
+ GPIO_SGMII_MDIO_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+ {
+ .name = "hsuart",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+ GPIO_HSUART_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+ {
+ .name = "hsuart_cts_rts",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+ GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+ {
+ .name = "jtag_udi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_UDI_EN_MASK,
+ JTAG_UDI_EN_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "jtag_dfd",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_DFD_EN_MASK,
+ JTAG_DFD_EN_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+ {
+ .name = "pcm1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM1_MODE_MASK,
+ GPIO_PCM1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM2_MODE_MASK,
+ GPIO_PCM2_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+ {
+ .name = "spi_quad",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_QUAD_MODE_MASK,
+ GPIO_SPI_QUAD_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS1_MODE_MASK,
+ GPIO_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+/* shared */
+static const struct airoha_pinctrl_func_group pnand_func_group[] = {
+ {
+ .name = "pnand",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PARALLEL_NAND_MODE_MASK,
+ GPIO_PARALLEL_NAND_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+ AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio30", GPIO30_FLASH_MODE_CFG,
+ I2C_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio31", GPIO31_FLASH_MODE_CFG,
+ I2C_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO("gpio32", SPI_CLK_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO("gpio33", SPI_CS_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO("gpio34", SPI_MOSI_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO("gpio35", SPI_MISO_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio36", GPIO36_FLASH_MODE_CFG,
+ UART_TXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio37", GPIO37_FLASH_MODE_CFG,
+ UART_RXD_GPIO_MODE_MASK),
+};
+
+/*
+ * On AN7563 a set GPIO_PCIE_RESET{0,1} bit routes the pad to its GPIO
+ * function, so the PCIe reset function must clear it.
+ */
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+ {
+ .name = "pcie_reset0",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET0_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcie_reset1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET1_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+ AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio30", GPIO30_FLASH_MODE_CFG,
+ I2C_SCL_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio31", GPIO31_FLASH_MODE_CFG,
+ I2C_SDA_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio36", GPIO36_FLASH_MODE_CFG,
+ UART_TXD_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio37", GPIO37_FLASH_MODE_CFG,
+ UART_RXD_GPIO_MODE_MASK),
+};
+
+/*
+ * LED pad mapping (datasheet table 4-9):
+ * GPIO8: LAN0_LED0, GPIO9: LAN1_LED0, GPIO10: LAN2_LED0, GPIO11: LAN3_LED0
+ * GPIO7: LAN0_LED1, GPIO6: LAN1_LED1, GPIO5: LAN2_LED1, GPIO4: LAN3_LED1
+ */
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
+ PINCTRL_FUNC_DESC("pon", pon),
+ PINCTRL_FUNC_DESC("sipo", sipo),
+ PINCTRL_FUNC_DESC("mdio", mdio),
+ PINCTRL_FUNC_DESC("uart", uart),
+ PINCTRL_FUNC_DESC("jtag", jtag),
+ PINCTRL_FUNC_DESC("pcm", pcm),
+ PINCTRL_FUNC_DESC("spi", spi),
+ PINCTRL_FUNC_DESC("pnand", pnand),
+ PINCTRL_FUNC_DESC("gpio", gpio),
+ PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+ PINCTRL_FUNC_DESC("pwm", pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+ PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+ PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+ PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_GPIO_L_PU, BIT(0)),
+ PINCTRL_CONF_DESC(1, REG_GPIO_L_PU, BIT(1)),
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(2)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(3)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(4)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(5)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(6)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(7)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(8)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(9)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(10)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(11)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(12)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(13)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(14)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(15)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(16)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(17)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(18)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(19)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(20)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(21)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(22)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(23)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(24)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(25)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(26)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(27)),
+ PINCTRL_CONF_DESC(28, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+ PINCTRL_CONF_DESC(29, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+ PINCTRL_CONF_DESC(30, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+ PINCTRL_CONF_DESC(31, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+ PINCTRL_CONF_DESC(32, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+ PINCTRL_CONF_DESC(33, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+ PINCTRL_CONF_DESC(34, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+ PINCTRL_CONF_DESC(35, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
+ PINCTRL_CONF_DESC(36, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+ PINCTRL_CONF_DESC(37, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_GPIO_L_PD, BIT(0)),
+ PINCTRL_CONF_DESC(1, REG_GPIO_L_PD, BIT(1)),
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(2)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(3)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(4)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(5)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(6)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(7)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(8)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(9)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(10)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(11)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(12)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(13)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(14)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(15)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(16)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(17)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(18)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(19)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(20)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(21)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(22)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(23)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(24)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(25)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(26)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(27)),
+ PINCTRL_CONF_DESC(28, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+ PINCTRL_CONF_DESC(29, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+ PINCTRL_CONF_DESC(30, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+ PINCTRL_CONF_DESC(31, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+ PINCTRL_CONF_DESC(32, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+ PINCTRL_CONF_DESC(33, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+ PINCTRL_CONF_DESC(34, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+ PINCTRL_CONF_DESC(35, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
+ PINCTRL_CONF_DESC(36, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+ PINCTRL_CONF_DESC(37, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_GPIO_L_E2, BIT(0)),
+ PINCTRL_CONF_DESC(1, REG_GPIO_L_E2, BIT(1)),
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(2)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(3)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(4)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(5)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(6)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(7)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(8)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(9)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(10)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(11)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(12)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(13)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(14)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(15)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(16)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(17)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(18)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(19)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(20)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(21)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(22)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(23)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(24)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(25)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(26)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(27)),
+ PINCTRL_CONF_DESC(28, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+ PINCTRL_CONF_DESC(29, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+ PINCTRL_CONF_DESC(30, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+ PINCTRL_CONF_DESC(31, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+ PINCTRL_CONF_DESC(32, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+ PINCTRL_CONF_DESC(33, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+ PINCTRL_CONF_DESC(34, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+ PINCTRL_CONF_DESC(35, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
+ PINCTRL_CONF_DESC(36, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+ PINCTRL_CONF_DESC(37, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
+ PINCTRL_CONF_DESC(0, REG_GPIO_L_E4, BIT(0)),
+ PINCTRL_CONF_DESC(1, REG_GPIO_L_E4, BIT(1)),
+ PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(2)),
+ PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(3)),
+ PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(4)),
+ PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(5)),
+ PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(6)),
+ PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(7)),
+ PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(8)),
+ PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(9)),
+ PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(10)),
+ PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(11)),
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(12)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(13)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(14)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(15)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(16)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(17)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(18)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(19)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(20)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(21)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(22)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(23)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(24)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(25)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(26)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(27)),
+ PINCTRL_CONF_DESC(28, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+ PINCTRL_CONF_DESC(29, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+ PINCTRL_CONF_DESC(30, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+ PINCTRL_CONF_DESC(31, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+ PINCTRL_CONF_DESC(32, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+ PINCTRL_CONF_DESC(33, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+ PINCTRL_CONF_DESC(34, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+ PINCTRL_CONF_DESC(35, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
+ PINCTRL_CONF_DESC(36, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+ PINCTRL_CONF_DESC(37, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
+ PINCTRL_CONF_DESC(28, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(29, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+};
+
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .chip_scu_compatible = "airoha,en7581-chip-scu",
+ .pinctrl_name = KBUILD_MODNAME,
+ .pinctrl_owner = THIS_MODULE,
+ .pins = pinctrl_pins,
+ .num_pins = ARRAY_SIZE(pinctrl_pins),
+ .grps = pinctrl_groups,
+ .num_grps = ARRAY_SIZE(pinctrl_groups),
+ .funcs = pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(pinctrl_funcs),
+ .confs_info = {
+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
+ .confs = pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+ .confs = pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+ .confs = pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+ .confs = pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+ .confs = pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
+ },
+ },
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+ { .compatible = "airoha,an7563-pinctrl", .data = &pinctrl_match_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+ .probe = airoha_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-airoha-an7563",
+ .of_match_table = airoha_pinctrl_of_match,
+ },
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7563 SoC");
--
2.53.0
^ permalink raw reply related
* [PATCH v6 10/17] pinctrl: airoha: an7583: remove an7583 prefix from variable names and definitions
From: Mikhail Kshevetskiy @ 2026-06-28 14:37 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260628143733.273651-1-mikhail.kshevetskiy@iopsys.eu>
We have only an7583 specific code in the pinctrl-an7583 kernel module,
so an7583 prefix is not necessary anymore. Remove it.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/pinctrl-an7583.c | 600 ++++++++++++------------
1 file changed, 300 insertions(+), 300 deletions(-)
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index b9d8dd94de5f..637b9377ff8f 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -24,7 +24,7 @@
#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(22)
#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
-#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
+#define GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
#define GPIO_PCM_SPI_MODE_MASK BIT(16)
#define GPIO_PCM2_MODE_MASK BIT(13)
@@ -38,18 +38,18 @@
#define GPIO_SPI_CS1_MODE_MASK BIT(0)
#define REG_GPIO_PON_MODE 0x021c
-#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26)
-#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25)
-#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24)
-#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23)
-#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22)
-#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21)
-#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20)
-#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19)
-#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18)
-#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17)
-#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16)
-#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15)
+#define MDIO_0_GPIO_MODE_MASK BIT(26)
+#define MDC_0_GPIO_MODE_MASK BIT(25)
+#define UART_RXD_GPIO_MODE_MASK BIT(24)
+#define UART_TXD_GPIO_MODE_MASK BIT(23)
+#define SPI_MISO_GPIO_MODE_MASK BIT(22)
+#define SPI_MOSI_GPIO_MODE_MASK BIT(21)
+#define SPI_CS_GPIO_MODE_MASK BIT(20)
+#define SPI_CLK_GPIO_MODE_MASK BIT(19)
+#define I2C1_SDA_GPIO_MODE_MASK BIT(18)
+#define I2C1_SCL_GPIO_MODE_MASK BIT(17)
+#define I2C0_SDA_GPIO_MODE_MASK BIT(16)
+#define I2C0_SCL_GPIO_MODE_MASK BIT(15)
#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
#define SIPO_RCLK_MODE_MASK BIT(11)
@@ -93,32 +93,32 @@
/* CONF */
#define REG_I2C_SDA_E2 0x001c
-#define AN7583_I2C1_SCL_E2_MASK BIT(16)
-#define AN7583_I2C1_SDA_E2_MASK BIT(15)
+#define I2C1_SCL_E2_MASK BIT(16)
+#define I2C1_SDA_E2_MASK BIT(15)
#define SPI_MISO_E2_MASK BIT(14)
#define SPI_MOSI_E2_MASK BIT(13)
#define SPI_CLK_E2_MASK BIT(12)
#define SPI_CS0_E2_MASK BIT(11)
#define PCIE1_RESET_E2_MASK BIT(9)
#define PCIE0_RESET_E2_MASK BIT(8)
-#define AN7583_MDIO_0_E2_MASK BIT(5)
-#define AN7583_MDC_0_E2_MASK BIT(4)
+#define MDIO_0_E2_MASK BIT(5)
+#define MDC_0_E2_MASK BIT(4)
#define UART1_RXD_E2_MASK BIT(3)
#define UART1_TXD_E2_MASK BIT(2)
#define I2C_SCL_E2_MASK BIT(1)
#define I2C_SDA_E2_MASK BIT(0)
#define REG_I2C_SDA_E4 0x0020
-#define AN7583_I2C1_SCL_E4_MASK BIT(16)
-#define AN7583_I2C1_SDA_E4_MASK BIT(15)
+#define I2C1_SCL_E4_MASK BIT(16)
+#define I2C1_SDA_E4_MASK BIT(15)
#define SPI_MISO_E4_MASK BIT(14)
#define SPI_MOSI_E4_MASK BIT(13)
#define SPI_CLK_E4_MASK BIT(12)
#define SPI_CS0_E4_MASK BIT(11)
#define PCIE1_RESET_E4_MASK BIT(9)
#define PCIE0_RESET_E4_MASK BIT(8)
-#define AN7583_MDIO_0_E4_MASK BIT(5)
-#define AN7583_MDC_0_E4_MASK BIT(4)
+#define MDIO_0_E4_MASK BIT(5)
+#define MDC_0_E4_MASK BIT(4)
#define UART1_RXD_E4_MASK BIT(3)
#define UART1_TXD_E4_MASK BIT(2)
#define I2C_SCL_E4_MASK BIT(1)
@@ -130,32 +130,32 @@
#define REG_GPIO_H_E4 0x0030
#define REG_I2C_SDA_PU 0x0044
-#define AN7583_I2C1_SCL_PU_MASK BIT(16)
-#define AN7583_I2C1_SDA_PU_MASK BIT(15)
+#define I2C1_SCL_PU_MASK BIT(16)
+#define I2C1_SDA_PU_MASK BIT(15)
#define SPI_MISO_PU_MASK BIT(14)
#define SPI_MOSI_PU_MASK BIT(13)
#define SPI_CLK_PU_MASK BIT(12)
#define SPI_CS0_PU_MASK BIT(11)
#define PCIE1_RESET_PU_MASK BIT(9)
#define PCIE0_RESET_PU_MASK BIT(8)
-#define AN7583_MDIO_0_PU_MASK BIT(5)
-#define AN7583_MDC_0_PU_MASK BIT(4)
+#define MDIO_0_PU_MASK BIT(5)
+#define MDC_0_PU_MASK BIT(4)
#define UART1_RXD_PU_MASK BIT(3)
#define UART1_TXD_PU_MASK BIT(2)
#define I2C_SCL_PU_MASK BIT(1)
#define I2C_SDA_PU_MASK BIT(0)
#define REG_I2C_SDA_PD 0x0048
-#define AN7583_I2C1_SCL_PD_MASK BIT(16)
-#define AN7583_I2C1_SDA_PD_MASK BIT(15)
+#define I2C1_SCL_PD_MASK BIT(16)
+#define I2C1_SDA_PD_MASK BIT(15)
#define SPI_MISO_PD_MASK BIT(14)
#define SPI_MOSI_PD_MASK BIT(13)
#define SPI_CLK_PD_MASK BIT(12)
#define SPI_CS0_PD_MASK BIT(11)
#define PCIE1_RESET_PD_MASK BIT(9)
#define PCIE0_RESET_PD_MASK BIT(8)
-#define AN7583_MDIO_0_PD_MASK BIT(5)
-#define AN7583_MDC_0_PD_MASK BIT(4)
+#define MDIO_0_PD_MASK BIT(5)
+#define MDC_0_PD_MASK BIT(4)
#define UART1_RXD_PD_MASK BIT(3)
#define UART1_TXD_PD_MASK BIT(2)
#define I2C_SCL_PD_MASK BIT(1)
@@ -333,7 +333,7 @@
.regmap_size = 2, \
}
-static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
+static struct pinctrl_pin_desc pinctrl_pins[] = {
PINCTRL_PIN(2, "gpio0"),
PINCTRL_PIN(3, "gpio1"),
PINCTRL_PIN(4, "gpio2"),
@@ -389,176 +389,176 @@ static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
PINCTRL_PIN(54, "mdio_0"),
};
-static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
-static const int an7583_pon_tod_1pps_pins[] = { 32 };
-static const int an7583_gsw_tod_1pps_pins[] = { 32 };
-static const int an7583_sipo_pins[] = { 34, 35 };
-static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
-static const int an7583_mdio_pins[] = { 43, 44 };
-static const int an7583_uart2_pins[] = { 34, 35 };
-static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
-static const int an7583_hsuart_pins[] = { 30, 31 };
-static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
-static const int an7583_npu_uart_pins[] = { 7, 8 };
-static const int an7583_uart4_pins[] = { 7, 8 };
-static const int an7583_uart5_pins[] = { 23, 24 };
-static const int an7583_i2c0_pins[] = { 41, 42 };
-static const int an7583_i2c1_pins[] = { 43, 44 };
-static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
-static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
-static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
-static const int an7583_spi_quad_pins[] = { 25, 26 };
-static const int an7583_spi_cs1_pins[] = { 27 };
-static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
-static const int an7583_pcm_spi_rst_pins[] = { 14 };
-static const int an7583_pcm_spi_cs1_pins[] = { 24 };
-static const int an7583_emmc_pins[] = {
+static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+static const int pon_tod_1pps_pins[] = { 32 };
+static const int gsw_tod_1pps_pins[] = { 32 };
+static const int sipo_pins[] = { 34, 35 };
+static const int sipo_rclk_pins[] = { 34, 35, 33 };
+static const int mdio_pins[] = { 43, 44 };
+static const int uart2_pins[] = { 34, 35 };
+static const int uart2_cts_rts_pins[] = { 32, 33 };
+static const int hsuart_pins[] = { 30, 31 };
+static const int hsuart_cts_rts_pins[] = { 28, 29 };
+static const int npu_uart_pins[] = { 7, 8 };
+static const int uart4_pins[] = { 7, 8 };
+static const int uart5_pins[] = { 23, 24 };
+static const int i2c0_pins[] = { 41, 42 };
+static const int i2c1_pins[] = { 43, 44 };
+static const int jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
+static const int jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+static const int pcm1_pins[] = { 10, 11, 12, 13, 14 };
+static const int pcm2_pins[] = { 28, 29, 30, 31, 24 };
+static const int spi_pins[] = { 28, 29, 30, 31 };
+static const int spi_quad_pins[] = { 25, 26 };
+static const int spi_cs1_pins[] = { 27 };
+static const int pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
+static const int pcm_spi_rst_pins[] = { 14 };
+static const int pcm_spi_cs1_pins[] = { 24 };
+static const int emmc_pins[] = {
7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
};
-static const int an7583_pnand_pins[] = {
+static const int pnand_pins[] = {
7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
};
-static const int an7583_gpio0_pins[] = { 2 };
-static const int an7583_gpio1_pins[] = { 3 };
-static const int an7583_gpio2_pins[] = { 4 };
-static const int an7583_gpio3_pins[] = { 5 };
-static const int an7583_gpio4_pins[] = { 6 };
-static const int an7583_gpio5_pins[] = { 7 };
-static const int an7583_gpio6_pins[] = { 8 };
-static const int an7583_gpio7_pins[] = { 9 };
-static const int an7583_gpio8_pins[] = { 10 };
-static const int an7583_gpio9_pins[] = { 11 };
-static const int an7583_gpio10_pins[] = { 12 };
-static const int an7583_gpio11_pins[] = { 13 };
-static const int an7583_gpio12_pins[] = { 14 };
-static const int an7583_gpio13_pins[] = { 15 };
-static const int an7583_gpio14_pins[] = { 16 };
-static const int an7583_gpio15_pins[] = { 17 };
-static const int an7583_gpio16_pins[] = { 18 };
-static const int an7583_gpio17_pins[] = { 19 };
-static const int an7583_gpio18_pins[] = { 20 };
-static const int an7583_gpio19_pins[] = { 21 };
-static const int an7583_gpio20_pins[] = { 22 };
-static const int an7583_gpio21_pins[] = { 23 };
-static const int an7583_gpio22_pins[] = { 24 };
-static const int an7583_gpio23_pins[] = { 25 };
-static const int an7583_gpio24_pins[] = { 26 };
-static const int an7583_gpio25_pins[] = { 27 };
-static const int an7583_gpio26_pins[] = { 28 };
-static const int an7583_gpio27_pins[] = { 29 };
-static const int an7583_gpio28_pins[] = { 30 };
-static const int an7583_gpio29_pins[] = { 31 };
-static const int an7583_gpio30_pins[] = { 32 };
-static const int an7583_gpio31_pins[] = { 33 };
-static const int an7583_gpio32_pins[] = { 34 };
-static const int an7583_gpio33_pins[] = { 35 };
-static const int an7583_gpio34_pins[] = { 36 };
-static const int an7583_gpio35_pins[] = { 37 };
-static const int an7583_gpio36_pins[] = { 38 };
-static const int an7583_gpio37_pins[] = { 39 };
-static const int an7583_gpio38_pins[] = { 40 };
-static const int an7583_gpio39_pins[] = { 41 };
-static const int an7583_gpio40_pins[] = { 42 };
-static const int an7583_gpio41_pins[] = { 43 };
-static const int an7583_gpio42_pins[] = { 44 };
-static const int an7583_gpio43_pins[] = { 45 };
-static const int an7583_gpio44_pins[] = { 46 };
-static const int an7583_gpio45_pins[] = { 47 };
-static const int an7583_gpio46_pins[] = { 48 };
-static const int an7583_gpio47_pins[] = { 49 };
-static const int an7583_gpio48_pins[] = { 50 };
-static const int an7583_gpio49_pins[] = { 51 };
-static const int an7583_gpio50_pins[] = { 52 };
-static const int an7583_gpio51_pins[] = { 53 };
-static const int an7583_gpio52_pins[] = { 54 };
-static const int an7583_pcie_reset0_pins[] = { 51 };
-static const int an7583_pcie_reset1_pins[] = { 52 };
-
-static const struct pingroup an7583_pinctrl_groups[] = {
- PINCTRL_PIN_GROUP("pon", an7583_pon),
- PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
- PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
- PINCTRL_PIN_GROUP("sipo", an7583_sipo),
- PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
- PINCTRL_PIN_GROUP("mdio", an7583_mdio),
- PINCTRL_PIN_GROUP("uart2", an7583_uart2),
- PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
- PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
- PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
- PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
- PINCTRL_PIN_GROUP("uart4", an7583_uart4),
- PINCTRL_PIN_GROUP("uart5", an7583_uart5),
- PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
- PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
- PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
- PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
- PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
- PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
- PINCTRL_PIN_GROUP("spi", an7583_spi),
- PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
- PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
- PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
- PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
- PINCTRL_PIN_GROUP("emmc", an7583_emmc),
- PINCTRL_PIN_GROUP("pnand", an7583_pnand),
- PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
- PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
- PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
- PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
- PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
- PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
- PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
- PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
- PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
- PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
- PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
- PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
- PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
- PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
- PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
- PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
- PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
- PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
- PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
- PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
- PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
- PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
- PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
- PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
- PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
- PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
- PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
- PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
- PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
- PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
- PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
- PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
- PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
- PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
- PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
- PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
- PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
- PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
- PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
- PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
- PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
- PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
- PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
- PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
- PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
- PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
- PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
- PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
- PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
- PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
- PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
- PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
- PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
- PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
- PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
+static const int gpio0_pins[] = { 2 };
+static const int gpio1_pins[] = { 3 };
+static const int gpio2_pins[] = { 4 };
+static const int gpio3_pins[] = { 5 };
+static const int gpio4_pins[] = { 6 };
+static const int gpio5_pins[] = { 7 };
+static const int gpio6_pins[] = { 8 };
+static const int gpio7_pins[] = { 9 };
+static const int gpio8_pins[] = { 10 };
+static const int gpio9_pins[] = { 11 };
+static const int gpio10_pins[] = { 12 };
+static const int gpio11_pins[] = { 13 };
+static const int gpio12_pins[] = { 14 };
+static const int gpio13_pins[] = { 15 };
+static const int gpio14_pins[] = { 16 };
+static const int gpio15_pins[] = { 17 };
+static const int gpio16_pins[] = { 18 };
+static const int gpio17_pins[] = { 19 };
+static const int gpio18_pins[] = { 20 };
+static const int gpio19_pins[] = { 21 };
+static const int gpio20_pins[] = { 22 };
+static const int gpio21_pins[] = { 23 };
+static const int gpio22_pins[] = { 24 };
+static const int gpio23_pins[] = { 25 };
+static const int gpio24_pins[] = { 26 };
+static const int gpio25_pins[] = { 27 };
+static const int gpio26_pins[] = { 28 };
+static const int gpio27_pins[] = { 29 };
+static const int gpio28_pins[] = { 30 };
+static const int gpio29_pins[] = { 31 };
+static const int gpio30_pins[] = { 32 };
+static const int gpio31_pins[] = { 33 };
+static const int gpio32_pins[] = { 34 };
+static const int gpio33_pins[] = { 35 };
+static const int gpio34_pins[] = { 36 };
+static const int gpio35_pins[] = { 37 };
+static const int gpio36_pins[] = { 38 };
+static const int gpio37_pins[] = { 39 };
+static const int gpio38_pins[] = { 40 };
+static const int gpio39_pins[] = { 41 };
+static const int gpio40_pins[] = { 42 };
+static const int gpio41_pins[] = { 43 };
+static const int gpio42_pins[] = { 44 };
+static const int gpio43_pins[] = { 45 };
+static const int gpio44_pins[] = { 46 };
+static const int gpio45_pins[] = { 47 };
+static const int gpio46_pins[] = { 48 };
+static const int gpio47_pins[] = { 49 };
+static const int gpio48_pins[] = { 50 };
+static const int gpio49_pins[] = { 51 };
+static const int gpio50_pins[] = { 52 };
+static const int gpio51_pins[] = { 53 };
+static const int gpio52_pins[] = { 54 };
+static const int pcie_reset0_pins[] = { 51 };
+static const int pcie_reset1_pins[] = { 52 };
+
+static const struct pingroup pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", mdio),
+ PINCTRL_PIN_GROUP("uart2", uart2),
+ PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts),
+ PINCTRL_PIN_GROUP("hsuart", hsuart),
+ PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
+ PINCTRL_PIN_GROUP("npu_uart", npu_uart),
+ PINCTRL_PIN_GROUP("uart4", uart4),
+ PINCTRL_PIN_GROUP("uart5", uart5),
+ PINCTRL_PIN_GROUP("i2c0", i2c0),
+ PINCTRL_PIN_GROUP("i2c1", i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+ PINCTRL_PIN_GROUP("pcm1", pcm1),
+ PINCTRL_PIN_GROUP("pcm2", pcm2),
+ PINCTRL_PIN_GROUP("spi", spi),
+ PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("emmc", emmc),
+ PINCTRL_PIN_GROUP("pnand", pnand),
+ PINCTRL_PIN_GROUP("gpio0", gpio0),
+ PINCTRL_PIN_GROUP("gpio1", gpio1),
+ PINCTRL_PIN_GROUP("gpio2", gpio2),
+ PINCTRL_PIN_GROUP("gpio3", gpio3),
+ PINCTRL_PIN_GROUP("gpio4", gpio4),
+ PINCTRL_PIN_GROUP("gpio5", gpio5),
+ PINCTRL_PIN_GROUP("gpio6", gpio6),
+ PINCTRL_PIN_GROUP("gpio7", gpio7),
+ PINCTRL_PIN_GROUP("gpio8", gpio8),
+ PINCTRL_PIN_GROUP("gpio9", gpio9),
+ PINCTRL_PIN_GROUP("gpio10", gpio10),
+ PINCTRL_PIN_GROUP("gpio11", gpio11),
+ PINCTRL_PIN_GROUP("gpio12", gpio12),
+ PINCTRL_PIN_GROUP("gpio13", gpio13),
+ PINCTRL_PIN_GROUP("gpio14", gpio14),
+ PINCTRL_PIN_GROUP("gpio15", gpio15),
+ PINCTRL_PIN_GROUP("gpio16", gpio16),
+ PINCTRL_PIN_GROUP("gpio17", gpio17),
+ PINCTRL_PIN_GROUP("gpio18", gpio18),
+ PINCTRL_PIN_GROUP("gpio19", gpio19),
+ PINCTRL_PIN_GROUP("gpio20", gpio20),
+ PINCTRL_PIN_GROUP("gpio21", gpio21),
+ PINCTRL_PIN_GROUP("gpio22", gpio22),
+ PINCTRL_PIN_GROUP("gpio23", gpio23),
+ PINCTRL_PIN_GROUP("gpio24", gpio24),
+ PINCTRL_PIN_GROUP("gpio25", gpio25),
+ PINCTRL_PIN_GROUP("gpio26", gpio26),
+ PINCTRL_PIN_GROUP("gpio27", gpio27),
+ PINCTRL_PIN_GROUP("gpio28", gpio28),
+ PINCTRL_PIN_GROUP("gpio29", gpio29),
+ PINCTRL_PIN_GROUP("gpio30", gpio30),
+ PINCTRL_PIN_GROUP("gpio31", gpio31),
+ PINCTRL_PIN_GROUP("gpio32", gpio32),
+ PINCTRL_PIN_GROUP("gpio33", gpio33),
+ PINCTRL_PIN_GROUP("gpio34", gpio34),
+ PINCTRL_PIN_GROUP("gpio35", gpio35),
+ PINCTRL_PIN_GROUP("gpio36", gpio36),
+ PINCTRL_PIN_GROUP("gpio37", gpio37),
+ PINCTRL_PIN_GROUP("gpio38", gpio38),
+ PINCTRL_PIN_GROUP("gpio39", gpio39),
+ PINCTRL_PIN_GROUP("gpio40", gpio40),
+ PINCTRL_PIN_GROUP("gpio41", gpio41),
+ PINCTRL_PIN_GROUP("gpio42", gpio42),
+ PINCTRL_PIN_GROUP("gpio43", gpio43),
+ PINCTRL_PIN_GROUP("gpio44", gpio44),
+ PINCTRL_PIN_GROUP("gpio45", gpio45),
+ PINCTRL_PIN_GROUP("gpio46", gpio46),
+ PINCTRL_PIN_GROUP("gpio47", gpio47),
+ PINCTRL_PIN_GROUP("gpio48", gpio48),
+ PINCTRL_PIN_GROUP("gpio49", gpio49),
+ PINCTRL_PIN_GROUP("gpio50", gpio50),
+ PINCTRL_PIN_GROUP("gpio51", gpio51),
+ PINCTRL_PIN_GROUP("gpio52", gpio52),
+ PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
};
static const char *const pon_groups[] = { "pon" };
@@ -566,7 +566,7 @@ static const char *const tod_1pps_groups[] = {
"pon_tod_1pps", "gsw_tod_1pps"
};
static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
-static const char *const an7583_mdio_groups[] = { "mdio" };
+static const char *const mdio_groups[] = { "mdio" };
static const char *const uart_groups[] = {
"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
"uart4", "uart5"
@@ -574,20 +574,20 @@ static const char *const uart_groups[] = {
static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
static const char *const pcm_groups[] = { "pcm1", "pcm2" };
static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
-static const char *const an7583_pcm_spi_groups[] = {
+static const char *const pcm_spi_groups[] = {
"pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
};
static const char *const emmc_groups[] = { "emmc" };
static const char *const pnand_groups[] = { "pnand" };
-static const char *const an7583_gpio_groups[] = {
+static const char *const gpio_groups[] = {
"gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
"gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
"gpio49", "gpio50", "gpio51", "gpio52"
};
-static const char *const an7583_pcie_reset_groups[] = {
+static const char *const pcie_reset_groups[] = {
"pcie_reset0", "pcie_reset1"
};
-static const char *const an7583_pwm_groups[] = {
+static const char *const pwm_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
@@ -597,28 +597,28 @@ static const char *const an7583_pwm_groups[] = {
"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
"gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
};
-static const char *const an7583_phy1_led0_groups[] = {
+static const char *const phy1_led0_groups[] = {
"gpio1", "gpio2", "gpio3", "gpio4"
};
-static const char *const an7583_phy2_led0_groups[] = {
+static const char *const phy2_led0_groups[] = {
"gpio1", "gpio2", "gpio3", "gpio4"
};
-static const char *const an7583_phy3_led0_groups[] = {
+static const char *const phy3_led0_groups[] = {
"gpio1", "gpio2", "gpio3", "gpio4"
};
-static const char *const an7583_phy4_led0_groups[] = {
+static const char *const phy4_led0_groups[] = {
"gpio1", "gpio2", "gpio3", "gpio4"
};
-static const char *const an7583_phy1_led1_groups[] = {
+static const char *const phy1_led1_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11"
};
-static const char *const an7583_phy2_led1_groups[] = {
+static const char *const phy2_led1_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11"
};
-static const char *const an7583_phy3_led1_groups[] = {
+static const char *const phy3_led1_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11"
};
-static const char *const an7583_phy4_led1_groups[] = {
+static const char *const phy4_led1_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11"
};
@@ -679,7 +679,7 @@ static const struct airoha_pinctrl_func_group sipo_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
{
.name = "mdio",
.regmap[0] = {
@@ -850,7 +850,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
{
.name = "pcm_spi",
.regmap[0] = {
@@ -892,8 +892,8 @@ static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
.regmap[0] = {
AIROHA_FUNC_MUX,
REG_GPIO_SPI_CS1_MODE,
- AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
- AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
+ GPIO_PCM_SPI_CS2_MODE_MASK,
+ GPIO_PCM_SPI_CS2_MODE_MASK
},
.regmap_size = 1,
}, {
@@ -943,37 +943,37 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
- AN7583_I2C0_SCL_GPIO_MODE_MASK),
+ I2C0_SCL_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
- AN7583_I2C0_SDA_GPIO_MODE_MASK),
+ I2C0_SDA_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
- AN7583_I2C1_SCL_GPIO_MODE_MASK),
+ I2C1_SCL_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
- AN7583_I2C1_SDA_GPIO_MODE_MASK),
+ I2C1_SDA_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
- AN7583_SPI_CLK_GPIO_MODE_MASK),
+ SPI_CLK_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
- AN7583_SPI_CS_GPIO_MODE_MASK),
+ SPI_CS_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
- AN7583_SPI_MOSI_GPIO_MODE_MASK),
+ SPI_MOSI_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
- AN7583_SPI_MISO_GPIO_MODE_MASK),
+ SPI_MISO_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
- AN7583_UART_TXD_GPIO_MODE_MASK),
+ UART_TXD_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
- AN7583_UART_RXD_GPIO_MODE_MASK),
+ UART_RXD_GPIO_MODE_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
GPIO_PCIE_RESET0_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
GPIO_PCIE_RESET1_MASK),
AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
- AN7583_MDC_0_GPIO_MODE_MASK),
- AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
+ MDC_0_GPIO_MODE_MASK),
+ AIROHA_PINCTRL_GPIO("gpio52", MDIO_0_GPIO_MODE_MASK),
};
-static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
{
.name = "pcie_reset0",
.regmap[0] = {
@@ -995,7 +995,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
@@ -1032,34 +1032,34 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
- AN7583_I2C0_SCL_GPIO_MODE_MASK),
+ I2C0_SCL_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
- AN7583_I2C0_SDA_GPIO_MODE_MASK),
+ I2C0_SDA_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
- AN7583_I2C1_SCL_GPIO_MODE_MASK),
+ I2C1_SCL_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
- AN7583_I2C1_SDA_GPIO_MODE_MASK),
+ I2C1_SDA_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
- AN7583_SPI_CLK_GPIO_MODE_MASK),
+ SPI_CLK_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
- AN7583_SPI_CS_GPIO_MODE_MASK),
+ SPI_CS_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
- AN7583_SPI_MOSI_GPIO_MODE_MASK),
+ SPI_MOSI_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
- AN7583_SPI_MISO_GPIO_MODE_MASK),
+ SPI_MISO_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
- AN7583_UART_TXD_GPIO_MODE_MASK),
+ UART_TXD_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
- AN7583_UART_RXD_GPIO_MODE_MASK),
+ UART_RXD_GPIO_MODE_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
GPIO_PCIE_RESET0_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
GPIO_PCIE_RESET1_MASK),
AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
- AN7583_MDC_0_GPIO_MODE_MASK),
+ MDC_0_GPIO_MODE_MASK),
};
-static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1070,7 +1070,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
-static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1081,7 +1081,7 @@ static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
-static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1092,7 +1092,7 @@ static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
-static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -1103,7 +1103,7 @@ static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
-static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1114,7 +1114,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
-static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1125,7 +1125,7 @@ static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
-static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1136,7 +1136,7 @@ static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
-static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -1147,32 +1147,32 @@ static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
-static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("pon", pon),
PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
PINCTRL_FUNC_DESC("sipo", sipo),
- PINCTRL_FUNC_DESC("mdio", an7583_mdio),
+ PINCTRL_FUNC_DESC("mdio", mdio),
PINCTRL_FUNC_DESC("uart", uart),
PINCTRL_FUNC_DESC("jtag", jtag),
PINCTRL_FUNC_DESC("pcm", pcm),
PINCTRL_FUNC_DESC("spi", spi),
- PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
+ PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
PINCTRL_FUNC_DESC("emmc", emmc),
PINCTRL_FUNC_DESC("pnand", pnand),
- PINCTRL_FUNC_DESC("gpio", an7583_gpio),
- PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
- PINCTRL_FUNC_DESC("pwm", an7583_pwm),
- PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
- PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
- PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
- PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
- PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
- PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
- PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
- PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
+ PINCTRL_FUNC_DESC("gpio", gpio),
+ PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+ PINCTRL_FUNC_DESC("pwm", pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+ PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+ PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+ PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
@@ -1214,8 +1214,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, I2C1_SCL_PU_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, I2C1_SDA_PU_MASK),
PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
@@ -1224,11 +1224,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, MDC_0_PU_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, MDIO_0_PU_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
@@ -1270,8 +1270,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, I2C1_SCL_PD_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, I2C1_SDA_PD_MASK),
PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
@@ -1280,11 +1280,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, MDC_0_PD_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, MDIO_0_PD_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
@@ -1326,8 +1326,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, I2C1_SCL_E2_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, I2C1_SDA_E2_MASK),
PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
@@ -1336,11 +1336,11 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, MDC_0_E2_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, MDIO_0_E2_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
@@ -1382,8 +1382,8 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
- PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
- PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
+ PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, I2C1_SCL_E4_MASK),
+ PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, I2C1_SDA_E4_MASK),
PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
@@ -1392,50 +1392,50 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
- PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
- PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
+ PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, MDC_0_E4_MASK),
+ PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, MDIO_0_E4_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
};
-static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
.pinctrl_name = KBUILD_MODNAME,
.pinctrl_owner = THIS_MODULE,
- .pins = an7583_pinctrl_pins,
- .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
- .grps = an7583_pinctrl_groups,
- .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
- .funcs = an7583_pinctrl_funcs,
- .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
+ .pins = pinctrl_pins,
+ .num_pins = ARRAY_SIZE(pinctrl_pins),
+ .grps = pinctrl_groups,
+ .num_grps = ARRAY_SIZE(pinctrl_groups),
+ .funcs = pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(pinctrl_funcs),
.confs_info = {
[AIROHA_PINCTRL_CONFS_PULLUP] = {
- .confs = an7583_pinctrl_pullup_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
+ .confs = pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
},
[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
- .confs = an7583_pinctrl_pulldown_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
+ .confs = pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
- .confs = an7583_pinctrl_drive_e2_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
+ .confs = pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
- .confs = an7583_pinctrl_drive_e4_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
+ .confs = pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
},
[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
- .confs = an7583_pinctrl_pcie_rst_od_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
+ .confs = pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
},
},
};
static const struct of_device_id airoha_pinctrl_of_match[] = {
- { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
+ { .compatible = "airoha,an7583-pinctrl", .data = &pinctrl_match_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
--
2.53.0
^ permalink raw reply related
* [PATCH v6 11/17] pinctrl: airoha: an7583: rename registers to match its an7583 names
From: Mikhail Kshevetskiy @ 2026-06-28 14:37 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260628143733.273651-1-mikhail.kshevetskiy@iopsys.eu>
In the an7581 case the register at 0x1FA20214 is called RG_GPIO_2ND_I2C_MODE.
The same register in the an7583 case is called RG_SW_TOD_1PPS_MODE.
Let's rename this register to avoid potential confuse.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/pinctrl-an7583.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 637b9377ff8f..b0b1dbbb4d76 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -8,7 +8,7 @@
#include "airoha-common.h"
/* MUX */
-#define REG_GPIO_2ND_I2C_MODE 0x0214
+#define REG_SW_TOD_1PPS_MODE 0x0214
#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
@@ -302,7 +302,7 @@
.name = (gpio), \
.regmap[0] = { \
AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
+ REG_SW_TOD_1PPS_MODE, \
(mux_val), \
(mux_val), \
}, \
@@ -320,7 +320,7 @@
.name = (gpio), \
.regmap[0] = { \
AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
+ REG_SW_TOD_1PPS_MODE, \
(mux_val), \
(mux_val), \
}, \
@@ -640,7 +640,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
.name = "pon_tod_1pps",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
+ REG_SW_TOD_1PPS_MODE,
PON_TOD_1PPS_MODE_MASK,
PON_TOD_1PPS_MODE_MASK
},
@@ -649,7 +649,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
.name = "gsw_tod_1pps",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
+ REG_SW_TOD_1PPS_MODE,
GSW_TOD_1PPS_MODE_MASK,
GSW_TOD_1PPS_MODE_MASK
},
--
2.53.0
^ permalink raw reply related
* [PATCH v6 12/17] pinctrl: airoha: an7583: add support for npu_uart pinmux
From: Mikhail Kshevetskiy @ 2026-06-28 14:37 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260628143733.273651-1-mikhail.kshevetskiy@iopsys.eu>
Add support for uart pin function for npu_uart pin group.
Also update device tree binding schema.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
.../bindings/pinctrl/airoha,an7583-pinctrl.yaml | 2 +-
drivers/pinctrl/airoha/pinctrl-an7583.c | 12 +++++++++++-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
index bedcb6374f1a..0a217429b2cb 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
@@ -115,7 +115,7 @@ patternProperties:
groups:
items:
enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts,
- uart4, uart5]
+ uart4, uart5, npu_uart]
maxItems: 2
- if:
properties:
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index b0b1dbbb4d76..9b5c7ea5e547 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -68,6 +68,7 @@
#define REG_NPU_UART_EN 0x0224
#define JTAG_UDI_EN_MASK BIT(4)
#define JTAG_DFD_EN_MASK BIT(3)
+#define NPU_UART_EN_MASK BIT(2)
#define REG_FORCE_GPIO_EN 0x0228
#define FORCE_GPIO_EN(n) BIT(n)
@@ -569,7 +570,7 @@ static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
static const char *const mdio_groups[] = { "mdio" };
static const char *const uart_groups[] = {
"uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
- "uart4", "uart5"
+ "uart4", "uart5", "npu_uart"
};
static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
static const char *const pcm_groups[] = { "pcm1", "pcm2" };
@@ -754,6 +755,15 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
GPIO_UART5_MODE_MASK
},
.regmap_size = 1,
+ }, {
+ .name = "npu_uart",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ NPU_UART_EN_MASK,
+ NPU_UART_EN_MASK
+ },
+ .regmap_size = 1,
},
};
--
2.53.0
^ permalink raw reply related
* [PATCH v6 13/17] pinctrl: airoha: an7583: add support for pon_alt pinmux
From: Mikhail Kshevetskiy @ 2026-06-28 14:37 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260628143733.273651-1-mikhail.kshevetskiy@iopsys.eu>
Add support for pon pin function for pon_alt pin group.
Also update device tree binding schema.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
.../bindings/pinctrl/airoha,an7583-pinctrl.yaml | 2 +-
drivers/pinctrl/airoha/pinctrl-an7583.c | 16 ++++++++++++++--
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
index 0a217429b2cb..7deb48db52c3 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
@@ -81,7 +81,7 @@ patternProperties:
then:
properties:
groups:
- enum: [pon]
+ enum: [pon, pon_alt]
- if:
properties:
function:
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 9b5c7ea5e547..7e94dcb3b61a 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -38,6 +38,7 @@
#define GPIO_SPI_CS1_MODE_MASK BIT(0)
#define REG_GPIO_PON_MODE 0x021c
+#define GPIO_PON_ALT_MODE_MASK BIT(27)
#define MDIO_0_GPIO_MODE_MASK BIT(26)
#define MDC_0_GPIO_MODE_MASK BIT(25)
#define UART_RXD_GPIO_MODE_MASK BIT(24)
@@ -391,6 +392,7 @@ static struct pinctrl_pin_desc pinctrl_pins[] = {
};
static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 };
static const int pon_tod_1pps_pins[] = { 32 };
static const int gsw_tod_1pps_pins[] = { 32 };
static const int sipo_pins[] = { 34, 35 };
@@ -479,6 +481,7 @@ static const int pcie_reset1_pins[] = { 52 };
static const struct pingroup pinctrl_groups[] = {
PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("pon_alt", pon_alt),
PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
PINCTRL_PIN_GROUP("sipo", sipo),
@@ -562,7 +565,7 @@ static const struct pingroup pinctrl_groups[] = {
PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
};
-static const char *const pon_groups[] = { "pon" };
+static const char *const pon_groups[] = { "pon", "pon_alt" };
static const char *const tod_1pps_groups[] = {
"pon_tod_1pps", "gsw_tod_1pps"
};
@@ -629,10 +632,19 @@ static const struct airoha_pinctrl_func_group pon_func_group[] = {
.regmap[0] = {
AIROHA_FUNC_MUX,
REG_GPIO_PON_MODE,
- GPIO_PON_MODE_MASK,
+ GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK,
GPIO_PON_MODE_MASK
},
.regmap_size = 1,
+ }, {
+ .name = "pon_alt",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK,
+ GPIO_PON_ALT_MODE_MASK
+ },
+ .regmap_size = 1,
},
};
--
2.53.0
^ permalink raw reply related
* [PATCH v6 14/17] pinctrl: airoha: an7583: add support for olt pinmux
From: Mikhail Kshevetskiy @ 2026-06-28 14:37 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260628143733.273651-1-mikhail.kshevetskiy@iopsys.eu>
Add support for olt pin function for olt pin group.
Also update device tree binding schema.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
.../pinctrl/airoha,an7583-pinctrl.yaml | 10 +++++++++-
drivers/pinctrl/airoha/pinctrl-an7583.c | 18 ++++++++++++++++++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
index 7deb48db52c3..f016e0da65a5 100644
--- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
@@ -60,7 +60,7 @@ patternProperties:
function:
description:
A string containing the name of the function to mux to the group.
- enum: [pon, tod_1pps, sipo, mdio, uart, jtag, pcm, spi,
+ enum: [pon, olt, tod_1pps, sipo, mdio, uart, jtag, pcm, spi,
pcm_spi, emmc, pnand, gpio, pcie_reset, pwm, phy1_led0,
phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
phy3_led1, phy4_led1]
@@ -82,6 +82,14 @@ patternProperties:
properties:
groups:
enum: [pon, pon_alt]
+ - if:
+ properties:
+ function:
+ const: olt
+ then:
+ properties:
+ groups:
+ enum: [olt]
- if:
properties:
function:
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 7e94dcb3b61a..74f93327d41a 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -53,6 +53,7 @@
#define I2C0_SCL_GPIO_MODE_MASK BIT(15)
#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
+#define GPIO_OLT_MODE_MASK BIT(12)
#define SIPO_RCLK_MODE_MASK BIT(11)
#define GPIO_PCIE_RESET1_MASK BIT(10)
#define GPIO_PCIE_RESET0_MASK BIT(9)
@@ -393,6 +394,7 @@ static struct pinctrl_pin_desc pinctrl_pins[] = {
static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 };
+static const int olt_pins[] = { 36, 37, 38, 39, 40 };
static const int pon_tod_1pps_pins[] = { 32 };
static const int gsw_tod_1pps_pins[] = { 32 };
static const int sipo_pins[] = { 34, 35 };
@@ -482,6 +484,7 @@ static const int pcie_reset1_pins[] = { 52 };
static const struct pingroup pinctrl_groups[] = {
PINCTRL_PIN_GROUP("pon", pon),
PINCTRL_PIN_GROUP("pon_alt", pon_alt),
+ PINCTRL_PIN_GROUP("olt", olt),
PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
PINCTRL_PIN_GROUP("sipo", sipo),
@@ -566,6 +569,7 @@ static const struct pingroup pinctrl_groups[] = {
};
static const char *const pon_groups[] = { "pon", "pon_alt" };
+static const char *const olt_groups[] = { "olt" };
static const char *const tod_1pps_groups[] = {
"pon_tod_1pps", "gsw_tod_1pps"
};
@@ -648,6 +652,19 @@ static const struct airoha_pinctrl_func_group pon_func_group[] = {
},
};
+static const struct airoha_pinctrl_func_group olt_func_group[] = {
+ {
+ .name = "olt",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_OLT_MODE_MASK,
+ GPIO_OLT_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
{
.name = "pon_tod_1pps",
@@ -1171,6 +1188,7 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
static const struct airoha_pinctrl_func pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("pon", pon),
+ PINCTRL_FUNC_DESC("olt", olt),
PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
PINCTRL_FUNC_DESC("sipo", sipo),
PINCTRL_FUNC_DESC("mdio", mdio),
--
2.53.0
^ permalink raw reply related
* [PATCH v6 15/17] pinctrl: airoha: add support of en7523 SoC
From: Mikhail Kshevetskiy @ 2026-06-28 14:37 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260628143733.273651-1-mikhail.kshevetskiy@iopsys.eu>
This patch adds support of Airoha en7523 SoC pin controller.
Also it adds corresponding device tree binding schema.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
.../pinctrl/airoha,en7523-pinctrl.yaml | 375 ++++++
drivers/pinctrl/airoha/Kconfig | 6 +
drivers/pinctrl/airoha/Makefile | 1 +
drivers/pinctrl/airoha/pinctrl-en7523.c | 1124 +++++++++++++++++
4 files changed, 1506 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml
create mode 100644 drivers/pinctrl/airoha/pinctrl-en7523.c
diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml
new file mode 100644
index 000000000000..270899e51e3c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml
@@ -0,0 +1,375 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/airoha,en7523-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7523 Pin Controller
+
+maintainers:
+ - Lorenzo Bianconi <lorenzo@kernel.org>
+
+description:
+ The Airoha's EN7523 Pin controller is used to control SoC pins.
+
+properties:
+ compatible:
+ const: airoha,en7523-pinctrl
+
+ interrupts:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+ - interrupts
+ - gpio-controller
+ - "#gpio-cells"
+ - interrupt-controller
+ - "#interrupt-cells"
+
+patternProperties:
+ '-pins$':
+ type: object
+
+ patternProperties:
+ '^mux(-|$)':
+ type: object
+
+ description:
+ pinmux configuration nodes.
+
+ $ref: /schemas/pinctrl/pinmux-node.yaml
+
+ properties:
+ function:
+ description:
+ A string containing the name of the function to mux to the group.
+ enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
+ pcm_spi, i2s, gpio, pcie_reset, pwm, phy1_led0,
+ phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
+ phy3_led1, phy4_led1]
+
+ groups:
+ description:
+ An array of strings. Each string contains the name of a group.
+
+ required:
+ - function
+ - groups
+
+ allOf:
+ - if:
+ properties:
+ function:
+ const: pon
+ then:
+ properties:
+ groups:
+ enum: [pon]
+ - if:
+ properties:
+ function:
+ const: tod_1pps
+ then:
+ properties:
+ groups:
+ enum: [pon_tod_1pps, gsw_tod_1pps]
+ - if:
+ properties:
+ function:
+ const: sipo
+ then:
+ properties:
+ groups:
+ enum: [sipo, sipo_rclk]
+ - if:
+ properties:
+ function:
+ const: mdio
+ then:
+ properties:
+ groups:
+ enum: [mdio]
+ - if:
+ properties:
+ function:
+ const: uart
+ then:
+ properties:
+ groups:
+ items:
+ enum: [uart2, npu_uart]
+ maxItems: 2
+ - if:
+ properties:
+ function:
+ const: i2c
+ then:
+ properties:
+ groups:
+ enum: [i2c1]
+ - if:
+ properties:
+ function:
+ const: jtag
+ then:
+ properties:
+ groups:
+ enum: [jtag_udi, jtag_dfd]
+ - if:
+ properties:
+ function:
+ const: pcm
+ then:
+ properties:
+ groups:
+ enum: [pcm1, pcm2]
+ - if:
+ properties:
+ function:
+ const: spi
+ then:
+ properties:
+ groups:
+ items:
+ enum: [spi_quad, spi_cs1]
+ maxItems: 2
+ - if:
+ properties:
+ function:
+ const: pcm_spi
+ then:
+ properties:
+ groups:
+ items:
+ enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1,
+ pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3,
+ pcm_spi_cs4]
+ maxItems: 7
+ - if:
+ properties:
+ function:
+ const: i2s
+ then:
+ properties:
+ groups:
+ enum: [i2s]
+ - if:
+ properties:
+ function:
+ const: gpio
+ then:
+ properties:
+ groups:
+ enum: [gpio28, gpio29]
+ - if:
+ properties:
+ function:
+ const: pcie_reset
+ then:
+ properties:
+ groups:
+ enum: [pcie_reset0, pcie_reset1]
+ - if:
+ properties:
+ function:
+ const: pwm
+ then:
+ properties:
+ groups:
+ enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6,
+ gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13,
+ gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+ gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
+ gpio26, gpio27, gpio28, gpio29]
+ - if:
+ properties:
+ function:
+ const: phy1_led0
+ then:
+ properties:
+ groups:
+ enum: [gpio22, gpio23, gpio24, gpio25]
+ - if:
+ properties:
+ function:
+ const: phy2_led0
+ then:
+ properties:
+ groups:
+ enum: [gpio22, gpio23, gpio24, gpio25]
+ - if:
+ properties:
+ function:
+ const: phy3_led0
+ then:
+ properties:
+ groups:
+ enum: [gpio22, gpio23, gpio24, gpio25]
+ - if:
+ properties:
+ function:
+ const: phy4_led0
+ then:
+ properties:
+ groups:
+ enum: [gpio22, gpio23, gpio24, gpio25]
+ - if:
+ properties:
+ function:
+ const: phy1_led1
+ then:
+ properties:
+ groups:
+ enum: [gpio7, gpio6, gpio5, gpio4]
+ - if:
+ properties:
+ function:
+ const: phy2_led1
+ then:
+ properties:
+ groups:
+ enum: [gpio7, gpio6, gpio5, gpio4]
+ - if:
+ properties:
+ function:
+ const: phy3_led1
+ then:
+ properties:
+ groups:
+ enum: [gpio7, gpio6, gpio5, gpio4]
+ - if:
+ properties:
+ function:
+ const: phy4_led1
+ then:
+ properties:
+ groups:
+ enum: [gpio7, gpio6, gpio5, gpio4]
+
+ additionalProperties: false
+
+ '^conf(-|$)':
+ type: object
+
+ description:
+ pinconf configuration nodes.
+
+ $ref: /schemas/pinctrl/pincfg-node.yaml
+
+ properties:
+ pins:
+ description:
+ An array of strings. Each string contains the name of a pin.
+ items:
+ enum: [i2c_sda, i2c_scl, spi_cs0, spi_clk, spi_mosi, spi_miso,
+ uart1_txd, uart1_rxd, gpio0, gpio1, gpio2, gpio3, gpio4,
+ gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12,
+ gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
+ gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26,
+ gpio27, pcie_reset0, pcie_reset1]
+ minItems: 1
+ maxItems: 38
+
+ bias-disable: true
+
+ bias-pull-up: true
+
+ bias-pull-down: true
+
+ input-enable: true
+
+ output-enable: true
+
+ output-low: true
+
+ output-high: true
+
+ drive-open-drain: true
+
+ drive-strength:
+ description:
+ Selects the drive strength for MIO pins, in mA.
+ enum: [2, 4, 6, 8]
+
+ required:
+ - pins
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pinctrl {
+ compatible = "airoha,en7521-pinctrl";
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ pcie1-rst-pins {
+ conf {
+ pins = "pcie_reset1";
+ drive-open-drain = <1>;
+ };
+ };
+
+ pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "gpio18";
+ };
+ };
+
+ spi-pins {
+ mux {
+ function = "spi";
+ groups = "spi_quad", "spi_cs1";
+ };
+ };
+
+ uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2";
+ };
+ };
+
+ mdio-pins {
+ mux {
+ function = "mdio";
+ groups = "mdio";
+ };
+
+ conf {
+ pins = "gpio2";
+ output-enable;
+ };
+ };
+ };
diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
index 08038a5b11c6..159b4496f64a 100644
--- a/drivers/pinctrl/airoha/Kconfig
+++ b/drivers/pinctrl/airoha/Kconfig
@@ -15,6 +15,7 @@ config PINCTRL_AIROHA
select REGMAP_MMIO
imply PINCTRL_AIROHA_AN7581
imply PINCTRL_AIROHA_AN7583
+ imply PINCTRL_AIROHA_EN7523
help
Say yes here to support pin controller and gpio driver
on Airoha SoC.
@@ -29,4 +30,9 @@ config PINCTRL_AIROHA_AN7583
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_AIROHA
+config PINCTRL_AIROHA_EN7523
+ tristate "EN7523 pinctrl"
+ depends on ARM || COMPILE_TEST
+ depends on PINCTRL_AIROHA
+
endmenu
diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
index cfd68c45ae0f..8b9202321ba8 100644
--- a/drivers/pinctrl/airoha/Makefile
+++ b/drivers/pinctrl/airoha/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
# SoC drivers
obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o
obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o
+obj-$(CONFIG_PINCTRL_AIROHA_EN7523) += pinctrl-en7523.o
diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c
new file mode 100644
index 000000000000..7f434c9bce92
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
@@ -0,0 +1,1124 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ * Author: Matheus Sampaio Queiroga <srherobrine20@gmail.com>
+ * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+ */
+#include "airoha-common.h"
+
+/* MUX */
+#define REG_GPIO_2ND_I2C_MODE 0x0210
+#define GPIO_I2S_MODE_MASK BIT(12)
+#define GPIO_I2C_SLAVE_MODE_MODE BIT(11)
+#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
+#define PON_TOD_1PPS_MODE_MASK BIT(2)
+#define GSW_TOD_1PPS_MODE_MASK BIT(1)
+#define GPIO_2ND_I2C_MODE_MASK BIT(0)
+
+#define REG_GPIO_SPI_CS1_MODE 0x0214
+#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
+#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
+#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK BIT(16)
+#define GPIO_PCM2_MODE_MASK BIT(13)
+#define GPIO_PCM1_MODE_MASK BIT(12)
+#define GPIO_PCM_INT_MODE_MASK BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
+#define GPIO_SPI_CS1_MODE_MASK BIT(0)
+
+#define REG_GPIO_PON_MODE 0x0218
+#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
+#define SIPO_RCLK_MODE_MASK BIT(11)
+#define GPIO_PCIE_RESET1_MASK BIT(10)
+#define GPIO_PCIE_RESET0_MASK BIT(9)
+#define GPIO_UART2_MODE_MASK BIT(3)
+#define GPIO_SIPO_MODE_MASK BIT(2)
+#define GPIO_PON_MODE_MASK BIT(0)
+
+#define REG_NPU_UART_EN 0x0220
+#define JTAG_UDI_EN_MASK BIT(4)
+#define JTAG_DFD_EN_MASK BIT(3)
+#define NPU_UART_EN_MASK BIT(2)
+
+#define REG_FORCE_GPIO_EN 0x0224
+#define FORCE_GPIO_EN(n) BIT(n)
+
+/* LED MAP */
+#define REG_LAN_LED0_MAPPING 0x0278
+#define REG_LAN_LED1_MAPPING 0x027c
+
+#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/* CONF */
+#define REG_I2C_SDA_E2 0x001c
+#define SPI_MISO_E2_MASK BIT(13)
+#define SPI_MOSI_E2_MASK BIT(12)
+#define SPI_CLK_E2_MASK BIT(11)
+#define SPI_CS0_E2_MASK BIT(10)
+#define PCIE1_RESET_E2_MASK BIT(9)
+#define PCIE0_RESET_E2_MASK BIT(8)
+#define UART1_RXD_E2_MASK BIT(3)
+#define UART1_TXD_E2_MASK BIT(2)
+#define I2C_SCL_E2_MASK BIT(1)
+#define I2C_SDA_E2_MASK BIT(0)
+
+#define REG_I2C_SDA_E4 0x0020
+#define SPI_MISO_E4_MASK BIT(13)
+#define SPI_MOSI_E4_MASK BIT(12)
+#define SPI_CLK_E4_MASK BIT(11)
+#define SPI_CS0_E4_MASK BIT(10)
+#define PCIE1_RESET_E4_MASK BIT(9)
+#define PCIE0_RESET_E4_MASK BIT(8)
+#define UART1_RXD_E4_MASK BIT(3)
+#define UART1_TXD_E4_MASK BIT(2)
+#define I2C_SCL_E4_MASK BIT(1)
+#define I2C_SDA_E4_MASK BIT(0)
+
+#define REG_GPIO_L_E2 0x0024
+#define REG_GPIO_L_E4 0x0028
+
+#define REG_I2C_SDA_PU 0x0044
+#define SPI_MISO_PU_MASK BIT(13)
+#define SPI_MOSI_PU_MASK BIT(12)
+#define SPI_CLK_PU_MASK BIT(11)
+#define SPI_CS0_PU_MASK BIT(10)
+#define PCIE1_RESET_PU_MASK BIT(9)
+#define PCIE0_RESET_PU_MASK BIT(8)
+#define UART1_RXD_PU_MASK BIT(3)
+#define UART1_TXD_PU_MASK BIT(2)
+#define I2C_SCL_PU_MASK BIT(1)
+#define I2C_SDA_PU_MASK BIT(0)
+
+#define REG_I2C_SDA_PD 0x0048
+#define SPI_MISO_PD_MASK BIT(13)
+#define SPI_MOSI_PD_MASK BIT(12)
+#define SPI_CLK_PD_MASK BIT(11)
+#define SPI_CS0_PD_MASK BIT(10)
+#define PCIE1_RESET_PD_MASK BIT(9)
+#define PCIE0_RESET_PD_MASK BIT(8)
+#define UART1_RXD_PD_MASK BIT(3)
+#define UART1_TXD_PD_MASK BIT(2)
+#define I2C_SCL_PD_MASK BIT(1)
+#define I2C_SDA_PD_MASK BIT(0)
+
+#define REG_GPIO_L_PU 0x004c
+#define REG_GPIO_L_PD 0x0050
+
+/* PWM MODE CONF */
+#define REG_GPIO_FLASH_MODE_CFG 0x0034
+#define GPIO15_FLASH_MODE_CFG BIT(15)
+#define GPIO14_FLASH_MODE_CFG BIT(14)
+#define GPIO13_FLASH_MODE_CFG BIT(13)
+#define GPIO12_FLASH_MODE_CFG BIT(12)
+#define GPIO11_FLASH_MODE_CFG BIT(11)
+#define GPIO10_FLASH_MODE_CFG BIT(10)
+#define GPIO9_FLASH_MODE_CFG BIT(9)
+#define GPIO8_FLASH_MODE_CFG BIT(8)
+#define GPIO7_FLASH_MODE_CFG BIT(7)
+#define GPIO6_FLASH_MODE_CFG BIT(6)
+#define GPIO5_FLASH_MODE_CFG BIT(5)
+#define GPIO4_FLASH_MODE_CFG BIT(4)
+#define GPIO3_FLASH_MODE_CFG BIT(3)
+#define GPIO2_FLASH_MODE_CFG BIT(2)
+#define GPIO1_FLASH_MODE_CFG BIT(1)
+#define GPIO0_FLASH_MODE_CFG BIT(0)
+
+/* PWM MODE CONF EXT */
+#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
+#define GPIO51_FLASH_MODE_CFG BIT(31)
+#define GPIO50_FLASH_MODE_CFG BIT(30)
+#define GPIO49_FLASH_MODE_CFG BIT(29)
+#define GPIO48_FLASH_MODE_CFG BIT(28)
+#define GPIO47_FLASH_MODE_CFG BIT(27)
+#define GPIO46_FLASH_MODE_CFG BIT(26)
+#define GPIO45_FLASH_MODE_CFG BIT(25)
+#define GPIO44_FLASH_MODE_CFG BIT(24)
+#define GPIO43_FLASH_MODE_CFG BIT(23)
+#define GPIO42_FLASH_MODE_CFG BIT(22)
+#define GPIO41_FLASH_MODE_CFG BIT(21)
+#define GPIO40_FLASH_MODE_CFG BIT(20)
+#define GPIO39_FLASH_MODE_CFG BIT(19)
+#define GPIO38_FLASH_MODE_CFG BIT(18)
+#define GPIO37_FLASH_MODE_CFG BIT(17)
+#define GPIO36_FLASH_MODE_CFG BIT(16)
+#define GPIO31_FLASH_MODE_CFG BIT(15)
+#define GPIO30_FLASH_MODE_CFG BIT(14)
+#define GPIO29_FLASH_MODE_CFG BIT(13)
+#define GPIO28_FLASH_MODE_CFG BIT(12)
+#define GPIO27_FLASH_MODE_CFG BIT(11)
+#define GPIO26_FLASH_MODE_CFG BIT(10)
+#define GPIO25_FLASH_MODE_CFG BIT(9)
+#define GPIO24_FLASH_MODE_CFG BIT(8)
+#define GPIO23_FLASH_MODE_CFG BIT(7)
+#define GPIO22_FLASH_MODE_CFG BIT(6)
+#define GPIO21_FLASH_MODE_CFG BIT(5)
+#define GPIO20_FLASH_MODE_CFG BIT(4)
+#define GPIO19_FLASH_MODE_CFG BIT(3)
+#define GPIO18_FLASH_MODE_CFG BIT(2)
+#define GPIO17_FLASH_MODE_CFG BIT(1)
+#define GPIO16_FLASH_MODE_CFG BIT(0)
+
+#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ 0 \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_MUX, \
+ REG_GPIO_FLASH_MODE_CFG, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ }
+
+#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_PON_MODE, \
+ (smux_val), \
+ (smux_val) \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED0_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED1_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+static struct pinctrl_pin_desc pinctrl_pins[] = {
+ PINCTRL_PIN(2, "i2c_sda"),
+ PINCTRL_PIN(3, "i2c_scl"),
+ PINCTRL_PIN(4, "spi_cs0"),
+ PINCTRL_PIN(5, "spi_clk"),
+ PINCTRL_PIN(6, "spi_mosi"),
+ PINCTRL_PIN(7, "spi_miso"),
+ PINCTRL_PIN(8, "uart1_txd"),
+ PINCTRL_PIN(9, "uart1_rxd"),
+ PINCTRL_PIN(12, "gpio0"),
+ PINCTRL_PIN(13, "gpio1"),
+ PINCTRL_PIN(14, "gpio2"),
+ PINCTRL_PIN(15, "gpio3"),
+ PINCTRL_PIN(16, "gpio4"),
+ PINCTRL_PIN(17, "gpio5"),
+ PINCTRL_PIN(18, "gpio6"),
+ PINCTRL_PIN(19, "gpio7"),
+ PINCTRL_PIN(20, "gpio8"),
+ PINCTRL_PIN(21, "gpio9"),
+ PINCTRL_PIN(22, "gpio10"),
+ PINCTRL_PIN(23, "gpio11"),
+ PINCTRL_PIN(24, "gpio12"),
+ PINCTRL_PIN(25, "gpio13"),
+ PINCTRL_PIN(26, "gpio14"),
+ PINCTRL_PIN(27, "gpio15"),
+ PINCTRL_PIN(28, "gpio16"),
+ PINCTRL_PIN(29, "gpio17"),
+ PINCTRL_PIN(30, "gpio18"),
+ PINCTRL_PIN(31, "gpio19"),
+ PINCTRL_PIN(32, "gpio20"),
+ PINCTRL_PIN(33, "gpio21"),
+ PINCTRL_PIN(34, "gpio22"),
+ PINCTRL_PIN(35, "gpio23"),
+ PINCTRL_PIN(36, "gpio24"),
+ PINCTRL_PIN(37, "gpio25"),
+ PINCTRL_PIN(38, "gpio26"),
+ PINCTRL_PIN(39, "gpio27"),
+ PINCTRL_PIN(40, "pcie_reset0"),
+ PINCTRL_PIN(41, "pcie_reset1"),
+};
+
+static const int pon_pins[] = { 28, 29, 30, 31, 32, 33 };
+static const int pon_tod_1pps_pins[] = { 21 };
+static const int gsw_tod_1pps_pins[] = { 21 };
+static const int sipo_pins[] = { 13, 38 };
+static const int sipo_rclk_pins[] = { 13, 30, 38 };
+static const int mdio_pins[] = { 20, 21 };
+static const int uart2_pins[] = { 20, 21 };
+static const int npu_uart_pins[] = { 13, 38 };
+static const int i2c0_pins[] = { 2, 3 };
+static const int i2c1_pins[] = { 14, 15 };
+static const int jtag_udi_pins[] = { 34, 35, 36, 37, 38 };
+static const int jtag_dfd_pins[] = { 34, 35, 36, 37, 38 };
+static const int i2s_pins[] = { 16, 17, 18, 19 };
+static const int pcm1_pins[] = { 24, 25, 26, 27 };
+static const int pcm2_pins[] = { 16, 17, 18, 19 };
+static const int spi_pins[] = { 4, 5, 6, 7 };
+static const int spi_quad_pins[] = { 14, 15 };
+static const int spi_cs1_pins[] = { 21 };
+static const int pcm_spi_pins[] = { 16, 17, 18, 19, 24, 25, 26, 27 };
+static const int pcm_spi_int_pins[] = { 15 };
+static const int pcm_spi_rst_pins[] = { 14 };
+static const int pcm_spi_cs1_pins[] = { 22 };
+static const int pcm_spi_cs2_p128_pins[] = { 39 };
+static const int pcm_spi_cs2_p156_pins[] = { 39 };
+static const int pcm_spi_cs3_pins[] = { 20 };
+static const int pcm_spi_cs4_pins[] = { 23 };
+static const int gpio0_pins[] = { 12 };
+static const int gpio1_pins[] = { 13 };
+static const int gpio2_pins[] = { 14 };
+static const int gpio3_pins[] = { 15 };
+static const int gpio4_pins[] = { 16 };
+static const int gpio5_pins[] = { 17 };
+static const int gpio6_pins[] = { 18 };
+static const int gpio7_pins[] = { 19 };
+static const int gpio8_pins[] = { 20 };
+static const int gpio9_pins[] = { 21 };
+static const int gpio10_pins[] = { 22 };
+static const int gpio11_pins[] = { 23 };
+static const int gpio12_pins[] = { 24 };
+static const int gpio13_pins[] = { 25 };
+static const int gpio14_pins[] = { 26 };
+static const int gpio15_pins[] = { 27 };
+static const int gpio16_pins[] = { 28 };
+static const int gpio17_pins[] = { 29 };
+static const int gpio18_pins[] = { 30 };
+static const int gpio19_pins[] = { 31 };
+static const int gpio20_pins[] = { 32 };
+static const int gpio21_pins[] = { 33 };
+static const int gpio22_pins[] = { 34 };
+static const int gpio23_pins[] = { 35 };
+static const int gpio24_pins[] = { 36 };
+static const int gpio25_pins[] = { 37 };
+static const int gpio26_pins[] = { 38 };
+static const int gpio27_pins[] = { 39 };
+static const int gpio28_pins[] = { 40 };
+static const int gpio29_pins[] = { 41 };
+static const int pcie_reset0_pins[] = { 40 };
+static const int pcie_reset1_pins[] = { 41 };
+
+static const struct pingroup pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", mdio),
+ PINCTRL_PIN_GROUP("uart2", uart2),
+ PINCTRL_PIN_GROUP("npu_uart", npu_uart),
+ PINCTRL_PIN_GROUP("i2c0", i2c0),
+ PINCTRL_PIN_GROUP("i2c1", i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+ PINCTRL_PIN_GROUP("i2s", i2s),
+ PINCTRL_PIN_GROUP("pcm1", pcm1),
+ PINCTRL_PIN_GROUP("pcm2", pcm2),
+ PINCTRL_PIN_GROUP("spi", spi),
+ PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156),
+ PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3),
+ PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4),
+ PINCTRL_PIN_GROUP("gpio0", gpio0),
+ PINCTRL_PIN_GROUP("gpio1", gpio1),
+ PINCTRL_PIN_GROUP("gpio2", gpio2),
+ PINCTRL_PIN_GROUP("gpio3", gpio3),
+ PINCTRL_PIN_GROUP("gpio4", gpio4),
+ PINCTRL_PIN_GROUP("gpio5", gpio5),
+ PINCTRL_PIN_GROUP("gpio6", gpio6),
+ PINCTRL_PIN_GROUP("gpio7", gpio7),
+ PINCTRL_PIN_GROUP("gpio8", gpio8),
+ PINCTRL_PIN_GROUP("gpio9", gpio9),
+ PINCTRL_PIN_GROUP("gpio10", gpio10),
+ PINCTRL_PIN_GROUP("gpio11", gpio11),
+ PINCTRL_PIN_GROUP("gpio12", gpio12),
+ PINCTRL_PIN_GROUP("gpio13", gpio13),
+ PINCTRL_PIN_GROUP("gpio14", gpio14),
+ PINCTRL_PIN_GROUP("gpio15", gpio15),
+ PINCTRL_PIN_GROUP("gpio16", gpio16),
+ PINCTRL_PIN_GROUP("gpio17", gpio17),
+ PINCTRL_PIN_GROUP("gpio18", gpio18),
+ PINCTRL_PIN_GROUP("gpio19", gpio19),
+ PINCTRL_PIN_GROUP("gpio20", gpio20),
+ PINCTRL_PIN_GROUP("gpio21", gpio21),
+ PINCTRL_PIN_GROUP("gpio22", gpio22),
+ PINCTRL_PIN_GROUP("gpio23", gpio23),
+ PINCTRL_PIN_GROUP("gpio24", gpio24),
+ PINCTRL_PIN_GROUP("gpio25", gpio25),
+ PINCTRL_PIN_GROUP("gpio26", gpio26),
+ PINCTRL_PIN_GROUP("gpio27", gpio27),
+ PINCTRL_PIN_GROUP("gpio28", gpio28),
+ PINCTRL_PIN_GROUP("gpio29", gpio29),
+ PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+};
+
+static const char *const pon_groups[] = { "pon" };
+static const char *const tod_1pps_groups[] = {
+ "pon_tod_1pps", "gsw_tod_1pps"
+};
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const mdio_groups[] = { "mdio" };
+static const char *const uart_groups[] = { "uart2", "npu_uart" };
+static const char *const i2c_groups[] = { "i2c1" };
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const pcm_spi_groups[] = {
+ "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
+ "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", "pcm_spi_cs4"
+};
+static const char *const i2s_groups[] = { "i2s" };
+static const char *const gpio_groups[] = { "gpio28", "gpio29" };
+static const char *const pcie_reset_groups[] = {
+ "pcie_reset0", "pcie_reset1"
+};
+static const char *const pwm_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+ "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29"
+};
+static const char *const phy1_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy2_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy3_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy4_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy1_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy2_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy3_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy4_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+ {
+ .name = "pon",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PON_MODE_MASK,
+ GPIO_PON_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+ {
+ .name = "pon_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ PON_TOD_1PPS_MODE_MASK,
+ PON_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "gsw_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GSW_TOD_1PPS_MODE_MASK,
+ GSW_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+ {
+ .name = "sipo",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "sipo_rclk",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
+ {
+ .name = "mdio",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_SGMII_MDIO_MODE_MASK,
+ GPIO_SGMII_MDIO_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+ {
+ .name = "uart2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK,
+ GPIO_UART2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "npu_uart",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ NPU_UART_EN_MASK,
+ NPU_UART_EN_MASK
+ },
+ .regmap_size = 1,
+ }
+};
+
+static const struct airoha_pinctrl_func_group i2c_func_group[] = {
+ {
+ .name = "i2c1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GPIO_2ND_I2C_MODE_MASK,
+ GPIO_2ND_I2C_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+ {
+ .name = "jtag_udi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_UDI_EN_MASK,
+ JTAG_UDI_EN_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "jtag_dfd",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_NPU_UART_EN,
+ JTAG_DFD_EN_MASK,
+ JTAG_DFD_EN_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+ {
+ .name = "pcm1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM1_MODE_MASK,
+ GPIO_PCM1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM2_MODE_MASK,
+ GPIO_PCM2_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+ {
+ .name = "spi_quad",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_QUAD_MODE_MASK,
+ GPIO_SPI_QUAD_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS1_MODE_MASK,
+ GPIO_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
+ {
+ .name = "pcm_spi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_MODE_MASK,
+ GPIO_PCM_SPI_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_int",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_INT_MODE_MASK,
+ GPIO_PCM_INT_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_rst",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_RESET_MODE_MASK,
+ GPIO_PCM_RESET_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS1_MODE_MASK,
+ GPIO_PCM_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs2_p128",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS2_MODE_P128_MASK,
+ GPIO_PCM_SPI_CS2_MODE_P128_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs2_p156",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS2_MODE_P156_MASK,
+ GPIO_PCM_SPI_CS2_MODE_P156_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS3_MODE_MASK,
+ GPIO_PCM_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS4_MODE_MASK,
+ GPIO_PCM_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group i2s_func_group[] = {
+ {
+ .name = "i2s",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_2ND_I2C_MODE,
+ GPIO_I2S_MODE_MASK,
+ GPIO_I2S_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+ AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+};
+
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+ {
+ .name = "pcie_reset0",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET0_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcie_reset1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET1_MASK,
+ 0
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+ AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET0_MASK),
+ AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG,
+ GPIO_PCIE_RESET1_MASK),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
+ PINCTRL_FUNC_DESC("pon", pon),
+ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+ PINCTRL_FUNC_DESC("sipo", sipo),
+ PINCTRL_FUNC_DESC("mdio", mdio),
+ PINCTRL_FUNC_DESC("uart", uart),
+ PINCTRL_FUNC_DESC("i2c", i2c),
+ PINCTRL_FUNC_DESC("jtag", jtag),
+ PINCTRL_FUNC_DESC("pcm", pcm),
+ PINCTRL_FUNC_DESC("spi", spi),
+ PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
+ PINCTRL_FUNC_DESC("i2s", i2s),
+ PINCTRL_FUNC_DESC("gpio", gpio),
+ PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+ PINCTRL_FUNC_DESC("pwm", pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+ PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+ PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+ PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(29)),
+};
+
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .pinctrl_name = KBUILD_MODNAME,
+ .pinctrl_owner = THIS_MODULE,
+ .pins = pinctrl_pins,
+ .num_pins = ARRAY_SIZE(pinctrl_pins),
+ .grps = pinctrl_groups,
+ .num_grps = ARRAY_SIZE(pinctrl_groups),
+ .funcs = pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(pinctrl_funcs),
+ .confs_info = {
+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
+ .confs = pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+ .confs = pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+ .confs = pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+ .confs = pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
+ },
+ },
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+ { .compatible = "airoha,en7523-pinctrl", .data = &pinctrl_match_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+ .probe = airoha_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-airoha-en7523",
+ .of_match_table = airoha_pinctrl_of_match,
+ },
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_AUTHOR("Matheus Sampaio Queiroga <srherobrine20@gmail.com>");
+MODULE_AUTHOR("Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha EN7523 SoC");
--
2.53.0
^ permalink raw reply related
* [PATCH v6 16/17] pinctrl: airoha: try to find chip scu node by phandle first
From: Mikhail Kshevetskiy @ 2026-06-28 14:37 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260628143733.273651-1-mikhail.kshevetskiy@iopsys.eu>
The "airoha,en7581-chip-scu" is not a good compatible string in the en7523
case. Let's search chip scu regmap with "airoha,chip-scu" phangle first
and fallback to SoC specific chip scu compatible string on failure.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/airoha-common.h | 1 +
drivers/pinctrl/airoha/pinctrl-airoha.c | 9 ++++++---
drivers/pinctrl/airoha/pinctrl-an7581.c | 1 +
drivers/pinctrl/airoha/pinctrl-an7583.c | 1 +
drivers/pinctrl/airoha/pinctrl-en7523.c | 1 +
5 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
index 9a202d5bb4b1..47900be19c2b 100644
--- a/drivers/pinctrl/airoha/airoha-common.h
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -154,6 +154,7 @@ struct airoha_pinctrl {
};
struct airoha_pinctrl_match_data {
+ const char *chip_scu_compatible;
const char *pinctrl_name;
struct module *pinctrl_owner;
const struct pinctrl_pin_desc *pins;
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index 543475d23fde..e24e03b39d3d 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -683,9 +683,12 @@ int airoha_pinctrl_probe(struct platform_device *pdev)
if (IS_ERR(pinctrl->regmap))
return PTR_ERR(pinctrl->regmap);
- map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
- if (IS_ERR(map))
- return PTR_ERR(map);
+ map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "airoha,chip-scu");
+ if (IS_ERR_OR_NULL(map)) {
+ map = syscon_regmap_lookup_by_compatible(data->chip_scu_compatible);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+ }
pinctrl->chip_scu = map;
diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
index 6e53143e91d7..6d6c5f1ee5d2 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
@@ -1432,6 +1432,7 @@ static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
};
static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .chip_scu_compatible = "airoha,en7581-chip-scu",
.pinctrl_name = KBUILD_MODNAME,
.pinctrl_owner = THIS_MODULE,
.pins = pinctrl_pins,
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 74f93327d41a..6d3ef32acf62 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -1442,6 +1442,7 @@ static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
};
static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .chip_scu_compatible = "airoha,en7581-chip-scu",
.pinctrl_name = KBUILD_MODNAME,
.pinctrl_owner = THIS_MODULE,
.pins = pinctrl_pins,
diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c
index 7f434c9bce92..a6202f6313d5 100644
--- a/drivers/pinctrl/airoha/pinctrl-en7523.c
+++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
@@ -1072,6 +1072,7 @@ static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
};
static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .chip_scu_compatible = "airoha,en7523-chip-scu",
.pinctrl_name = KBUILD_MODNAME,
.pinctrl_owner = THIS_MODULE,
.pins = pinctrl_pins,
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v3 3/8] irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper
From: Val Packett @ 2026-06-28 17:54 UTC (permalink / raw)
To: Maulik Shah, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thomas Gleixner, Linus Walleij
Cc: linux-arm-msm, linux-kernel, devicetree, linux-gpio, Sneh Mankad
In-Reply-To: <20260616-hamoa_pdc_v3-v3-3-4d8e1504ea75@oss.qualcomm.com>
On 6/16/26 6:25 AM, Maulik Shah wrote:
> pdc->enable_intr() function already points to respective version
> specific enable function. pdc_enable_intr() now only kept as wrapper.
> Remove the wrapper and invoke pdc->enable_intr() from caller.
>
> Locking in pdc_enable_intr() applies lock to all pdc->enable_intr()
> however its only required for pdc_enable_intr_bank() which uses
> a shared bank across all interrupts. pdc_enable_intr_cfg() do not
> required locking as IRQ_CFG registers are one per interrupt. Move
> locking accordingly.
>
> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
> ---
> drivers/irqchip/qcom-pdc.c | 13 ++++---------
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
> index b9acb0f25c9c..6c556464d37c 100644
> --- a/drivers/irqchip/qcom-pdc.c
> +++ b/drivers/irqchip/qcom-pdc.c
> @@ -206,6 +206,8 @@ static void pdc_enable_intr_bank(int pin_out, bool on)
> index = FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out);
> mask = FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out);
>
> + guard(raw_spinlock)(&pdc->lock);
> [..]
whoops..
[ 0.197090] BUG: spinlock bad magic on CPU#7, swapper/0/1
[ 0.197104] lock: 0xffff0001022e37b0, .magic: 00000000, .owner:
<none>/-1, .owner_cpu: 0
[ 0.197122] CPU: 7 UID: 0 PID: 1 Comm: swapper/0 Not tainted
7.1.0-next-20260626-uwu+ #128 PREEMPT(full)
[ 0.197129] Hardware name: motorola Motorola Edge 30
(Tianma)/Motorola Edge 30 (Tianma), BIOS 2026.07-rc2-g432bcf301c03-dirty
07/01/2026
[ 0.197133] Call trace:
[ 0.197135] show_stack+0x24/0x38 (C)
[ 0.197148] __dump_stack+0x28/0x38
[ 0.197156] dump_stack_lvl+0x7c/0xa8
[ 0.197165] dump_stack+0x18/0x30
[ 0.197172] spin_dump+0x7c/0x98
[ 0.197179] do_raw_spin_lock+0xa4/0x140
[ 0.197189] _raw_spin_lock+0x2c/0x40
[ 0.197195] pdc_enable_intr_bank+0x40/0x128
[ 0.197201] qcom_pdc_probe+0x3bc/0x520
Gotta also move the spinlock init to before the call to
pdc_setup_pin_mapping..
~val
^ permalink raw reply
* Re: [PATCH v3 0/8] x1e80100: Enable PDC wake GPIOs and deepest idle state
From: Val Packett @ 2026-06-28 18:39 UTC (permalink / raw)
To: Maulik Shah, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thomas Gleixner, Linus Walleij
Cc: linux-arm-msm, linux-kernel, devicetree, linux-gpio, Sneh Mankad,
Stephan Gerhold
In-Reply-To: <20260616-hamoa_pdc_v3-v3-0-4d8e1504ea75@oss.qualcomm.com>
On 6/16/26 6:25 AM, Maulik Shah wrote:
> [..]
> ---
> Maulik Shah (7):
> irqchip/qcom-pdc: restructure version support
> irqchip/qcom-pdc: Move all statics to struct pdc_desc
> irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper
> irqchip/qcom-pdc: Differentiate between direct SPI and GPIO as SPI
> irqchip/qcom-pdc: Configure PDC to pass through mode
> Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now"
> arm64: dts: qcom: x1e80100: Add deepest idle state
>
> Stephan Gerhold (1):
> pinctrl: qcom: Acknowledge IRQs for PDC interrupt controller
>
> [..]
Something about this series breaks the touchscreen interrupt (<&tlmm 81
IRQ_TYPE_LEVEL_LOW>) on sm7325-motorola-dubai :(
With this series, that interrupt only happens once (stuck at 1 in
/proc/interrupts) so events are not reported. Something something level
triggered..??
Thanks,
~val
^ permalink raw reply
* Re: [PATCH v6 01/17] dt-bindings: pinctrl: airoha: update/fix device tree binding schemas
From: Conor Dooley @ 2026-06-28 19:15 UTC (permalink / raw)
To: Mikhail Kshevetskiy
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
In-Reply-To: <20260628143733.273651-2-mikhail.kshevetskiy@iopsys.eu>
[-- Attachment #1: Type: text/plain, Size: 5531 bytes --]
On Sun, Jun 28, 2026 at 05:37:17PM +0300, Mikhail Kshevetskiy wrote:
> This patch fix several misprints and sync device tree binding schemas
> with actual driver code.
Please split this up and provide some explanation for why each thing is
incorrect.
pw-bot: changes-requested
>
Missing a Fixes: tag.
Thanks,
Conor.
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
> .../pinctrl/airoha,an7583-pinctrl.yaml | 37 +++++++------------
> .../pinctrl/airoha,en7581-pinctrl.yaml | 4 +-
> 2 files changed, 16 insertions(+), 25 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
> index 79910214d9b5..f52802a3ad79 100644
> --- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
> @@ -61,7 +61,7 @@ patternProperties:
> description:
> A string containing the name of the function to mux to the group.
> enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
> - pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0,
> + pcm_spi, emmc, pnand, pcie_reset, pwm, phy1_led0,
> phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
> phy3_led1, phy4_led1]
>
> @@ -159,17 +159,8 @@ patternProperties:
> properties:
> groups:
> items:
> - enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1,
> - pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4]
> - maxItems: 7
> - - if:
> - properties:
> - function:
> - const: i2c
> - then:
> - properties:
> - groups:
> - enum: [i2s]
> + enum: [pcm_spi, pcm_spi_rst, pcm_spi_cs1]
> + maxItems: 3
> - if:
> properties:
> function:
> @@ -207,7 +198,8 @@ patternProperties:
> gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
> gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
> gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
> - gpio42, gpio43, gpio44, gpio45, gpio46, gpio47]
> + gpio42, gpio43, gpio44, gpio45, gpio46, gpio47,
> + gpio48]
> - if:
> properties:
> function:
> @@ -288,17 +280,16 @@ patternProperties:
> description:
> An array of strings. Each string contains the name of a pin.
> items:
> - enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk,
> - spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4,
> - gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12,
> - gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19,
> - gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26,
> - gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33,
> - gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40,
> - gpio41, gpio42, gpio43, gpio44, gpio45, gpio46,
> - pcie_reset0, pcie_reset1, pcie_reset2]
> + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
> + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
> + gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21,
> + gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28,
> + gpio29, gpio30, gpio31, gpio32, gpio33, gpio34, gpio35,
> + gpio36, gpio37, gpio38, i2c0_scl, i2c0_sda, i2c1_scl,
> + i2c1_sda, spi_clk, spi_cs, spi_mosi, spi_miso, uart_txd,
> + uart_rxd, pcie_reset0, pcie_reset1, mdc_0, mdio_0]
> minItems: 1
> - maxItems: 58
> + maxItems: 53
>
> bias-disable: true
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> index 21fd4f1ba78b..12dd85b5b410 100644
> --- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> @@ -166,7 +166,7 @@ patternProperties:
> - if:
> properties:
> function:
> - const: i2c
> + const: i2s
> then:
> properties:
> groups:
> @@ -208,7 +208,7 @@ patternProperties:
> gpio20, gpio21, gpio22, gpio23, gpio24, gpio25,
> gpio26, gpio27, gpio28, gpio29, gpio30, gpio31,
> gpio36, gpio37, gpio38, gpio39, gpio40, gpio41,
> - gpio42, gpio43, gpio44, gpio45, gpio46, gpio47]
> + gpio42, gpio43, gpio44, gpio45, gpio46]
> - if:
> properties:
> function:
> --
> 2.53.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH 4/9] MIPS: TXX9: rbtx4927: Use GPIO lookup table for TXx9 LEDs
From: XIAO WU @ 2026-06-28 19:23 UTC (permalink / raw)
To: Geert Uytterhoeven, Thomas Bogendoerfer, Linus Walleij,
Bartosz Golaszewski, Arnd Bergmann
Cc: linux-mips, linux-gpio, linux-kernel
In-Reply-To: <3615eba18ff6a9351ecb11d9f5a0c86ef7b0e670.1782389357.git.geert@linux-m68k.org>
Hi,
I came across the Sashiko AI review of this series and reproduced the
use-after-free that it flagged in rbtx4927_gpioled_init() — a KASAN
slab-use-after-free triggers when platform_device_add() fails on the
error path.
The Sashiko review is at:
https://sashiko.dev/#/patchset/cover.1782389357.git.geert@linux-m68k.org
In rbtx4927_gpioled_init() (arch/mips/txx9/rbtx4927/setup.c), this
patch introduces a GPIO lookup table that references the platform
device name. The error path looks like:
```c
pdev = platform_device_alloc("leds-gpio", 0);
if (!pdev)
return;
pdev->dev.platform_data = &pdata;
if (platform_device_add(pdev))
platform_device_put(pdev); // frees pdev on error!
rbtx4927_gpioled_table.dev_id = dev_name(&pdev->dev); // UAF!
```
If platform_device_add() fails (e.g., because a device with the same
name already exists in the platform bus), platform_device_put() drops
the last reference and frees the struct platform_device. The code then
unconditionally calls dev_name(&pdev->dev) on the freed pointer, and
assigns the dangling pointer into the global GPIO lookup table.
This is a classic use-after-free: the freed memory can be reallocated
and overwritten, and the GPIO lookup table will later dereference a
dangling or corrupted dev_id pointer.
For comparison, the iocled equivalent introduced in patch 6 handles
this correctly with a goto:
```c
if (platform_device_add(pdev))
goto out_pdev; // skips dev_name()
txx9_iocled_table.dev_id = dev_name(&pdev->dev);
...
out_pdev:
platform_device_put(pdev);
```
=== Reproduction ===
Kernel: 7.1.0-next-20260623-gaca8efd71d03-dirty #3 PREEMPT(full)
Arch: x86_64 (QEMU Standard PC Q35 + ICH9, 2009)
Config: CONFIG_KASAN=y
The UAF pattern is reproduced via a kernel module that mirrors the
same platform_device_add / dev_name error path sequence. The module
loads at boot via late_initcall.
=== Crash Log ===
[ 18.070459][ T1] BUG: KASAN: slab-use-after-free in
poc_uaf_init+0x25b/0x270
[ 18.071324][ T1] Read of size 8 at addr ffff8880300f5060 by task
swapper/0/1
[ 18.072437][ T1] CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted
7.1.0-next-20260623-gaca8efd71d03-dirty #3
[ 18.072448][ T1] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009)
[ 18.072452][ T1] Call Trace:
[ 18.072455][ T1] <TASK>
[ 18.072458][ T1] dump_stack_lvl+0x116/0x1f0
[ 18.072466][ T1] print_report+0xf4/0x600
[ 18.072497][ T1] kasan_report+0xe0/0x110
[ 18.072509][ T1] ? poc_uaf_init+0x25b/0x270
[ 18.072519][ T1] poc_uaf_init+0x25b/0x270
[ 18.072528][ T1] do_one_initcall+0x128/0x700
[ 18.072558][ T1] kernel_init_freeable+0x5d2/0x940
[ 18.072573][ T1] kernel_init+0x21/0x2c0
[ 18.072596][ T1] ret_from_fork+0xb2c/0xdd0
[ 18.072648][ T1] </TASK>
[ 18.087231][ T1] Allocated by task 1:
[ 18.088000][ T1] kasan_save_stack+0x33/0x60
[ 18.089000][ T1] __kasan_kmalloc+0xaa/0xb0
[ 18.090000][ T1] platform_device_alloc+0x3a/0x110
[ 18.091000][ T1] poc_uaf_init+0x1a0/0x270
[ 18.092000][ T1] Freed by task 1:
[ 18.093000][ T1] kfree+0x171/0x720
[ 18.094000][ T1] platform_device_put+0x2f/0x40
[ 18.095000][ T1] poc_uaf_init+0x240/0x270
The KASAN report confirms: platform_device_alloc() allocates, then
platform_device_put() frees, and the subsequent dev_name() read
triggers the slab-use-after-free.
=== PoC ===
The trigger is a minimal kernel module that replicates the buggy
error-path pattern. It:
1. Calls platform_device_alloc("poc-uaf", 0)
2. Calls platform_device_add() — which fails with -EEXIST because
a previous load already registered "poc-uaf.0"
3. Calls platform_device_put() — frees the device
4. Reads dev_name(&pdev->dev) — UAF on freed pdev
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/init.h>
static int __init poc_uaf_init(void)
{
struct platform_device *pdev;
int ret;
pdev = platform_device_alloc("poc-uaf", 0);
if (!pdev)
return -ENOMEM;
ret = platform_device_add(pdev);
if (ret)
platform_device_put(pdev);
/* UAF: pdev freed by platform_device_put() above,
* but dev_name() dereferences the freed memory.
*/
pr_info("poc-uaf: dev_name=%s\n", dev_name(&pdev->dev));
return 0;
}
module_init(poc_uaf_init);
MODULE_LICENSE("GPL");
Build: insert into kernel tree and build with CONFIG_POC_UAF=m
Run: insmod poc_uaf.ko (twice, so the second load hits -EEXIST)
Thanks,
Xiao
^ permalink raw reply
* Re: [PATCH v6 17/17] pinctrl: airoha: add support of an7563 SoC
From: Rob Herring (Arm) @ 2026-06-28 20:51 UTC (permalink / raw)
To: Mikhail Kshevetskiy
Cc: Benjamin Larsson, Krzysztof Kozlowski, Matheus Sampaio Queiroga,
Christian Marangi, linux-kernel, AngeloGioacchino Del Regno,
devicetree, Lorenzo Bianconi, linux-gpio, linux-mediatek,
Markus Gothe, Linus Walleij, Conor Dooley
In-Reply-To: <20260628143733.273651-18-mikhail.kshevetskiy@iopsys.eu>
On Sun, 28 Jun 2026 17:37:33 +0300, Mikhail Kshevetskiy wrote:
> This patch adds support of Airoha an7563 SoC pin controller.
> Also it adds corresponding device tree binding schema.
>
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
> .../pinctrl/airoha,an7563-pinctrl.yaml | 348 +++++
> drivers/pinctrl/airoha/Kconfig | 6 +
> drivers/pinctrl/airoha/Makefile | 1 +
> drivers/pinctrl/airoha/pinctrl-an7563.c | 1115 +++++++++++++++++
> 4 files changed, 1470 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml
> create mode 100644 drivers/pinctrl/airoha/pinctrl-an7563.c
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.example.dtb: /example-0/pinctrl: failed to match any schema with compatible: ['airoha,en7521-pinctrl']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260628143733.273651-18-mikhail.kshevetskiy@iopsys.eu
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH v6 15/17] pinctrl: airoha: add support of en7523 SoC
From: Rob Herring (Arm) @ 2026-06-28 20:51 UTC (permalink / raw)
To: Mikhail Kshevetskiy
Cc: Matheus Sampaio Queiroga, devicetree, Benjamin Larsson,
Christian Marangi, Conor Dooley, linux-mediatek, Markus Gothe,
Krzysztof Kozlowski, linux-gpio, linux-kernel, Lorenzo Bianconi,
AngeloGioacchino Del Regno, Linus Walleij
In-Reply-To: <20260628143733.273651-16-mikhail.kshevetskiy@iopsys.eu>
On Sun, 28 Jun 2026 17:37:31 +0300, Mikhail Kshevetskiy wrote:
> This patch adds support of Airoha en7523 SoC pin controller.
> Also it adds corresponding device tree binding schema.
>
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
> .../pinctrl/airoha,en7523-pinctrl.yaml | 375 ++++++
> drivers/pinctrl/airoha/Kconfig | 6 +
> drivers/pinctrl/airoha/Makefile | 1 +
> drivers/pinctrl/airoha/pinctrl-en7523.c | 1124 +++++++++++++++++
> 4 files changed, 1506 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml
> create mode 100644 drivers/pinctrl/airoha/pinctrl-en7523.c
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.example.dtb: /example-0/pinctrl: failed to match any schema with compatible: ['airoha,en7521-pinctrl']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260628143733.273651-16-mikhail.kshevetskiy@iopsys.eu
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* [PATCH] gpio: mvebu: add wake-up interrupt support
From: Rosen Penev @ 2026-06-28 23:02 UTC (permalink / raw)
To: linux-gpio; +Cc: Linus Walleij, Bartosz Golaszewski, open list
Implement wake IRQ support for the mvebu GPIO controller:
- Replace unused irqbase field with bank_irq[4] to store per-bank
IRQ numbers for use in the wake-up callback.
- Add mvebu_gpio_set_wake_irq() that forwards enable_irq_wake /
disable_irq_wake to the correct parent IRQ based on hwirq.
- Set IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags
on both level and edge chip types.
- Set IRQ_GC_INIT_NESTED_LOCK for the nested irq domain.
- Add missing <linux/interrupt.h> include.
Assisted-by: opencode:big-pickle
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/gpio/gpio-mvebu.c | 40 ++++++++++++++++++++++++++++++++++++---
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index c030d1f00abc..26092b223be5 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -37,6 +37,7 @@
#include <linux/gpio/consumer.h>
#include <linux/gpio/machine.h>
#include <linux/init.h>
+#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
@@ -114,7 +115,7 @@ struct mvebu_gpio_chip {
struct regmap *regs;
u32 offset;
struct regmap *percpu_regs;
- int irqbase;
+ int bank_irq[4];
struct irq_domain *domain;
int soc_variant;
@@ -603,6 +604,34 @@ static const struct regmap_config mvebu_gpio_regmap_config = {
.val_bits = 32,
};
+/*
+ * Forward wake-up configuration to the parent bank IRQ.
+ * @d: interrupt data
+ * @enable: enable as wake-up if non-zero
+ *
+ * Return: 0 on success, or a negative error code.
+ */
+static int mvebu_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct mvebu_gpio_chip *mvchip = gc->private;
+ int bank;
+ int irq;
+
+ bank = d->hwirq / 8;
+ if (bank >= ARRAY_SIZE(mvchip->bank_irq))
+ return -EINVAL;
+
+ irq = mvchip->bank_irq[bank];
+ if (irq <= 0)
+ return -EINVAL;
+
+ if (enable)
+ return enable_irq_wake(irq);
+
+ return disable_irq_wake(irq);
+}
+
/*
* Functions implementing the pwm_chip methods
*/
@@ -1249,7 +1278,7 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
err = irq_alloc_domain_generic_chips(
mvchip->domain, ngpios, 2, np->name, handle_level_irq,
- IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
+ IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, IRQ_GC_INIT_NESTED_LOCK);
if (err) {
dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
mvchip->chip.label);
@@ -1267,6 +1296,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
+ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
ct->chip.name = mvchip->chip.label;
ct = &gc->chip_types[1];
@@ -1275,6 +1306,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
+ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
ct->handler = handle_edge_irq;
ct->chip.name = mvchip->chip.label;
@@ -1283,13 +1316,14 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
* interrupt handlers, with each handler dealing with 8 GPIO
* pins.
*/
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < ARRAY_SIZE(mvchip->bank_irq); i++) {
int irq = platform_get_irq_optional(pdev, i);
if (irq < 0)
continue;
irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
mvchip);
+ mvchip->bank_irq[i] = irq;
}
return 0;
--
2.54.0
^ permalink raw reply related
* [PATCH] gpio: dwapb: Defer clock gating until noirq
From: Jia Wang via B4 Relay @ 2026-06-29 5:30 UTC (permalink / raw)
To: Hoan Tran, Linus Walleij, Bartosz Golaszewski
Cc: Hoan Tran, linux-gpio, linux-kernel, Jia Wang
From: Jia Wang <wangjia@ultrarisc.com>
GPIO consumers such as gpio-keys can enable IRQ wake and adjust the wake
trigger type from their suspend callbacks. If the DWAPB controller suspends
first, masking interrupts and disabling its clocks in the normal suspend
phase prevents that late wake configuration from reliably reaching the
hardware. Systems with real DWAPB bus clocks then fail to wake from s2idle
through GPIO keys.
Save the register context in the normal suspend callback, but defer IRQ
masking and clock gating until suspend_noirq. At that point all consumers
have finished configuring wake IRQs, so keep the clocks enabled when wake
lines are armed and only gate them when no wake source is active.
Resume_noirq reenables clocks, if they were gated, before the normal resume
path restores registers.
Propagate wake requests to the parent irqchip while keeping the local wake
mask in sync with failures.
Fixes: 6437c7ba69c3 ("gpio: dwapb: Add wakeup source support")
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
This one-patch series fixes system wakeup for DesignWare APB GPIO
controllers that have real APB/debounce clocks.
The driver currently masks interrupts and disables its clocks from the
normal suspend callback. That is too early for GPIO consumers such as
gpio-keys, which may still enable IRQ wake or adjust the wake trigger type
from their own suspend callbacks. Once the DWAPB clocks are disabled, those
late wake updates cannot reliably reach the controller, and GPIO-key wake
from s2idle can fail.
Move the final interrupt masking and clock gating to suspend_noirq, after
consumers have completed their wake configuration. If at least one wake
line is armed, leave the clocks running and mark the device as part of the
wakeup path. Otherwise, gate the clocks in noirq and re-enable them from
resume_noirq before restoring the saved register state.
The patch also propagates aggregate wake enable/disable state to the
parent irqchip so a wake-capable parent interrupt is armed only while the
DWAPB controller has at least one local wake source.
Based on v7.2-rc1.
---
drivers/gpio/gpio-dwapb.c | 76 +++++++++++++++++++++++++++++++++++++++--------
1 file changed, 64 insertions(+), 12 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
index c1f3d83a67c1..504e2d779584 100644
--- a/drivers/gpio/gpio-dwapb.c
+++ b/drivers/gpio/gpio-dwapb.c
@@ -118,6 +118,7 @@ struct dwapb_gpio {
unsigned int flags;
struct reset_control *rst;
struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
+ bool clocks_on_for_wake;
struct dwapb_gpio_port ports[] __counted_by(nr_ports);
};
@@ -365,11 +366,21 @@ static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
struct dwapb_context *ctx = gpio->ports[0].ctx;
irq_hw_number_t bit = irqd_to_hwirq(d);
+ u32 wake_en = ctx->wake_en;
+ int err;
if (enable)
- ctx->wake_en |= BIT(bit);
+ wake_en |= BIT(bit);
else
- ctx->wake_en &= ~BIT(bit);
+ wake_en &= ~BIT(bit);
+
+ if (d->parent_data && !!ctx->wake_en != !!wake_en) {
+ err = irq_chip_set_wake_parent(d, enable);
+ if (err)
+ return err;
+ }
+
+ ctx->wake_en = wake_en;
return 0;
}
@@ -750,6 +761,8 @@ static int dwapb_gpio_suspend(struct device *dev)
int i;
scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
+ gpio->clocks_on_for_wake = false;
+
for (i = 0; i < gpio->nr_ports; i++) {
unsigned int offset;
unsigned int idx = gpio->ports[i].idx;
@@ -771,11 +784,38 @@ static int dwapb_gpio_suspend(struct device *dev)
ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int dwapb_gpio_suspend_noirq(struct device *dev)
+{
+ struct dwapb_gpio *gpio = dev_get_drvdata(dev);
+ struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
+ bool wake_enabled = false;
+ int i;
+
+ scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
+ for (i = 0; i < gpio->nr_ports; i++) {
+ unsigned int idx = gpio->ports[i].idx;
+ struct dwapb_context *ctx = gpio->ports[i].ctx;
- /* Mask out interrupts */
+ if (idx == 0) {
+ wake_enabled = ctx->wake_en;
dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
+ break;
}
}
+
+ gpio->clocks_on_for_wake = wake_enabled;
+ }
+
+ if (wake_enabled) {
+ device_set_wakeup_path(dev);
+ return 0;
}
clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
@@ -783,18 +823,27 @@ static int dwapb_gpio_suspend(struct device *dev)
return 0;
}
-static int dwapb_gpio_resume(struct device *dev)
+static int dwapb_gpio_resume_noirq(struct device *dev)
{
struct dwapb_gpio *gpio = dev_get_drvdata(dev);
- struct gpio_chip *gc = &gpio->ports[0].chip.gc;
- struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
- int i, err;
+ int err;
+
+ if (gpio->clocks_on_for_wake)
+ return 0;
err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
- if (err) {
+ if (err)
dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
- return err;
- }
+
+ return err;
+}
+
+static int dwapb_gpio_resume(struct device *dev)
+{
+ struct dwapb_gpio *gpio = dev_get_drvdata(dev);
+ struct gpio_chip *gc = &gpio->ports[0].chip.gc;
+ struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
+ int i;
guard(gpio_generic_lock_irqsave)(gen_gc);
@@ -828,8 +877,11 @@ static int dwapb_gpio_resume(struct device *dev)
return 0;
}
-static DEFINE_SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops,
- dwapb_gpio_suspend, dwapb_gpio_resume);
+static const struct dev_pm_ops dwapb_gpio_pm_ops = {
+ SYSTEM_SLEEP_PM_OPS(dwapb_gpio_suspend, dwapb_gpio_resume)
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(dwapb_gpio_suspend_noirq,
+ dwapb_gpio_resume_noirq)
+};
static struct platform_driver dwapb_gpio_driver = {
.driver = {
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260629-gpio-dwapb-wakeup-34a058f6c324
Best regards,
--
Jia Wang <wangjia@ultrarisc.com>
^ permalink raw reply related
* [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces
From: Juergen Gross @ 2026-06-29 6:04 UTC (permalink / raw)
To: linux-kernel, linux-pm, linux-edac, x86, linux-acpi, kvm,
linux-coco, linux-pci, virtualization, linux-ide, dri-devel,
linux-fbdev, linux-crypto, linux-gpio, linux-hyperv, linux-hwmon,
linux-perf-users, linux-mtd, platform-driver-x86
Cc: Juergen Gross, Rafael J. Wysocki, Daniel Lezcano, Zhang Rui,
Lukasz Luba, Jason Baron, Borislav Petkov, Tony Luck,
Yazen Ghannam, Len Brown, Pavel Machek, Thomas Gleixner,
Ingo Molnar, Dave Hansen, H. Peter Anvin, Sean Christopherson,
Paolo Bonzini, Kiryl Shutsemau, Rick Edgecombe, Pu Wen,
Bjorn Helgaas, Ajay Kaher, Alexey Makhalov,
Broadcom internal kernel review list, Viresh Kumar,
Reinette Chatre, Dave Martin, James Morse, Babu Moger,
Tony W Wang-oc, Damien Le Moal, Niklas Cassel, David Airlie,
Helge Deller, linux-geode, Olivia Mackall, Herbert Xu,
Linus Walleij, Bartosz Golaszewski, Arnd Bergmann,
Greg Kroah-Hartman, K. Y. Srinivasan, Haiyang Zhang, Wei Liu,
Dexuan Cui, Long Li, Guenter Roeck, Peter Zijlstra,
Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
James Clark, Josh Poimboeuf, Pawan Gupta, Vitaly Kuznetsov,
Andy Lutomirski, Boris Ostrovsky, Huang Rui, Mario Limonciello,
Perry Yuan, K Prateek Nayak, Srinivas Pandruvada,
Artem Bityutskiy, Artem Bityutskiy, Miquel Raynal,
Richard Weinberger, Vignesh Raghavendra, Ashok Raj, Hans de Goede,
Ilpo Järvinen, Rajneesh Bhardwaj, David E Box, xen-devel
For accessing the MSR registers on the local CPU, there are 2 types of
interfaces: the "modern" 64-bit ones (rdmsrq() etc.) and the 32-bit
ones (rdmsr() etc.) which are using the upper and lower 32-bit halves
of the 64-bit wide MSR register values.
The 32-bit interfaces are not optimal for 3 reasons:
- They are based on primitives using 64-bit sized values anyway.
- Modern x86 CPUs have added support for MSR access instructions using
an immediate value instead of a register for addressing the MSR,
while the value is in a 64-bit register.
- rdmsr() is a macro storing the upper and lower 32-bit halves in
variables specified as macro parameters. This is obscuring variable
assignment through a macro. Additionally rdmsrq() is mimicking this
pattern by being a macro, too, with the target variable specified as
a parameter as well.
For those reasons drop the 32-bit interfaces for accessing the x86 MSR
registers completely and only use the 64-bit variants.
This allows to switch all "high-level" MSR access macros to inline
functions in the end.
This series will be used as the base for further reorganisation of the
MSR access functions, especially for completely inlining the MSR
access instructions even with paravirtualization being active.
Note that most patches of this series are independent from each other.
Only the patches removing a specific interface (patches 7, 15, 26 and
30) and the last two patches of the series depend on all previous
patches.
Based on kernel 7.2-rc1, tested with and without parvirtualization
active, compile tested for x86 with 64- and 32-bit allyes and allno
configs.
Juergen Gross (32):
thermal/intel: Stop using 32-bit MSR interfaces
powercap: Stop using 32-bit MSR interfaces
edac: Stop using 32-bit MSR interfaces
acpi: Stop using 32-bit MSR interfaces
x86/mtrr: Stop using 32-bit MSR interfaces
x86/msr: Stop using 32-bit MSR interfaces in lib/msr-smp.c
x86/msr: Remove wrmsr_safe()
x86/mce: Stop using 32-bit MSR interfaces
KVM/x86: Stop using 32-bit MSR interfaces
x86/hygon: Stop using 32-bit MSR interfaces
x86/pci: Stop using 32-bit MSR interfaces
x86/amd: Stop using 32-bit MSR interfaces
x86/featctl: Stop using 32-bit MSR interfaces
x86/tsc: Stop using 32-bit MSR interfaces
x86/msr: Remove rdmsr_safe()
cpufreq: Stop using 32-bit MSR interfaces
x86/resctrl: Stop using 32-bit MSR interfaces
x86/apic: Stop using 32-bit MSR interfaces
x86/cpu: Stop using 32-bit MSR interfaces
drivers/ata: Stop using 32-bit MSR interfaces
agp/nvidia: Stop using 32-bit MSR interfaces
fbdev/geode: Stop using 32-bit MSR interfaces
hw_random/via-rng: Stop using 32-bit MSR interfaces
drivers/gpio: Stop using 32-bit MSR interfaces
drivers/misc: Stop using 32-bit MSR interfaces
x86/msr: Remove wrmsr()
x86/hyperv: Stop using 32-bit MSR interfaces
x86/olpc: Stop using 32-bit MSR interfaces
hwmon: Stop using 32-bit MSR interfaces
x86/msr: Remove rdmsr()
treewide: convert rdmsrq() from a macro to an inline function
x86/msr: Simplify some rdmsrq() use cases
arch/x86/coco/sev/core.c | 2 +-
arch/x86/events/amd/brs.c | 4 +-
arch/x86/events/amd/core.c | 8 +-
arch/x86/events/amd/ibs.c | 18 ++--
arch/x86/events/amd/lbr.c | 16 +--
arch/x86/events/amd/power.c | 8 +-
arch/x86/events/amd/uncore.c | 4 +-
arch/x86/events/core.c | 20 ++--
arch/x86/events/intel/core.c | 14 +--
arch/x86/events/intel/cstate.c | 5 +-
arch/x86/events/intel/ds.c | 2 +-
arch/x86/events/intel/knc.c | 10 +-
arch/x86/events/intel/lbr.c | 25 ++---
arch/x86/events/intel/p4.c | 6 +-
arch/x86/events/intel/p6.c | 4 +-
arch/x86/events/intel/pt.c | 12 +--
arch/x86/events/intel/uncore.c | 6 +-
arch/x86/events/intel/uncore_nhmex.c | 4 +-
arch/x86/events/intel/uncore_snb.c | 2 +-
arch/x86/events/intel/uncore_snbep.c | 6 +-
arch/x86/events/msr.c | 2 +-
arch/x86/events/perf_event.h | 6 +-
arch/x86/events/rapl.c | 6 +-
arch/x86/events/zhaoxin/core.c | 10 +-
arch/x86/hyperv/hv_apic.c | 17 ++--
arch/x86/hyperv/hv_init.c | 26 ++---
arch/x86/hyperv/hv_spinlock.c | 2 +-
arch/x86/include/asm/apic.h | 7 +-
arch/x86/include/asm/debugreg.h | 6 +-
arch/x86/include/asm/fsgsbase.h | 2 +-
arch/x86/include/asm/kvm_host.h | 5 +-
arch/x86/include/asm/msr.h | 39 +-------
arch/x86/include/asm/paravirt.h | 26 +----
arch/x86/include/asm/resctrl.h | 5 +-
arch/x86/kernel/acpi/sleep.c | 20 ++--
arch/x86/kernel/apic/apic.c | 45 ++++-----
arch/x86/kernel/apic/apic_numachip.c | 6 +-
arch/x86/kernel/cet.c | 2 +-
arch/x86/kernel/cpu/amd.c | 42 ++++----
arch/x86/kernel/cpu/aperfmperf.c | 8 +-
arch/x86/kernel/cpu/bugs.c | 12 +--
arch/x86/kernel/cpu/bus_lock.c | 8 +-
arch/x86/kernel/cpu/centaur.c | 35 +++----
arch/x86/kernel/cpu/common.c | 22 +++--
arch/x86/kernel/cpu/feat_ctl.c | 27 +++---
arch/x86/kernel/cpu/hygon.c | 9 +-
arch/x86/kernel/cpu/intel.c | 12 +--
arch/x86/kernel/cpu/intel_epb.c | 4 +-
arch/x86/kernel/cpu/mce/amd.c | 89 ++++++++---------
arch/x86/kernel/cpu/mce/core.c | 10 +-
arch/x86/kernel/cpu/mce/inject.c | 2 +-
arch/x86/kernel/cpu/mce/intel.c | 18 ++--
arch/x86/kernel/cpu/mce/p5.c | 16 +--
arch/x86/kernel/cpu/mce/winchip.c | 10 +-
arch/x86/kernel/cpu/microcode/intel.c | 2 +-
arch/x86/kernel/cpu/mshyperv.c | 6 +-
arch/x86/kernel/cpu/mtrr/amd.c | 36 ++++---
arch/x86/kernel/cpu/mtrr/centaur.c | 18 ++--
arch/x86/kernel/cpu/mtrr/cleanup.c | 18 ++--
arch/x86/kernel/cpu/mtrr/generic.c | 97 ++++++++++---------
arch/x86/kernel/cpu/mtrr/mtrr.c | 4 +-
arch/x86/kernel/cpu/resctrl/core.c | 9 +-
arch/x86/kernel/cpu/resctrl/monitor.c | 27 +++---
arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 12 +--
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 2 +-
arch/x86/kernel/cpu/topology.c | 2 +-
arch/x86/kernel/cpu/topology_amd.c | 4 +-
arch/x86/kernel/cpu/transmeta.c | 9 +-
arch/x86/kernel/cpu/tsx.c | 10 +-
arch/x86/kernel/cpu/umwait.c | 2 +-
arch/x86/kernel/cpu/zhaoxin.c | 12 +--
arch/x86/kernel/fpu/core.c | 2 +-
arch/x86/kernel/hpet.c | 2 +-
arch/x86/kernel/kvm.c | 2 +-
arch/x86/kernel/mmconf-fam10h_64.c | 6 +-
arch/x86/kernel/process.c | 4 +-
arch/x86/kernel/process_64.c | 14 +--
arch/x86/kernel/shstk.c | 8 +-
arch/x86/kernel/traps.c | 4 +-
arch/x86/kernel/tsc.c | 8 +-
arch/x86/kernel/tsc_msr.c | 15 +--
arch/x86/kernel/tsc_sync.c | 6 +-
arch/x86/kvm/svm/pmu.c | 4 +-
arch/x86/kvm/svm/svm.c | 4 +-
arch/x86/kvm/vmx/nested.c | 4 +-
arch/x86/kvm/vmx/pmu_intel.c | 8 +-
arch/x86/kvm/vmx/sgx.c | 6 +-
arch/x86/kvm/vmx/vmx.c | 54 ++++++-----
arch/x86/kvm/x86.c | 12 +--
arch/x86/lib/insn-eval.c | 6 +-
arch/x86/lib/msr-smp.c | 8 +-
arch/x86/mm/pat/memtype.c | 2 +-
arch/x86/pci/amd_bus.c | 8 +-
arch/x86/pci/mmconfig-shared.c | 8 +-
arch/x86/platform/olpc/olpc-xo1-rtc.c | 6 +-
arch/x86/platform/olpc/olpc-xo1-sci.c | 11 ++-
arch/x86/power/cpu.c | 10 +-
arch/x86/realmode/init.c | 2 +-
arch/x86/virt/hw.c | 8 +-
arch/x86/virt/svm/sev.c | 18 ++--
arch/x86/virt/vmx/tdx/tdx.c | 8 +-
arch/x86/xen/suspend.c | 2 +-
drivers/acpi/processor_perflib.c | 11 ++-
drivers/acpi/processor_throttling.c | 14 +--
drivers/ata/pata_cs5535.c | 20 ++--
drivers/ata/pata_cs5536.c | 17 ++--
drivers/char/agp/nvidia-agp.c | 32 +++---
drivers/char/hw_random/via-rng.c | 29 +++---
drivers/cpufreq/acpi-cpufreq.c | 24 ++---
drivers/cpufreq/amd-pstate.c | 4 +-
drivers/cpufreq/e_powersaver.c | 52 +++++-----
drivers/cpufreq/intel_pstate.c | 30 +++---
drivers/cpufreq/longhaul.c | 23 ++---
drivers/cpufreq/longrun.c | 78 ++++++++-------
drivers/cpufreq/powernow-k6.c | 12 +--
drivers/cpufreq/powernow-k7.c | 10 +-
drivers/cpufreq/powernow-k8.c | 67 ++++++-------
drivers/cpufreq/speedstep-centrino.c | 16 +--
drivers/cpufreq/speedstep-lib.c | 63 ++++++------
drivers/edac/amd64_edac.c | 6 +-
drivers/edac/ie31200_edac.c | 10 +-
drivers/edac/mce_amd.c | 8 +-
drivers/gpio/gpio-cs5535.c | 10 +-
drivers/hv/mshv_vtl_main.c | 2 +-
drivers/hwmon/hwmon-vid.c | 11 ++-
drivers/idle/intel_idle.c | 26 ++---
drivers/misc/cs5535-mfgpt.c | 33 +++----
drivers/mtd/nand/raw/cs553x_nand.c | 6 +-
drivers/platform/x86/intel/ifs/load.c | 10 +-
drivers/platform/x86/intel/ifs/runtest.c | 8 +-
drivers/platform/x86/intel/pmc/cnp.c | 2 +-
.../intel/speed_select_if/isst_if_mbox_msr.c | 6 +-
.../intel/speed_select_if/isst_tpmi_core.c | 2 +-
drivers/platform/x86/intel_ips.c | 20 ++--
drivers/powercap/intel_rapl_common.c | 20 ++--
drivers/powercap/intel_rapl_msr.c | 2 +-
drivers/thermal/intel/intel_hfi.c | 8 +-
drivers/thermal/intel/intel_tcc.c | 10 +-
drivers/thermal/intel/therm_throt.c | 74 +++++++-------
drivers/thermal/intel/x86_pkg_temp_thermal.c | 32 +++---
drivers/video/fbdev/geode/display_gx.c | 8 +-
drivers/video/fbdev/geode/gxfb_core.c | 2 +-
drivers/video/fbdev/geode/lxfb_ops.c | 50 +++++-----
drivers/video/fbdev/geode/suspend_gx.c | 24 ++---
drivers/video/fbdev/geode/video_gx.c | 8 +-
include/linux/cs5535.h | 10 +-
146 files changed, 1044 insertions(+), 1128 deletions(-)
--
2.54.0
^ permalink raw reply
* [PATCH 24/32] drivers/gpio: Stop using 32-bit MSR interfaces
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, linux-gpio
Cc: Juergen Gross, Linus Walleij, Bartosz Golaszewski
In-Reply-To: <20260629060526.3638272-1-jgross@suse.com>
The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
drivers/gpio/gpio-cs5535.c | 10 +++++-----
include/linux/cs5535.h | 10 +++++-----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/gpio-cs5535.c b/drivers/gpio/gpio-cs5535.c
index 5f5373d86397..a97ec7561889 100644
--- a/drivers/gpio/gpio-cs5535.c
+++ b/drivers/gpio/gpio-cs5535.c
@@ -143,17 +143,17 @@ EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
int cs5535_gpio_set_irq(unsigned group, unsigned irq)
{
- uint32_t lo, hi;
+ struct msr val;
if (group > 7 || irq > 15)
return -EINVAL;
- rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
+ rdmsrq(MSR_PIC_ZSEL_HIGH, val.q);
- lo &= ~(0xF << (group * 4));
- lo |= (irq & 0xF) << (group * 4);
+ val.l &= ~(0xF << (group * 4));
+ val.l |= (irq & 0xF) << (group * 4);
- wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
+ wrmsrq(MSR_PIC_ZSEL_HIGH, val.q);
return 0;
}
EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
diff --git a/include/linux/cs5535.h b/include/linux/cs5535.h
index 2be1120174eb..5ec2aca537bb 100644
--- a/include/linux/cs5535.h
+++ b/include/linux/cs5535.h
@@ -49,12 +49,12 @@
static inline int cs5535_pic_unreqz_select_high(unsigned int group,
unsigned int irq)
{
- uint32_t lo, hi;
+ struct msr val;
- rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
- lo &= ~(0xF << (group * 4));
- lo |= (irq & 0xF) << (group * 4);
- wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
+ rdmsrq(MSR_PIC_ZSEL_HIGH, val.q);
+ val.l &= ~(0xF << (group * 4));
+ val.l |= (irq & 0xF) << (group * 4);
+ wrmsrq(MSR_PIC_ZSEL_HIGH, val.q);
return 0;
}
--
2.54.0
^ permalink raw reply related
* [PATCH 31/32] treewide: convert rdmsrq() from a macro to an inline function
From: Juergen Gross @ 2026-06-29 6:05 UTC (permalink / raw)
To: linux-kernel, x86, linux-perf-users, linux-hyperv, kvm,
virtualization, linux-edac, linux-pci, linux-pm, linux-coco,
linux-acpi, linux-ide, dri-devel, linux-crypto, linux-gpio,
linux-hwmon, linux-mtd, platform-driver-x86, linux-fbdev
Cc: Juergen Gross, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Peter Zijlstra,
Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
James Clark, K. Y. Srinivasan, Haiyang Zhang, Wei Liu, Dexuan Cui,
Long Li, Sean Christopherson, Paolo Bonzini, Ajay Kaher,
Alexey Makhalov, Broadcom internal kernel review list,
Josh Poimboeuf, Pawan Gupta, Pu Wen, Tony Luck, Reinette Chatre,
Dave Martin, James Morse, Babu Moger, Tony W Wang-oc,
Vitaly Kuznetsov, Andy Lutomirski, Bjorn Helgaas,
Rafael J. Wysocki, Pavel Machek, Kiryl Shutsemau, Rick Edgecombe,
Boris Ostrovsky, Len Brown, Damien Le Moal, Niklas Cassel,
David Airlie, Olivia Mackall, Herbert Xu, Viresh Kumar, Huang Rui,
Mario Limonciello, Perry Yuan, K Prateek Nayak,
Srinivas Pandruvada, Yazen Ghannam, Linus Walleij,
Bartosz Golaszewski, Guenter Roeck, Artem Bityutskiy,
Artem Bityutskiy, Arnd Bergmann, Greg Kroah-Hartman,
Miquel Raynal, Richard Weinberger, Vignesh Raghavendra, Ashok Raj,
Hans de Goede, Ilpo Järvinen, Rajneesh Bhardwaj, David E Box,
Daniel Lezcano, Zhang Rui, Lukasz Luba, Helge Deller, xen-devel,
linux-geode
In-Reply-To: <20260629060526.3638272-1-jgross@suse.com>
Today rdmsrq() is a macro using its second parameter as the target for
storing the read MSR value.
Convert rdmsrq() to an inline function returning the MSR value.
The users have been converted using the following semantic patch:
// Options: --include-headers
virtual patch
virtual report
@@
expression msr, val;
@@
(
- rdmsrq(msr,val)
+ val = rdmsrq(msr)
)
Signed-off-by: Juergen Gross <jgross@suse.com>
---
arch/x86/coco/sev/core.c | 2 +-
arch/x86/events/amd/brs.c | 4 +--
arch/x86/events/amd/core.c | 4 +--
arch/x86/events/amd/ibs.c | 18 +++++-----
arch/x86/events/amd/lbr.c | 8 ++---
arch/x86/events/amd/power.c | 8 ++---
arch/x86/events/amd/uncore.c | 4 +--
arch/x86/events/core.c | 20 +++++------
arch/x86/events/intel/core.c | 10 +++---
arch/x86/events/intel/cstate.c | 2 +-
arch/x86/events/intel/ds.c | 2 +-
arch/x86/events/intel/knc.c | 6 ++--
arch/x86/events/intel/lbr.c | 14 ++++----
arch/x86/events/intel/p4.c | 6 ++--
arch/x86/events/intel/p6.c | 4 +--
arch/x86/events/intel/pt.c | 12 +++----
arch/x86/events/intel/uncore.c | 2 +-
arch/x86/events/intel/uncore_nhmex.c | 4 +--
arch/x86/events/intel/uncore_snb.c | 2 +-
arch/x86/events/intel/uncore_snbep.c | 6 ++--
arch/x86/events/msr.c | 2 +-
arch/x86/events/perf_event.h | 6 ++--
arch/x86/events/rapl.c | 4 +--
arch/x86/events/zhaoxin/core.c | 6 ++--
arch/x86/hyperv/hv_apic.c | 6 ++--
arch/x86/hyperv/hv_init.c | 26 +++++++-------
arch/x86/hyperv/hv_spinlock.c | 2 +-
arch/x86/include/asm/apic.h | 4 +--
arch/x86/include/asm/debugreg.h | 2 +-
arch/x86/include/asm/fsgsbase.h | 2 +-
arch/x86/include/asm/kvm_host.h | 2 +-
arch/x86/include/asm/msr.h | 15 ++++----
arch/x86/include/asm/paravirt.h | 8 ++---
arch/x86/kernel/apic/apic.c | 14 ++++----
arch/x86/kernel/apic/apic_numachip.c | 6 ++--
arch/x86/kernel/cet.c | 2 +-
arch/x86/kernel/cpu/amd.c | 14 ++++----
arch/x86/kernel/cpu/aperfmperf.c | 8 ++---
arch/x86/kernel/cpu/bugs.c | 12 +++----
arch/x86/kernel/cpu/bus_lock.c | 8 ++---
arch/x86/kernel/cpu/centaur.c | 8 ++---
arch/x86/kernel/cpu/common.c | 12 +++----
arch/x86/kernel/cpu/feat_ctl.c | 4 +--
arch/x86/kernel/cpu/hygon.c | 4 +--
arch/x86/kernel/cpu/intel.c | 6 ++--
arch/x86/kernel/cpu/intel_epb.c | 4 +--
arch/x86/kernel/cpu/mce/amd.c | 4 +--
arch/x86/kernel/cpu/mce/core.c | 8 ++---
arch/x86/kernel/cpu/mce/inject.c | 2 +-
arch/x86/kernel/cpu/mce/intel.c | 18 +++++-----
arch/x86/kernel/cpu/mce/p5.c | 8 ++---
arch/x86/kernel/cpu/mce/winchip.c | 2 +-
arch/x86/kernel/cpu/microcode/intel.c | 2 +-
arch/x86/kernel/cpu/mshyperv.c | 6 ++--
arch/x86/kernel/cpu/mtrr/amd.c | 4 +--
arch/x86/kernel/cpu/mtrr/cleanup.c | 4 +--
arch/x86/kernel/cpu/mtrr/generic.c | 32 ++++++++---------
arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +-
arch/x86/kernel/cpu/resctrl/core.c | 2 +-
arch/x86/kernel/cpu/resctrl/monitor.c | 4 +--
arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 4 +--
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 2 +-
arch/x86/kernel/cpu/topology.c | 2 +-
arch/x86/kernel/cpu/topology_amd.c | 4 +--
arch/x86/kernel/cpu/transmeta.c | 2 +-
arch/x86/kernel/cpu/tsx.c | 10 +++---
arch/x86/kernel/cpu/umwait.c | 2 +-
arch/x86/kernel/cpu/zhaoxin.c | 4 +--
arch/x86/kernel/fpu/core.c | 2 +-
arch/x86/kernel/hpet.c | 2 +-
arch/x86/kernel/kvm.c | 2 +-
arch/x86/kernel/mmconf-fam10h_64.c | 6 ++--
arch/x86/kernel/process.c | 4 +--
arch/x86/kernel/process_64.c | 14 ++++----
arch/x86/kernel/shstk.c | 8 ++---
arch/x86/kernel/traps.c | 4 +--
arch/x86/kernel/tsc.c | 2 +-
arch/x86/kernel/tsc_msr.c | 6 ++--
arch/x86/kernel/tsc_sync.c | 6 ++--
arch/x86/kvm/svm/pmu.c | 4 +--
arch/x86/kvm/svm/svm.c | 4 +--
arch/x86/kvm/vmx/nested.c | 4 +--
arch/x86/kvm/vmx/pmu_intel.c | 8 ++---
arch/x86/kvm/vmx/sgx.c | 6 ++--
arch/x86/kvm/vmx/vmx.c | 36 +++++++++----------
arch/x86/kvm/x86.c | 8 ++---
arch/x86/lib/insn-eval.c | 6 ++--
arch/x86/lib/msr-smp.c | 2 +-
arch/x86/mm/pat/memtype.c | 2 +-
arch/x86/pci/amd_bus.c | 8 ++---
arch/x86/platform/olpc/olpc-xo1-rtc.c | 6 ++--
arch/x86/platform/olpc/olpc-xo1-sci.c | 2 +-
arch/x86/power/cpu.c | 10 +++---
arch/x86/realmode/init.c | 2 +-
arch/x86/virt/hw.c | 8 ++---
arch/x86/virt/svm/sev.c | 18 +++++-----
arch/x86/virt/vmx/tdx/tdx.c | 2 +-
arch/x86/xen/suspend.c | 2 +-
drivers/acpi/processor_perflib.c | 2 +-
drivers/ata/pata_cs5535.c | 4 +--
drivers/ata/pata_cs5536.c | 2 +-
drivers/char/agp/nvidia-agp.c | 6 ++--
drivers/char/hw_random/via-rng.c | 4 +--
drivers/cpufreq/acpi-cpufreq.c | 8 ++---
drivers/cpufreq/amd-pstate.c | 4 +--
drivers/cpufreq/e_powersaver.c | 20 +++++------
drivers/cpufreq/intel_pstate.c | 30 ++++++++--------
drivers/cpufreq/longhaul.c | 12 +++----
drivers/cpufreq/longrun.c | 16 ++++-----
drivers/cpufreq/powernow-k7.c | 10 +++---
drivers/cpufreq/powernow-k8.c | 8 ++---
drivers/cpufreq/speedstep-centrino.c | 4 +--
drivers/cpufreq/speedstep-lib.c | 14 ++++----
drivers/edac/amd64_edac.c | 6 ++--
drivers/gpio/gpio-cs5535.c | 2 +-
drivers/hv/mshv_vtl_main.c | 2 +-
drivers/hwmon/hwmon-vid.c | 4 +--
drivers/idle/intel_idle.c | 26 +++++++-------
drivers/misc/cs5535-mfgpt.c | 6 ++--
drivers/mtd/nand/raw/cs553x_nand.c | 6 ++--
drivers/platform/x86/intel/ifs/load.c | 10 +++---
drivers/platform/x86/intel/ifs/runtest.c | 8 ++---
drivers/platform/x86/intel/pmc/cnp.c | 2 +-
.../intel/speed_select_if/isst_if_mbox_msr.c | 6 ++--
.../intel/speed_select_if/isst_tpmi_core.c | 2 +-
drivers/platform/x86/intel_ips.c | 20 +++++------
drivers/powercap/intel_rapl_msr.c | 2 +-
drivers/thermal/intel/intel_hfi.c | 8 ++---
drivers/thermal/intel/therm_throt.c | 18 +++++-----
drivers/thermal/intel/x86_pkg_temp_thermal.c | 6 ++--
drivers/video/fbdev/geode/display_gx.c | 2 +-
drivers/video/fbdev/geode/gxfb_core.c | 2 +-
drivers/video/fbdev/geode/lxfb_ops.c | 18 +++++-----
drivers/video/fbdev/geode/suspend_gx.c | 8 ++---
drivers/video/fbdev/geode/video_gx.c | 8 ++---
include/linux/cs5535.h | 2 +-
136 files changed, 482 insertions(+), 483 deletions(-)
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
index ecd77d3217f3..0a67c71a6ba0 100644
--- a/arch/x86/coco/sev/core.c
+++ b/arch/x86/coco/sev/core.c
@@ -2037,7 +2037,7 @@ void __init snp_secure_tsc_init(void)
secrets = (__force struct snp_secrets_page *)mem;
setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
- rdmsrq(MSR_AMD64_GUEST_TSC_FREQ, tsc_freq_mhz);
+ tsc_freq_mhz = rdmsrq(MSR_AMD64_GUEST_TSC_FREQ);
/* Extract the GUEST TSC MHZ from BIT[17:0], rest is reserved space */
tsc_freq_mhz &= GENMASK_ULL(17, 0);
diff --git a/arch/x86/events/amd/brs.c b/arch/x86/events/amd/brs.c
index 06f35a6b58a5..35c56bcffd92 100644
--- a/arch/x86/events/amd/brs.c
+++ b/arch/x86/events/amd/brs.c
@@ -325,7 +325,7 @@ void amd_brs_drain(void)
u32 brs_idx = tos - i;
u64 from, to;
- rdmsrq(brs_to(brs_idx), to);
+ to = rdmsrq(brs_to(brs_idx));
/* Entry does not belong to us (as marked by kernel) */
if (to == BRS_POISON)
@@ -341,7 +341,7 @@ void amd_brs_drain(void)
if (!amd_brs_match_plm(event, to))
continue;
- rdmsrq(brs_from(brs_idx), from);
+ from = rdmsrq(brs_from(brs_idx));
perf_clear_branch_entry_bitfields(br+nr);
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 6569048a8c1c..ee08ed4f41ec 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -663,7 +663,7 @@ static inline u64 amd_pmu_get_global_status(void)
u64 status;
/* PerfCntrGlobalStatus is read-only */
- rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, status);
+ status = rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS);
return status;
}
@@ -683,7 +683,7 @@ static bool amd_pmu_test_overflow_topbit(int idx)
{
u64 counter;
- rdmsrq(x86_pmu_event_addr(idx), counter);
+ counter = rdmsrq(x86_pmu_event_addr(idx));
return !(counter & BIT_ULL(x86_pmu.cntval_bits - 1));
}
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index 3531f9c23b8c..17eab32164df 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -505,7 +505,7 @@ perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
* prev count manually on overflow.
*/
while (!perf_event_try_update(event, count, 64)) {
- rdmsrq(event->hw.config_base, *config);
+ *config = rdmsrq(event->hw.config_base);
count = perf_ibs->get_count(*config);
}
}
@@ -610,7 +610,7 @@ static void perf_ibs_stop(struct perf_event *event, int flags)
if (!stopping && (hwc->state & PERF_HES_UPTODATE))
return;
- rdmsrq(hwc->config_base, config);
+ config = rdmsrq(hwc->config_base);
if (stopping) {
/*
@@ -1437,7 +1437,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
hwc = &event->hw;
msr = hwc->config_base;
buf = ibs_data.regs;
- rdmsrq(msr, *buf);
+ *buf = rdmsrq(msr);
if (!(*buf++ & perf_ibs->valid_mask))
goto fail;
@@ -1455,7 +1455,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
offset_max = perf_ibs_get_offset_max(perf_ibs, event, check_rip);
do {
- rdmsrq(msr + offset, *buf++);
+ *buf++ = rdmsrq(msr + offset);
size++;
offset = find_next_bit(perf_ibs->offset_mask,
perf_ibs->offset_max,
@@ -1497,17 +1497,17 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
if (event->attr.sample_type & PERF_SAMPLE_RAW) {
if (perf_ibs == &perf_ibs_op) {
if (ibs_caps & IBS_CAPS_BRNTRGT) {
- rdmsrq(MSR_AMD64_IBSBRTARGET, *buf++);
+ *buf++ = rdmsrq(MSR_AMD64_IBSBRTARGET);
br_target_idx = size;
size++;
}
if (ibs_caps & IBS_CAPS_OPDATA4) {
- rdmsrq(MSR_AMD64_IBSOPDATA4, *buf++);
+ *buf++ = rdmsrq(MSR_AMD64_IBSOPDATA4);
size++;
}
}
if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {
- rdmsrq(MSR_AMD64_ICIBSEXTDCTL, *buf++);
+ *buf++ = rdmsrq(MSR_AMD64_ICIBSEXTDCTL);
size++;
}
}
@@ -1768,7 +1768,7 @@ static inline int ibs_eilvt_valid(void)
preempt_disable();
- rdmsrq(MSR_AMD64_IBSCTL, val);
+ val = rdmsrq(MSR_AMD64_IBSCTL);
offset = val & IBSCTL_LVT_OFFSET_MASK;
if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
@@ -1883,7 +1883,7 @@ static inline int get_ibs_lvt_offset(void)
{
u64 val;
- rdmsrq(MSR_AMD64_IBSCTL, val);
+ val = rdmsrq(MSR_AMD64_IBSCTL);
if (!(val & IBSCTL_LVT_OFFSET_VALID))
return -EINVAL;
diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c
index 5b437dc8e4ce..0b6aec1e5bf1 100644
--- a/arch/x86/events/amd/lbr.c
+++ b/arch/x86/events/amd/lbr.c
@@ -76,7 +76,7 @@ static __always_inline u64 amd_pmu_lbr_get_from(unsigned int idx)
{
u64 val;
- rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2, val);
+ val = rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2);
return val;
}
@@ -85,7 +85,7 @@ static __always_inline u64 amd_pmu_lbr_get_to(unsigned int idx)
{
u64 val;
- rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1, val);
+ val = rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1);
return val;
}
@@ -403,11 +403,11 @@ void amd_pmu_lbr_enable_all(void)
}
if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {
- rdmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
+ dbg_ctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
}
- rdmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
+ dbg_extn_cfg = rdmsrq(MSR_AMD_DBG_EXTN_CFG);
wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN);
}
diff --git a/arch/x86/events/amd/power.c b/arch/x86/events/amd/power.c
index 744dffa42dee..553a6d0c8a14 100644
--- a/arch/x86/events/amd/power.c
+++ b/arch/x86/events/amd/power.c
@@ -52,8 +52,8 @@ static void event_update(struct perf_event *event)
prev_pwr_acc = hwc->pwr_acc;
prev_ptsc = hwc->ptsc;
- rdmsrq(MSR_F15H_CU_PWR_ACCUMULATOR, new_pwr_acc);
- rdmsrq(MSR_F15H_PTSC, new_ptsc);
+ new_pwr_acc = rdmsrq(MSR_F15H_CU_PWR_ACCUMULATOR);
+ new_ptsc = rdmsrq(MSR_F15H_PTSC);
/*
* Calculate the CU power consumption over a time period, the unit of
@@ -79,8 +79,8 @@ static void __pmu_event_start(struct perf_event *event)
event->hw.state = 0;
- rdmsrq(MSR_F15H_PTSC, event->hw.ptsc);
- rdmsrq(MSR_F15H_CU_PWR_ACCUMULATOR, event->hw.pwr_acc);
+ event->hw.ptsc = rdmsrq(MSR_F15H_PTSC);
+ event->hw.pwr_acc = rdmsrq(MSR_F15H_CU_PWR_ACCUMULATOR);
}
static void pmu_event_start(struct perf_event *event, int mode)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index dbc00b6dd69e..eca29ba9a795 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -151,7 +151,7 @@ static void amd_uncore_read(struct perf_event *event)
* read counts directly from the corresponding PERF_CTR.
*/
if (hwc->event_base_rdpmc < 0)
- rdmsrq(hwc->event_base, new);
+ new = rdmsrq(hwc->event_base);
else
new = rdpmc(hwc->event_base_rdpmc);
@@ -967,7 +967,7 @@ static void amd_uncore_umc_read(struct perf_event *event)
* UMC counters do not have RDPMC assignments. Read counts directly
* from the corresponding PERF_CTR.
*/
- rdmsrq(hwc->event_base, new);
+ new = rdmsrq(hwc->event_base);
/*
* Unlike the other uncore counters, UMC counters saturate and set the
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index d1af33d96d0a..b97f4cb1ca5f 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -713,7 +713,7 @@ void x86_pmu_disable_all(void)
if (!test_bit(idx, cpuc->active_mask))
continue;
- rdmsrq(x86_pmu_config_addr(idx), val);
+ val = rdmsrq(x86_pmu_config_addr(idx));
if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
continue;
val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
@@ -1578,10 +1578,10 @@ void perf_event_print_debug(void)
return;
if (x86_pmu.version >= 2) {
- rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
- rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status);
- rdmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
- rdmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
+ ctrl = rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL);
+ status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
+ overflow = rdmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL);
+ fixed = rdmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL);
pr_info("\n");
pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
@@ -1589,19 +1589,19 @@ void perf_event_print_debug(void)
pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
if (pebs_constraints) {
- rdmsrq(MSR_IA32_PEBS_ENABLE, pebs);
+ pebs = rdmsrq(MSR_IA32_PEBS_ENABLE);
pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
}
if (x86_pmu.lbr_nr) {
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
+ debugctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
}
}
pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
for_each_set_bit(idx, cntr_mask, X86_PMC_IDX_MAX) {
- rdmsrq(x86_pmu_config_addr(idx), pmc_ctrl);
- rdmsrq(x86_pmu_event_addr(idx), pmc_count);
+ pmc_ctrl = rdmsrq(x86_pmu_config_addr(idx));
+ pmc_count = rdmsrq(x86_pmu_event_addr(idx));
prev_left = per_cpu(pmc_prev_left[idx], cpu);
@@ -1615,7 +1615,7 @@ void perf_event_print_debug(void)
for_each_set_bit(idx, fixed_cntr_mask, X86_PMC_IDX_MAX) {
if (fixed_counter_disabled(idx, cpuc->pmu))
continue;
- rdmsrq(x86_pmu_fixed_ctr_addr(idx), pmc_count);
+ pmc_count = rdmsrq(x86_pmu_fixed_ctr_addr(idx));
pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
cpu, idx, pmc_count);
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2b35483e2b70..c6fc2d9079d9 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2965,7 +2965,7 @@ static inline u64 intel_pmu_get_status(void)
{
u64 status;
- rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status);
+ status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
return status;
}
@@ -3494,7 +3494,7 @@ static void intel_pmu_enable_event_ext(struct perf_event *event)
else
new.thresh = ARCH_PEBS_THRESH_SINGLE;
- rdmsrq(MSR_IA32_PEBS_INDEX, old.whole);
+ old.whole = rdmsrq(MSR_IA32_PEBS_INDEX);
if (new.thresh != old.thresh || !old.en) {
if (old.thresh == ARCH_PEBS_THRESH_MULTI && old.wr > 0) {
/*
@@ -6239,7 +6239,7 @@ static void update_pmu_cap(struct pmu *pmu)
if (!intel_pmu_broken_perf_cap()) {
/* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */
- rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities);
+ hybrid(pmu, intel_cap).capabilities = rdmsrq(MSR_IA32_PERF_CAPABILITIES);
}
}
@@ -6387,7 +6387,7 @@ static void intel_pmu_cpu_starting(int cpu)
if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
union perf_capabilities perf_cap;
- rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
+ perf_cap.capabilities = rdmsrq(MSR_IA32_PERF_CAPABILITIES);
if (!perf_cap.perf_metrics) {
x86_pmu.intel_cap.perf_metrics = 0;
x86_pmu.intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;
@@ -7931,7 +7931,7 @@ __init int intel_pmu_init(void)
if (boot_cpu_has(X86_FEATURE_PDCM)) {
u64 capabilities;
- rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities);
+ capabilities = rdmsrq(MSR_IA32_PERF_CAPABILITIES);
x86_pmu.intel_cap.capabilities = capabilities;
}
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index f3d5ee07f8f2..69eb6cf51d3b 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -324,7 +324,7 @@ static inline u64 cstate_pmu_read_counter(struct perf_event *event)
{
u64 val;
- rdmsrq(event->hw.event_base, val);
+ val = rdmsrq(event->hw.event_base);
return val;
}
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 91a093d8cf2e..0b3f2bf101f2 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -3244,7 +3244,7 @@ static void intel_pmu_drain_arch_pebs(struct pt_regs *iregs,
void *base, *at, *top;
u64 mask;
- rdmsrq(MSR_IA32_PEBS_INDEX, index.whole);
+ index.whole = rdmsrq(MSR_IA32_PEBS_INDEX);
if (unlikely(!index.wr)) {
intel_pmu_pebs_event_update_no_drain(cpuc, X86_PMC_IDX_MAX);
diff --git a/arch/x86/events/intel/knc.c b/arch/x86/events/intel/knc.c
index e887adc108ac..c4f81215f758 100644
--- a/arch/x86/events/intel/knc.c
+++ b/arch/x86/events/intel/knc.c
@@ -160,7 +160,7 @@ static void knc_pmu_disable_all(void)
{
u64 val;
- rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
+ val = rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL);
val &= ~(KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1);
wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
}
@@ -169,7 +169,7 @@ static void knc_pmu_enable_all(int added)
{
u64 val;
- rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
+ val = rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL);
val |= (KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1);
wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val);
}
@@ -201,7 +201,7 @@ static inline u64 knc_pmu_get_status(void)
{
u64 status;
- rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_STATUS, status);
+ status = rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_STATUS);
return status;
}
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index cae2e02fe6cc..e65a4ed121d7 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -141,7 +141,7 @@ static void __intel_pmu_lbr_enable(bool pmi)
if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && !pmi && cpuc->lbr_sel)
wrmsrq(MSR_LBR_SELECT, lbr_select);
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
+ debugctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
orig_debugctl = debugctl;
if (!static_cpu_has(X86_FEATURE_ARCH_LBR))
@@ -211,7 +211,7 @@ static inline u64 intel_pmu_lbr_tos(void)
{
u64 tos;
- rdmsrq(x86_pmu.lbr_tos, tos);
+ tos = rdmsrq(x86_pmu.lbr_tos);
return tos;
}
@@ -304,7 +304,7 @@ static __always_inline u64 rdlbr_from(unsigned int idx, struct lbr_entry *lbr)
if (lbr)
return lbr->from;
- rdmsrq(x86_pmu.lbr_from + idx, val);
+ val = rdmsrq(x86_pmu.lbr_from + idx);
return lbr_from_signext_quirk_rd(val);
}
@@ -316,7 +316,7 @@ static __always_inline u64 rdlbr_to(unsigned int idx, struct lbr_entry *lbr)
if (lbr)
return lbr->to;
- rdmsrq(x86_pmu.lbr_to + idx, val);
+ val = rdmsrq(x86_pmu.lbr_to + idx);
return val;
}
@@ -328,7 +328,7 @@ static __always_inline u64 rdlbr_info(unsigned int idx, struct lbr_entry *lbr)
if (lbr)
return lbr->info;
- rdmsrq(x86_pmu.lbr_info + idx, val);
+ val = rdmsrq(x86_pmu.lbr_info + idx);
return val;
}
@@ -477,7 +477,7 @@ void intel_pmu_lbr_save(void *ctx)
task_ctx->tos = tos;
if (cpuc->lbr_select)
- rdmsrq(MSR_LBR_SELECT, task_ctx->lbr_sel);
+ task_ctx->lbr_sel = rdmsrq(MSR_LBR_SELECT);
}
static void intel_pmu_arch_lbr_save(void *ctx)
@@ -754,7 +754,7 @@ void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
u64 lbr;
} msr_lastbranch;
- rdmsrq(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
+ msr_lastbranch.lbr = rdmsrq(x86_pmu.lbr_from + lbr_idx);
perf_clear_branch_entry_bitfields(br);
diff --git a/arch/x86/events/intel/p4.c b/arch/x86/events/intel/p4.c
index 5368dc31787c..e675e85682f1 100644
--- a/arch/x86/events/intel/p4.c
+++ b/arch/x86/events/intel/p4.c
@@ -860,7 +860,7 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
u64 v;
/* an official way for overflow indication */
- rdmsrq(hwc->config_base, v);
+ v = rdmsrq(hwc->config_base);
if (v & P4_CCCR_OVF) {
wrmsrq(hwc->config_base, v & ~P4_CCCR_OVF);
return 1;
@@ -873,7 +873,7 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
* the counter has reached zero value and continued counting before
* real NMI signal was received:
*/
- rdmsrq(hwc->event_base, v);
+ v = rdmsrq(hwc->event_base);
if (!(v & ARCH_P4_UNFLAGGED_BIT))
return 1;
@@ -1373,7 +1373,7 @@ __init int p4_pmu_init(void)
/* If we get stripped -- indexing fails */
BUILD_BUG_ON(ARCH_P4_MAX_CCCR > INTEL_PMC_MAX_GENERIC);
- rdmsrq(MSR_IA32_MISC_ENABLE, misc);
+ misc = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(misc & MSR_IA32_MISC_ENABLE_EMON)) {
pr_cont("unsupported Netburst CPU model %d ",
boot_cpu_data.x86_model);
diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c
index fb991e0ac614..4268b576b5d8 100644
--- a/arch/x86/events/intel/p6.c
+++ b/arch/x86/events/intel/p6.c
@@ -143,7 +143,7 @@ static void p6_pmu_disable_all(void)
u64 val;
/* p6 only has one enable register */
- rdmsrq(MSR_P6_EVNTSEL0, val);
+ val = rdmsrq(MSR_P6_EVNTSEL0);
val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
wrmsrq(MSR_P6_EVNTSEL0, val);
}
@@ -153,7 +153,7 @@ static void p6_pmu_enable_all(int added)
unsigned long val;
/* p6 only has one enable register */
- rdmsrq(MSR_P6_EVNTSEL0, val);
+ val = rdmsrq(MSR_P6_EVNTSEL0);
val |= ARCH_PERFMON_EVENTSEL_ENABLE;
wrmsrq(MSR_P6_EVNTSEL0, val);
}
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index b5726b50e77d..c8f23e68a4bb 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -196,7 +196,7 @@ static int __init pt_pmu_hw_init(void)
int ret;
long i;
- rdmsrq(MSR_PLATFORM_INFO, reg);
+ reg = rdmsrq(MSR_PLATFORM_INFO);
pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8;
/*
@@ -232,7 +232,7 @@ static int __init pt_pmu_hw_init(void)
* "IA32_VMX_MISC[bit 14]" being 1 means PT can trace
* post-VMXON.
*/
- rdmsrq(MSR_IA32_VMX_MISC, reg);
+ reg = rdmsrq(MSR_IA32_VMX_MISC);
if (reg & BIT(14))
pt_pmu.vmx = true;
}
@@ -928,7 +928,7 @@ static void pt_handle_status(struct pt *pt)
int advance = 0;
u64 status;
- rdmsrq(MSR_IA32_RTIT_STATUS, status);
+ status = rdmsrq(MSR_IA32_RTIT_STATUS);
if (status & RTIT_STATUS_ERROR) {
pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n");
@@ -987,12 +987,12 @@ static void pt_read_offset(struct pt_buffer *buf)
struct topa_page *tp;
if (!buf->single) {
- rdmsrq(MSR_IA32_RTIT_OUTPUT_BASE, pt->output_base);
+ pt->output_base = rdmsrq(MSR_IA32_RTIT_OUTPUT_BASE);
tp = phys_to_virt(pt->output_base);
buf->cur = &tp->topa;
}
- rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK, pt->output_mask);
+ pt->output_mask = rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK);
/* offset within current output region */
buf->output_off = pt->output_mask >> 32;
/* index of current output region within this table */
@@ -1612,7 +1612,7 @@ static void pt_event_start(struct perf_event *event, int mode)
* PMI might have just cleared these, so resume_allowed
* must be checked again also.
*/
- rdmsrq(MSR_IA32_RTIT_STATUS, status);
+ status = rdmsrq(MSR_IA32_RTIT_STATUS);
if (!(status & (RTIT_STATUS_TRIGGEREN |
RTIT_STATUS_ERROR |
RTIT_STATUS_STOPPED)) &&
diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index 7857959c6e82..0067bd35aa7f 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -171,7 +171,7 @@ u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *eve
{
u64 count;
- rdmsrq(event->hw.event_base, count);
+ count = rdmsrq(event->hw.event_base);
return count;
}
diff --git a/arch/x86/events/intel/uncore_nhmex.c b/arch/x86/events/intel/uncore_nhmex.c
index 8962e7cb21e3..c06ffcdce6e0 100644
--- a/arch/x86/events/intel/uncore_nhmex.c
+++ b/arch/x86/events/intel/uncore_nhmex.c
@@ -215,7 +215,7 @@ static void nhmex_uncore_msr_disable_box(struct intel_uncore_box *box)
u64 config;
if (msr) {
- rdmsrq(msr, config);
+ config = rdmsrq(msr);
config &= ~((1ULL << uncore_num_counters(box)) - 1);
/* WBox has a fixed counter */
if (uncore_msr_fixed_ctl(box))
@@ -230,7 +230,7 @@ static void nhmex_uncore_msr_enable_box(struct intel_uncore_box *box)
u64 config;
if (msr) {
- rdmsrq(msr, config);
+ config = rdmsrq(msr);
config |= (1ULL << uncore_num_counters(box)) - 1;
/* WBox has a fixed counter */
if (uncore_msr_fixed_ctl(box))
diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
index edddd4f9ab5f..b095b0fdeb3a 100644
--- a/arch/x86/events/intel/uncore_snb.c
+++ b/arch/x86/events/intel/uncore_snb.c
@@ -529,7 +529,7 @@ static int icl_get_cbox_num(void)
{
u64 num_boxes;
- rdmsrq(ICL_UNC_CBO_CONFIG, num_boxes);
+ num_boxes = rdmsrq(ICL_UNC_CBO_CONFIG);
return num_boxes & ICL_UNC_NUM_CBO_MASK;
}
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 334dc384b5b9..5c2c4199eb74 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -642,7 +642,7 @@ static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
msr = uncore_msr_box_ctl(box);
if (msr) {
- rdmsrq(msr, config);
+ config = rdmsrq(msr);
config |= SNBEP_PMON_BOX_CTL_FRZ;
wrmsrq(msr, config);
}
@@ -655,7 +655,7 @@ static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
msr = uncore_msr_box_ctl(box);
if (msr) {
- rdmsrq(msr, config);
+ config = rdmsrq(msr);
config &= ~SNBEP_PMON_BOX_CTL_FRZ;
wrmsrq(msr, config);
}
@@ -6357,7 +6357,7 @@ void spr_uncore_cpu_init(void)
* of UNCORE_SPR_CHA) is incorrect on some SPR variants because of a
* firmware bug. Using the value from SPR_MSR_UNC_CBO_CONFIG to replace it.
*/
- rdmsrq(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
+ num_cbo = rdmsrq(SPR_MSR_UNC_CBO_CONFIG);
/*
* The MSR doesn't work on the EMR XCC, but the firmware bug doesn't impact
* the EMR XCC. Don't let the value from the MSR replace the existing value.
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 76d6418c5055..0e59781549ca 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -158,7 +158,7 @@ static inline u64 msr_read_counter(struct perf_event *event)
u64 now;
if (event->hw.event_base)
- rdmsrq(event->hw.event_base, now);
+ now = rdmsrq(event->hw.event_base);
else
now = rdtsc_ordered();
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index eae24bb35dc1..a4b1cfccedd1 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1481,11 +1481,11 @@ static __always_inline void __amd_pmu_lbr_disable(void)
{
u64 dbg_ctl, dbg_extn_cfg;
- rdmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
+ dbg_extn_cfg = rdmsrq(MSR_AMD_DBG_EXTN_CFG);
wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN);
if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {
- rdmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
+ dbg_ctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
}
}
@@ -1639,7 +1639,7 @@ static __always_inline void __intel_pmu_lbr_disable(void)
{
u64 debugctl;
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
+ debugctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
}
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index 8ed03c32f560..180cc18282ca 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -193,7 +193,7 @@ static inline unsigned int get_rapl_pmu_idx(int cpu, int scope)
static inline u64 rapl_read_counter(struct perf_event *event)
{
u64 raw;
- rdmsrq(event->hw.event_base, raw);
+ raw = rdmsrq(event->hw.event_base);
return raw;
}
@@ -222,7 +222,7 @@ static u64 rapl_event_update(struct perf_event *event)
prev_raw_count = local64_read(&hwc->prev_count);
do {
- rdmsrq(event->hw.event_base, new_raw_count);
+ new_raw_count = rdmsrq(event->hw.event_base);
} while (!local64_try_cmpxchg(&hwc->prev_count,
&prev_raw_count, new_raw_count));
diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index e506f677db57..1980e5995e27 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -268,7 +268,7 @@ static inline u64 zhaoxin_pmu_get_status(void)
{
u64 status;
- rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status);
+ status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
return status;
}
@@ -295,7 +295,7 @@ static void zhaoxin_pmu_disable_fixed(struct hw_perf_event *hwc)
mask = 0xfULL << (idx * 4);
- rdmsrq(hwc->config_base, ctrl_val);
+ ctrl_val = rdmsrq(hwc->config_base);
ctrl_val &= ~mask;
wrmsrq(hwc->config_base, ctrl_val);
}
@@ -331,7 +331,7 @@ static void zhaoxin_pmu_enable_fixed(struct hw_perf_event *hwc)
bits <<= (idx * 4);
mask = 0xfULL << (idx * 4);
- rdmsrq(hwc->config_base, ctrl_val);
+ ctrl_val = rdmsrq(hwc->config_base);
ctrl_val &= ~mask;
ctrl_val |= bits;
wrmsrq(hwc->config_base, ctrl_val);
diff --git a/arch/x86/hyperv/hv_apic.c b/arch/x86/hyperv/hv_apic.c
index 95f1782d1e17..4e30f9a11bc4 100644
--- a/arch/x86/hyperv/hv_apic.c
+++ b/arch/x86/hyperv/hv_apic.c
@@ -38,7 +38,7 @@ static u64 hv_apic_icr_read(void)
{
u64 reg_val;
- rdmsrq(HV_X64_MSR_ICR, reg_val);
+ reg_val = rdmsrq(HV_X64_MSR_ICR);
return reg_val;
}
@@ -64,10 +64,10 @@ static u32 hv_apic_read(u32 reg)
switch (reg) {
case APIC_EOI:
- rdmsrq(HV_X64_MSR_EOI, reg_val.q);
+ reg_val.q = rdmsrq(HV_X64_MSR_EOI);
return reg_val.l;
case APIC_TASKPRI:
- rdmsrq(HV_X64_MSR_TPR, reg_val.q);
+ reg_val.q = rdmsrq(HV_X64_MSR_TPR);
return reg_val.l;
default:
diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c
index 55a8b6de2865..bc8f91114868 100644
--- a/arch/x86/hyperv/hv_init.c
+++ b/arch/x86/hyperv/hv_init.c
@@ -101,7 +101,7 @@ static int hyperv_init_ghcb(void)
* returned by MSR_AMD64_SEV_ES_GHCB is above shared
* memory boundary and map it here.
*/
- rdmsrq(MSR_AMD64_SEV_ES_GHCB, ghcb_gpa);
+ ghcb_gpa = rdmsrq(MSR_AMD64_SEV_ES_GHCB);
/* Mask out vTOM bit and map as decrypted */
ghcb_gpa &= ~ms_hyperv.shared_gpa_boundary;
@@ -134,7 +134,7 @@ static int hv_cpu_init(unsigned int cpu)
* For root partition we get the hypervisor provided VP assist
* page, instead of allocating a new page.
*/
- rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64);
+ msr.as_uint64 = rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE);
*hvp = memremap(msr.pfn << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT,
PAGE_SIZE, MEMREMAP_WB);
} else {
@@ -183,7 +183,7 @@ static void hv_reenlightenment_notify(struct work_struct *dummy)
{
struct hv_tsc_emulation_status emu_status;
- rdmsrq(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status);
+ *(u64 *)&emu_status = rdmsrq(HV_X64_MSR_TSC_EMULATION_STATUS);
/* Don't issue the callback if TSC accesses are not emulated */
if (hv_reenlightenment_cb && emu_status.inprogress)
@@ -196,11 +196,11 @@ void hyperv_stop_tsc_emulation(void)
u64 freq;
struct hv_tsc_emulation_status emu_status;
- rdmsrq(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status);
+ *(u64 *)&emu_status = rdmsrq(HV_X64_MSR_TSC_EMULATION_STATUS);
emu_status.inprogress = 0;
wrmsrq(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status);
- rdmsrq(HV_X64_MSR_TSC_FREQUENCY, freq);
+ freq = rdmsrq(HV_X64_MSR_TSC_FREQUENCY);
tsc_khz = div64_u64(freq, 1000);
}
EXPORT_SYMBOL_GPL(hyperv_stop_tsc_emulation);
@@ -260,7 +260,7 @@ void clear_hv_tscchange_cb(void)
if (!hv_reenlightenment_available())
return;
- rdmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl);
+ *(u64 *)&re_ctrl = rdmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL);
re_ctrl.enabled = 0;
wrmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl);
@@ -297,7 +297,7 @@ static int hv_cpu_die(unsigned int cpu)
*/
memunmap(hv_vp_assist_page[cpu]);
hv_vp_assist_page[cpu] = NULL;
- rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64);
+ msr.as_uint64 = rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE);
msr.enable = 0;
}
wrmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64);
@@ -306,7 +306,7 @@ static int hv_cpu_die(unsigned int cpu)
if (hv_reenlightenment_cb == NULL)
return 0;
- rdmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl));
+ *((u64 *)&re_ctrl) = rdmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL);
if (re_ctrl.target_vp == hv_vp_index[cpu]) {
/*
* Reassign reenlightenment notifications to some other online
@@ -377,7 +377,7 @@ static int hv_suspend(void *data)
hv_set_hypercall_pg(NULL);
/* Disable the hypercall page in the hypervisor */
- rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
+ hypercall_msr.as_uint64 = rdmsrq(HV_X64_MSR_HYPERCALL);
hypercall_msr.enable = 0;
wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
@@ -394,7 +394,7 @@ static void hv_resume(void *data)
WARN_ON(ret);
/* Re-enable the hypercall page */
- rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
+ hypercall_msr.as_uint64 = rdmsrq(HV_X64_MSR_HYPERCALL);
hypercall_msr.enable = 1;
hypercall_msr.guest_physical_address =
vmalloc_to_pfn(hv_hypercall_pg_saved);
@@ -529,7 +529,7 @@ void __init hyperv_init(void)
if (hv_hypercall_pg == NULL)
goto clean_guest_os_id;
- rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
+ hypercall_msr.as_uint64 = rdmsrq(HV_X64_MSR_HYPERCALL);
hypercall_msr.enable = 1;
if (hv_root_partition()) {
@@ -671,7 +671,7 @@ void hyperv_report_panic(struct pt_regs *regs, long err, bool in_die)
return;
panic_reported = true;
- rdmsrq(HV_X64_MSR_GUEST_OS_ID, guest_id);
+ guest_id = rdmsrq(HV_X64_MSR_GUEST_OS_ID);
wrmsrq(HV_X64_MSR_CRASH_P0, err);
wrmsrq(HV_X64_MSR_CRASH_P1, guest_id);
@@ -705,7 +705,7 @@ bool hv_is_hyperv_initialized(void)
* that the hypercall page is setup
*/
hypercall_msr.as_uint64 = 0;
- rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
+ hypercall_msr.as_uint64 = rdmsrq(HV_X64_MSR_HYPERCALL);
return hypercall_msr.enable;
}
diff --git a/arch/x86/hyperv/hv_spinlock.c b/arch/x86/hyperv/hv_spinlock.c
index 210b494e4de0..29dad837f459 100644
--- a/arch/x86/hyperv/hv_spinlock.c
+++ b/arch/x86/hyperv/hv_spinlock.c
@@ -50,7 +50,7 @@ static void hv_qlock_wait(u8 *byte, u8 val)
if (READ_ONCE(*byte) == val) {
unsigned long msr_val;
- rdmsrq(HV_X64_MSR_GUEST_IDLE, msr_val);
+ msr_val = rdmsrq(HV_X64_MSR_GUEST_IDLE);
(void)msr_val;
}
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 9cd493d467d4..e028140fac49 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -220,7 +220,7 @@ static inline u32 native_apic_msr_read(u32 reg)
if (reg == APIC_DFR)
return -1;
- rdmsrq(APIC_BASE_MSR + (reg >> 4), msr);
+ msr = rdmsrq(APIC_BASE_MSR + (reg >> 4));
return (u32)msr;
}
@@ -233,7 +233,7 @@ static inline u64 native_x2apic_icr_read(void)
{
unsigned long val;
- rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), val);
+ val = rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4));
return val;
}
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index a2c1f2d24b64..426d48beef81 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -180,7 +180,7 @@ static inline unsigned long get_debugctlmsr(void)
if (boot_cpu_data.x86 < 6)
return 0;
#endif
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
+ debugctlmsr = rdmsrq(MSR_IA32_DEBUGCTLMSR);
return debugctlmsr;
}
diff --git a/arch/x86/include/asm/fsgsbase.h b/arch/x86/include/asm/fsgsbase.h
index 70ff4ef457b1..9de49d732e9e 100644
--- a/arch/x86/include/asm/fsgsbase.h
+++ b/arch/x86/include/asm/fsgsbase.h
@@ -60,7 +60,7 @@ static inline unsigned long x86_fsbase_read_cpu(void)
if (boot_cpu_has(X86_FEATURE_FSGSBASE))
fsbase = rdfsbase();
else
- rdmsrq(MSR_FS_BASE, fsbase);
+ fsbase = rdmsrq(MSR_FS_BASE);
return fsbase;
}
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 5f6c1ce9673b..e9b4ad535643 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -2417,7 +2417,7 @@ static inline unsigned long read_msr(unsigned long msr)
{
u64 value;
- rdmsrq(msr, value);
+ value = rdmsrq(msr);
return value;
}
#endif
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 6d7bab33af71..95761803c2e6 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -173,14 +173,13 @@ static inline u64 native_read_pmc(int counter)
#include <asm/paravirt.h>
#else
#include <linux/errno.h>
-/*
- * Access to machine-specific registers (available on 586 and better only)
- * Note: the rd* operations modify the parameters directly (without using
- * pointer indirection), this allows gcc to optimize better
- */
-#define rdmsrq(msr, val) \
- ((val) = native_read_msr((msr)))
+/* Access to machine-specific registers (available on 586 and better only) */
+
+static __always_inline u64 rdmsrq(u32 msr)
+{
+ return native_read_msr(msr);
+}
static inline void wrmsrq(u32 msr, u64 val)
{
@@ -237,7 +236,7 @@ int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
#else /* CONFIG_SMP */
static inline int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
{
- rdmsrq(msr_no, *q);
+ *q = rdmsrq(msr_no);
return 0;
}
static inline int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 93754aa60d5e..19442bc3af37 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -150,10 +150,10 @@ static inline int paravirt_write_msr_safe(u32 msr, u64 val)
return PVOP_CALL2(int, pv_ops, cpu.write_msr_safe, msr, val);
}
-#define rdmsrq(msr, val) \
-do { \
- val = paravirt_read_msr(msr); \
-} while (0)
+static __always_inline u64 rdmsrq(u32 msr)
+{
+ return paravirt_read_msr(msr);
+}
static inline void wrmsrq(u32 msr, u64 val)
{
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 90025451ace2..7a6c77e6a44e 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1193,7 +1193,7 @@ void disable_local_APIC(void)
if (enabled_via_apicbase) {
struct msr val;
- rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.q = rdmsrq(MSR_IA32_APICBASE);
val.l &= ~MSR_IA32_APICBASE_ENABLE;
wrmsrq(MSR_IA32_APICBASE, val.q);
}
@@ -1710,7 +1710,7 @@ static bool x2apic_hw_locked(void)
x86_arch_cap_msr = x86_read_arch_cap_msr();
if (x86_arch_cap_msr & ARCH_CAP_XAPIC_DISABLE) {
- rdmsrq(MSR_IA32_XAPIC_DISABLE_STATUS, msr);
+ msr = rdmsrq(MSR_IA32_XAPIC_DISABLE_STATUS);
return (msr & LEGACY_XAPIC_DISABLED);
}
return false;
@@ -1723,7 +1723,7 @@ static void __x2apic_disable(void)
if (!boot_cpu_has(X86_FEATURE_APIC))
return;
- rdmsrq(MSR_IA32_APICBASE, msr);
+ msr = rdmsrq(MSR_IA32_APICBASE);
if (!(msr & X2APIC_ENABLE))
return;
/* Disable xapic and x2apic first and then reenable xapic mode */
@@ -1736,7 +1736,7 @@ static void __x2apic_enable(void)
{
u64 msr;
- rdmsrq(MSR_IA32_APICBASE, msr);
+ msr = rdmsrq(MSR_IA32_APICBASE);
if (msr & X2APIC_ENABLE)
return;
wrmsrq(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
@@ -1976,7 +1976,7 @@ static bool __init apic_verify(unsigned long addr)
/* The BIOS may have set up the APIC at some other address */
if (boot_cpu_data.x86 >= 6) {
- rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.q = rdmsrq(MSR_IA32_APICBASE);
if (val.l & MSR_IA32_APICBASE_ENABLE)
addr = val.l & MSR_IA32_APICBASE_BASE;
}
@@ -1999,7 +1999,7 @@ bool __init apic_force_enable(unsigned long addr)
* and AMD K7 (Model > 1) or later.
*/
if (boot_cpu_data.x86 >= 6) {
- rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.q = rdmsrq(MSR_IA32_APICBASE);
if (!(val.l & MSR_IA32_APICBASE_ENABLE)) {
pr_info("Local APIC disabled by BIOS -- reenabling.\n");
val.l &= ~MSR_IA32_APICBASE_BASE;
@@ -2476,7 +2476,7 @@ static void lapic_resume(void *data)
* SMP! We'll need to do this as part of the CPU restore!
*/
if (boot_cpu_data.x86 >= 6) {
- rdmsrq(MSR_IA32_APICBASE, val.q);
+ val.q = rdmsrq(MSR_IA32_APICBASE);
val.l &= ~MSR_IA32_APICBASE_BASE;
val.l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
wrmsrq(MSR_IA32_APICBASE, val.q);
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 5c5be2d58242..e61bab997e61 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -32,7 +32,7 @@ static u32 numachip1_get_apic_id(u32 x)
unsigned int id = (x >> 24) & 0xff;
if (static_cpu_has(X86_FEATURE_NODEID_MSR)) {
- rdmsrq(MSR_FAM10H_NODE_ID, value);
+ value = rdmsrq(MSR_FAM10H_NODE_ID);
id |= (value << 2) & 0xff00;
}
@@ -43,7 +43,7 @@ static u32 numachip2_get_apic_id(u32 x)
{
u64 mcfg;
- rdmsrq(MSR_FAM10H_MMIO_CONF_BASE, mcfg);
+ mcfg = rdmsrq(MSR_FAM10H_MMIO_CONF_BASE);
return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24);
}
@@ -151,7 +151,7 @@ static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
/* Account for nodes per socket in multi-core-module processors */
if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
- rdmsrq(MSR_FAM10H_NODE_ID, val);
+ val = rdmsrq(MSR_FAM10H_NODE_ID);
nodes = ((val >> 3) & 7) + 1;
}
diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c
index 99444409c026..3efceee443b7 100644
--- a/arch/x86/kernel/cet.c
+++ b/arch/x86/kernel/cet.c
@@ -56,7 +56,7 @@ static void do_user_cp_fault(struct pt_regs *regs, unsigned long error_code)
* will be whatever is live in userspace. So read the SSP before enabling
* interrupts so locking the fpregs to do it later is not required.
*/
- rdmsrq(MSR_IA32_PL3_SSP, ssp);
+ ssp = rdmsrq(MSR_IA32_PL3_SSP);
cond_local_irq_enable(regs);
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 169e373418bb..47052e8c328b 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -160,7 +160,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
if (mbytes > 508)
mbytes = 508;
- rdmsrq(MSR_K6_WHCR, val.q);
+ val.q = rdmsrq(MSR_K6_WHCR);
if ((val.l & 0x0000FFFF) == 0) {
unsigned long flags;
val.l = (1 << 0) | ((mbytes / 4) << 1);
@@ -181,7 +181,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
if (mbytes > 4092)
mbytes = 4092;
- rdmsrq(MSR_K6_WHCR, val.q);
+ val.q = rdmsrq(MSR_K6_WHCR);
if ((val.l & 0xFFFF0000) == 0) {
unsigned long flags;
val.l = ((mbytes >> 2) << 22) | (1 << 16);
@@ -228,7 +228,7 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
* As per AMD technical note 27212 0.2
*/
if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
- rdmsrq(MSR_K7_CLK_CTL, val.q);
+ val.q = rdmsrq(MSR_K7_CLK_CTL);
if ((val.l & 0xfff00000) != 0x20000000) {
pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
val.l, ((val.l & 0x000fffff) | 0x20000000));
@@ -429,7 +429,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
(c->x86 == 0x10 && c->x86_model >= 0x2)) {
u64 val;
- rdmsrq(MSR_K7_HWCR, val);
+ val = rdmsrq(MSR_K7_HWCR);
if (!(val & BIT(24)))
pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
}
@@ -581,7 +581,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
*/
if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
/* Check if memory encryption is enabled */
- rdmsrq(MSR_AMD64_SYSCFG, msr);
+ msr = rdmsrq(MSR_AMD64_SYSCFG);
if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
goto clear_all;
@@ -598,7 +598,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
if (!sme_me_mask)
setup_clear_cpu_cap(X86_FEATURE_SME);
- rdmsrq(MSR_K7_HWCR, msr);
+ msr = rdmsrq(MSR_K7_HWCR);
if (!(msr & MSR_K7_HWCR_SMMLOCK))
goto clear_sev;
@@ -1109,7 +1109,7 @@ static void init_amd(struct cpuinfo_x86 *c)
init_amd_cacheinfo(c);
if (cpu_has(c, X86_FEATURE_SVM)) {
- rdmsrq(MSR_VM_CR, vm_cr);
+ vm_cr = rdmsrq(MSR_VM_CR);
if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) {
pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n");
clear_cpu_cap(c, X86_FEATURE_SVM);
diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmperf.c
index 7ffc78d5ebf2..492dc9a11d6b 100644
--- a/arch/x86/kernel/cpu/aperfmperf.c
+++ b/arch/x86/kernel/cpu/aperfmperf.c
@@ -41,8 +41,8 @@ static void init_counter_refs(void *data)
{
u64 aperf, mperf;
- rdmsrq(MSR_IA32_APERF, aperf);
- rdmsrq(MSR_IA32_MPERF, mperf);
+ aperf = rdmsrq(MSR_IA32_APERF);
+ mperf = rdmsrq(MSR_IA32_MPERF);
this_cpu_write(cpu_samples.aperf, aperf);
this_cpu_write(cpu_samples.mperf, mperf);
@@ -479,8 +479,8 @@ void arch_scale_freq_tick(void)
if (!cpu_feature_enabled(X86_FEATURE_APERFMPERF))
return;
- rdmsrq(MSR_IA32_APERF, aperf);
- rdmsrq(MSR_IA32_MPERF, mperf);
+ aperf = rdmsrq(MSR_IA32_APERF);
+ mperf = rdmsrq(MSR_IA32_MPERF);
acnt = aperf - s->aperf;
mcnt = mperf - s->mperf;
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 83f51cab0b1e..bad99e491e13 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -760,7 +760,7 @@ void update_srbds_msr(void)
if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
return;
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
+ mcu_ctrl = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
switch (srbds_mitigation) {
case SRBDS_MITIGATION_OFF:
@@ -896,7 +896,7 @@ void update_gds_msr(void)
switch (gds_mitigation) {
case GDS_MITIGATION_OFF:
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
+ mcu_ctrl = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
mcu_ctrl |= GDS_MITG_DIS;
break;
case GDS_MITIGATION_FULL_LOCKED:
@@ -906,7 +906,7 @@ void update_gds_msr(void)
* CPUs.
*/
case GDS_MITIGATION_FULL:
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
+ mcu_ctrl = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
mcu_ctrl &= ~GDS_MITG_DIS;
break;
case GDS_MITIGATION_FORCE:
@@ -923,7 +923,7 @@ void update_gds_msr(void)
* GDS_MITG_DIS will be ignored if this processor is locked but the boot
* processor was not.
*/
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl_after);
+ mcu_ctrl_after = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
WARN_ON_ONCE(mcu_ctrl != mcu_ctrl_after);
}
@@ -958,7 +958,7 @@ static void __init gds_select_mitigation(void)
if (gds_mitigation == GDS_MITIGATION_FORCE)
gds_mitigation = GDS_MITIGATION_FULL;
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
+ mcu_ctrl = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
if (mcu_ctrl & GDS_MITG_LOCKED) {
if (gds_mitigation == GDS_MITIGATION_OFF)
pr_warn("Mitigation locked. Disable failed.\n");
@@ -3232,7 +3232,7 @@ void __init cpu_select_mitigations(void)
* init code as it is not enumerated and depends on the family.
*/
if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
- rdmsrq(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
+ x86_spec_ctrl_base = rdmsrq(MSR_IA32_SPEC_CTRL);
/*
* Previously running kernel (kexec), may have some controls
diff --git a/arch/x86/kernel/cpu/bus_lock.c b/arch/x86/kernel/cpu/bus_lock.c
index bba28607a59a..c9074c368146 100644
--- a/arch/x86/kernel/cpu/bus_lock.c
+++ b/arch/x86/kernel/cpu/bus_lock.c
@@ -105,7 +105,7 @@ static bool split_lock_verify_msr(bool on)
ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
if (wrmsrq_safe(MSR_TEST_CTRL, ctrl))
return false;
- rdmsrq(MSR_TEST_CTRL, tmp);
+ tmp = rdmsrq(MSR_TEST_CTRL);
return ctrl == tmp;
}
@@ -145,7 +145,7 @@ static void __init __split_lock_setup(void)
return;
}
- rdmsrq(MSR_TEST_CTRL, msr_test_ctrl_cache);
+ msr_test_ctrl_cache = rdmsrq(MSR_TEST_CTRL);
if (!split_lock_verify_msr(true)) {
pr_info("MSR access failed: Disabled\n");
@@ -305,7 +305,7 @@ void bus_lock_init(void)
if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
return;
- rdmsrq(MSR_IA32_DEBUGCTLMSR, val);
+ val = rdmsrq(MSR_IA32_DEBUGCTLMSR);
if ((boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
(sld_state == sld_warn || sld_state == sld_fatal)) ||
@@ -383,7 +383,7 @@ static void __init split_lock_setup(struct cpuinfo_x86 *c)
* MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT is. All CPUs that set
* it have split lock detection.
*/
- rdmsrq(MSR_IA32_CORE_CAPS, ia32_core_caps);
+ ia32_core_caps = rdmsrq(MSR_IA32_CORE_CAPS);
if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)
goto supported;
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 513fa1f640f9..6cd89b5ac9de 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -30,7 +30,7 @@ static void init_c3(struct cpuinfo_x86 *c)
/* enable ACE unit, if present and disabled */
if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
- rdmsrq(MSR_VIA_FCR, msr);
+ msr = rdmsrq(MSR_VIA_FCR);
/* enable ACE unit */
wrmsrq(MSR_VIA_FCR, msr | ACE_FCR);
pr_info("CPU: Enabled ACE h/w crypto\n");
@@ -38,7 +38,7 @@ static void init_c3(struct cpuinfo_x86 *c)
/* enable RNG unit, if present and disabled */
if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
- rdmsrq(MSR_VIA_RNG, msr);
+ msr = rdmsrq(MSR_VIA_RNG);
/* enable RNG unit */
wrmsrq(MSR_VIA_RNG, msr | RNG_ENABLE);
pr_info("CPU: Enabled h/w RNG\n");
@@ -52,7 +52,7 @@ static void init_c3(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_32
/* Cyrix III family needs CX8 & PGE explicitly enabled. */
if (c->x86_model >= 6 && c->x86_model <= 13) {
- rdmsrq(MSR_VIA_FCR, msr);
+ msr = rdmsrq(MSR_VIA_FCR);
wrmsrq(MSR_VIA_FCR, msr | (1 << 1 | 1 << 7));
set_cpu_cap(c, X86_FEATURE_CX8);
}
@@ -169,7 +169,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
name = "??";
}
- rdmsrq(MSR_IDT_FCR1, val.q);
+ val.q = rdmsrq(MSR_IDT_FCR1);
newlo = (val.l | fcr_set) & (~fcr_clr);
if (newlo != val.l) {
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index cbef2c6c8478..5a36d96595b4 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -346,7 +346,7 @@ static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
/* Disable processor serial number: */
- rdmsrq(MSR_IA32_BBL_CR_CTL, val.q);
+ val.q = rdmsrq(MSR_IA32_BBL_CR_CTL);
val.l |= 0x200000;
wrmsrq(MSR_IA32_BBL_CR_CTL, val.q);
@@ -610,7 +610,7 @@ __noendbr u64 ibt_save(bool disable)
u64 msr = 0;
if (cpu_feature_enabled(X86_FEATURE_IBT)) {
- rdmsrq(MSR_IA32_S_CET, msr);
+ msr = rdmsrq(MSR_IA32_S_CET);
if (disable)
wrmsrq(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);
}
@@ -623,7 +623,7 @@ __noendbr void ibt_restore(u64 save)
u64 msr;
if (cpu_feature_enabled(X86_FEATURE_IBT)) {
- rdmsrq(MSR_IA32_S_CET, msr);
+ msr = rdmsrq(MSR_IA32_S_CET);
msr &= ~CET_ENDBR_EN;
msr |= (save & CET_ENDBR_EN);
wrmsrq(MSR_IA32_S_CET, msr);
@@ -1361,7 +1361,7 @@ u64 x86_read_arch_cap_msr(void)
u64 x86_arch_cap_msr = 0;
if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
- rdmsrq(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr);
+ x86_arch_cap_msr = rdmsrq(MSR_IA32_ARCH_CAPABILITIES);
return x86_arch_cap_msr;
}
@@ -1913,10 +1913,10 @@ static bool detect_null_seg_behavior(void)
*/
unsigned long old_base, tmp;
- rdmsrq(MSR_FS_BASE, old_base);
+ old_base = rdmsrq(MSR_FS_BASE);
wrmsrq(MSR_FS_BASE, 1);
loadsegment(fs, 0);
- rdmsrq(MSR_FS_BASE, tmp);
+ tmp = rdmsrq(MSR_FS_BASE);
wrmsrq(MSR_FS_BASE, old_base);
return tmp == 0;
}
diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c
index 1ce30a5c26ce..3adcab54c16f 100644
--- a/arch/x86/kernel/cpu/feat_ctl.c
+++ b/arch/x86/kernel/cpu/feat_ctl.c
@@ -40,7 +40,7 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c)
* as they exist on any CPU that supports VMX, i.e. we want the WARN if
* the RDMSR faults.
*/
- rdmsrq(MSR_IA32_VMX_PROCBASED_CTLS, val.q);
+ val.q = rdmsrq(MSR_IA32_VMX_PROCBASED_CTLS);
c->vmx_capability[PRIMARY_CTLS] = val.h;
rdmsrq_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &val.q);
@@ -51,7 +51,7 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c)
c->vmx_capability[TERTIARY_CTLS_LOW] = val.l;
c->vmx_capability[TERTIARY_CTLS_HIGH] = val.h;
- rdmsrq(MSR_IA32_VMX_PINBASED_CTLS, val.q);
+ val.q = rdmsrq(MSR_IA32_VMX_PINBASED_CTLS);
supported = val.h;
rdmsrq_safe(MSR_IA32_VMX_VMFUNC, &val.q);
funcs = val.h;
diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index ec51c2b9a257..44b462799cf6 100644
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -99,7 +99,7 @@ static void bsp_init_hygon(struct cpuinfo_x86 *c)
if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
u64 val;
- rdmsrq(MSR_K7_HWCR, val);
+ val = rdmsrq(MSR_K7_HWCR);
if (!(val & BIT(24)))
pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
}
@@ -194,7 +194,7 @@ static void init_hygon(struct cpuinfo_x86 *c)
init_hygon_cacheinfo(c);
if (cpu_has(c, X86_FEATURE_SVM)) {
- rdmsrq(MSR_VM_CR, vm_cr);
+ vm_cr = rdmsrq(MSR_VM_CR);
if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) {
pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n");
clear_cpu_cap(c, X86_FEATURE_SVM);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 076bdd0d3f85..20d48ffa27b8 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -159,7 +159,7 @@ static void detect_tme_early(struct cpuinfo_x86 *c)
u64 tme_activate;
int keyid_bits;
- rdmsrq(MSR_IA32_TME_ACTIVATE, tme_activate);
+ tme_activate = rdmsrq(MSR_IA32_TME_ACTIVATE);
if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
pr_info_once("x86/tme: not enabled by BIOS\n");
@@ -300,7 +300,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
* string flag and enhanced fast string capabilities accordingly.
*/
if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) {
- rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable);
+ misc_enable = rdmsrq(MSR_IA32_MISC_ENABLE);
if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
/* X86_FEATURE_ERMS is set based on CPUID */
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
@@ -544,7 +544,7 @@ static void init_intel(struct cpuinfo_x86 *c)
if (boot_cpu_has(X86_FEATURE_DS)) {
u64 l;
- rdmsrq(MSR_IA32_MISC_ENABLE, l);
+ l = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(l & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
set_cpu_cap(c, X86_FEATURE_BTS);
if (!(l & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c
index 2c56f8730f59..a02d562253d9 100644
--- a/arch/x86/kernel/cpu/intel_epb.c
+++ b/arch/x86/kernel/cpu/intel_epb.c
@@ -79,7 +79,7 @@ static int intel_epb_save(void *data)
{
u64 epb;
- rdmsrq(MSR_IA32_ENERGY_PERF_BIAS, epb);
+ epb = rdmsrq(MSR_IA32_ENERGY_PERF_BIAS);
/*
* Ensure that saved_epb will always be nonzero after this write even if
* the EPB value read from the MSR is 0.
@@ -94,7 +94,7 @@ static void intel_epb_restore(void *data)
u64 val = this_cpu_read(saved_epb);
u64 epb;
- rdmsrq(MSR_IA32_ENERGY_PERF_BIAS, epb);
+ epb = rdmsrq(MSR_IA32_ENERGY_PERF_BIAS);
if (val) {
val &= EPB_MASK;
} else {
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index f916fb4c5d13..febdd4fe9b3b 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -438,7 +438,7 @@ static void threshold_restart_block(void *_tr)
if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)
return;
- rdmsrq(tr->b->address, val.q);
+ val.q = rdmsrq(tr->b->address);
/*
* Reset error count and overflow bit.
@@ -658,7 +658,7 @@ static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
return;
}
- rdmsrq(MSR_K7_HWCR, hwcr);
+ hwcr = rdmsrq(MSR_K7_HWCR);
/* McStatusWrEn has to be set */
need_toggle = !(hwcr & BIT(18));
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 017aaf57ba47..0d4f4c000405 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1845,7 +1845,7 @@ static void __mcheck_cpu_cap_init(void)
u64 cap;
u8 b;
- rdmsrq(MSR_IA32_MCG_CAP, cap);
+ cap = rdmsrq(MSR_IA32_MCG_CAP);
b = cap & MCG_BANKCNT_MASK;
@@ -1864,7 +1864,7 @@ static void __mcheck_cpu_init_generic(void)
{
u64 cap;
- rdmsrq(MSR_IA32_MCG_CAP, cap);
+ cap = rdmsrq(MSR_IA32_MCG_CAP);
if (cap & MCG_CTL_P)
wrmsrq(MSR_IA32_MCG_CTL, ~0ULL);
}
@@ -1896,7 +1896,7 @@ static void __mcheck_cpu_init_prepare_banks(void)
wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl);
wrmsrq(mca_msr_reg(i, MCA_STATUS), 0);
- rdmsrq(mca_msr_reg(i, MCA_CTL), msrval);
+ msrval = rdmsrq(mca_msr_reg(i, MCA_CTL));
b->init = !!msrval;
}
}
@@ -2214,7 +2214,7 @@ void mca_bsp_init(struct cpuinfo_x86 *c)
if (mce_flags.smca)
smca_bsp_init();
- rdmsrq(MSR_IA32_MCG_CAP, cap);
+ cap = rdmsrq(MSR_IA32_MCG_CAP);
/* Use accurate RIP reporting if available. */
if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index 6f8a49d8baeb..aa933864f32e 100644
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -743,7 +743,7 @@ static void check_hw_inj_possible(void)
u64 status = MCI_STATUS_VAL, ipid;
/* Check whether bank is populated */
- rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank), ipid);
+ ipid = rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank));
if (!ipid)
continue;
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 4655223ba560..2edb05d5e2d7 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -94,7 +94,7 @@ static bool cmci_supported(int *banks)
if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
return false;
- rdmsrq(MSR_IA32_MCG_CAP, cap);
+ cap = rdmsrq(MSR_IA32_MCG_CAP);
*banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK);
return !!(cap & MCG_CMCI_P);
}
@@ -106,7 +106,7 @@ static bool lmce_supported(void)
if (mca_cfg.lmce_disabled)
return false;
- rdmsrq(MSR_IA32_MCG_CAP, tmp);
+ tmp = rdmsrq(MSR_IA32_MCG_CAP);
/*
* LMCE depends on recovery support in the processor. Hence both
@@ -123,7 +123,7 @@ static bool lmce_supported(void)
* WARN if the MSR isn't locked as init_ia32_feat_ctl() unconditionally
* locks the MSR in the event that it wasn't already locked by BIOS.
*/
- rdmsrq(MSR_IA32_FEAT_CTL, tmp);
+ tmp = rdmsrq(MSR_IA32_FEAT_CTL);
if (WARN_ON_ONCE(!(tmp & FEAT_CTL_LOCKED)))
return false;
@@ -141,7 +141,7 @@ static void cmci_set_threshold(int bank, int thresh)
u64 val;
raw_spin_lock_irqsave(&cmci_discover_lock, flags);
- rdmsrq(MSR_IA32_MCx_CTL2(bank), val);
+ val = rdmsrq(MSR_IA32_MCx_CTL2(bank));
val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh);
raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
@@ -184,7 +184,7 @@ static bool cmci_skip_bank(int bank, u64 *val)
if (test_bit(bank, mce_banks_ce_disabled))
return true;
- rdmsrq(MSR_IA32_MCx_CTL2(bank), *val);
+ *val = rdmsrq(MSR_IA32_MCx_CTL2(bank));
/* Already owned by someone else? */
if (*val & MCI_CTL2_CMCI_EN) {
@@ -233,7 +233,7 @@ static void cmci_claim_bank(int bank, u64 val, int bios_zero_thresh, int *bios_w
val |= MCI_CTL2_CMCI_EN;
wrmsrq(MSR_IA32_MCx_CTL2(bank), val);
- rdmsrq(MSR_IA32_MCx_CTL2(bank), val);
+ val = rdmsrq(MSR_IA32_MCx_CTL2(bank));
/* If the enable bit did not stick, this bank should be polled. */
if (!(val & MCI_CTL2_CMCI_EN)) {
@@ -324,7 +324,7 @@ static void __cmci_disable_bank(int bank)
if (!test_bit(bank, this_cpu_ptr(mce_banks_owned)))
return;
- rdmsrq(MSR_IA32_MCx_CTL2(bank), val);
+ val = rdmsrq(MSR_IA32_MCx_CTL2(bank));
val &= ~MCI_CTL2_CMCI_EN;
wrmsrq(MSR_IA32_MCx_CTL2(bank), val);
__clear_bit(bank, this_cpu_ptr(mce_banks_owned));
@@ -430,7 +430,7 @@ void intel_init_lmce(void)
if (!lmce_supported())
return;
- rdmsrq(MSR_IA32_MCG_EXT_CTL, val);
+ val = rdmsrq(MSR_IA32_MCG_EXT_CTL);
if (!(val & MCG_EXT_CTL_LMCE_EN))
wrmsrq(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
@@ -443,7 +443,7 @@ void intel_clear_lmce(void)
if (!lmce_supported())
return;
- rdmsrq(MSR_IA32_MCG_EXT_CTL, val);
+ val = rdmsrq(MSR_IA32_MCG_EXT_CTL);
val &= ~MCG_EXT_CTL_LMCE_EN;
wrmsrq(MSR_IA32_MCG_EXT_CTL, val);
}
diff --git a/arch/x86/kernel/cpu/mce/p5.c b/arch/x86/kernel/cpu/mce/p5.c
index eb99f384d747..7b363b604bad 100644
--- a/arch/x86/kernel/cpu/mce/p5.c
+++ b/arch/x86/kernel/cpu/mce/p5.c
@@ -26,8 +26,8 @@ noinstr void pentium_machine_check(struct pt_regs *regs)
u64 addr, type;
instrumentation_begin();
- rdmsrq(MSR_IA32_P5_MC_ADDR, addr);
- rdmsrq(MSR_IA32_P5_MC_TYPE, type);
+ addr = rdmsrq(MSR_IA32_P5_MC_ADDR);
+ type = rdmsrq(MSR_IA32_P5_MC_TYPE);
pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
smp_processor_id(), (u32)addr, (u32)type);
@@ -55,8 +55,8 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
return;
/* Read registers before enabling: */
- rdmsrq(MSR_IA32_P5_MC_ADDR, q);
- rdmsrq(MSR_IA32_P5_MC_TYPE, q);
+ q = rdmsrq(MSR_IA32_P5_MC_ADDR);
+ q = rdmsrq(MSR_IA32_P5_MC_TYPE);
pr_info("Intel old style machine check architecture supported.\n");
/* Enable MCE: */
diff --git a/arch/x86/kernel/cpu/mce/winchip.c b/arch/x86/kernel/cpu/mce/winchip.c
index 7040243533d9..7b967f2abd8f 100644
--- a/arch/x86/kernel/cpu/mce/winchip.c
+++ b/arch/x86/kernel/cpu/mce/winchip.c
@@ -30,7 +30,7 @@ void winchip_mcheck_init(struct cpuinfo_x86 *c)
{
struct msr val;
- rdmsrq(MSR_IDT_FCR1, val.q);
+ val.q = rdmsrq(MSR_IDT_FCR1);
val.l |= (1<<2); /* Enable EIERRINT (int 18 MCE) */
val.l &= ~(1<<4); /* Enable MCE */
wrmsrq(MSR_IDT_FCR1, val.q);
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index f4a444e6114d..4d860fea5cc8 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -1027,7 +1027,7 @@ static __init bool staging_available(void)
if (!(val & ARCH_CAP_MCU_ENUM))
return false;
- rdmsrq(MSR_IA32_MCU_ENUMERATION, val);
+ val = rdmsrq(MSR_IA32_MCU_ENUMERATION);
return !!(val & MCU_STAGING);
}
diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
index 185d4f677ec0..65ad235ef5c6 100644
--- a/arch/x86/kernel/cpu/mshyperv.c
+++ b/arch/x86/kernel/cpu/mshyperv.c
@@ -74,7 +74,7 @@ u64 hv_get_non_nested_msr(unsigned int reg)
if (hv_is_synic_msr(reg) && ms_hyperv.paravisor_present)
hv_ivm_msr_read(reg, &value);
else
- rdmsrq(reg, value);
+ value = rdmsrq(reg);
return value;
}
EXPORT_SYMBOL_GPL(hv_get_non_nested_msr);
@@ -399,7 +399,7 @@ static unsigned long hv_get_tsc_khz(void)
{
unsigned long freq;
- rdmsrq(HV_X64_MSR_TSC_FREQUENCY, freq);
+ freq = rdmsrq(HV_X64_MSR_TSC_FREQUENCY);
return freq / 1000;
}
@@ -645,7 +645,7 @@ static void __init ms_hyperv_init_platform(void)
*/
u64 hv_lapic_frequency;
- rdmsrq(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency);
+ hv_lapic_frequency = rdmsrq(HV_X64_MSR_APIC_FREQUENCY);
hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ);
lapic_timer_period = hv_lapic_frequency;
pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n",
diff --git a/arch/x86/kernel/cpu/mtrr/amd.c b/arch/x86/kernel/cpu/mtrr/amd.c
index fad93cbf6869..6622eaf9445e 100644
--- a/arch/x86/kernel/cpu/mtrr/amd.c
+++ b/arch/x86/kernel/cpu/mtrr/amd.c
@@ -13,7 +13,7 @@ amd_get_mtrr(unsigned int reg, unsigned long *base,
unsigned long val;
struct msr msr;
- rdmsrq(MSR_K6_UWCCR, msr.q);
+ msr.q = rdmsrq(MSR_K6_UWCCR);
/* Upper dword is region 1, lower is region 0 */
if (reg == 1)
val = msr.h;
@@ -70,7 +70,7 @@ amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type
/*
* Low is MTRR0, High MTRR 1
*/
- rdmsrq(MSR_K6_UWCCR, msr.val);
+ msr.val = rdmsrq(MSR_K6_UWCCR);
/*
* Blank to disable
*/
diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c
index cd1a6dec4064..2b72c784db9e 100644
--- a/arch/x86/kernel/cpu/mtrr/cleanup.c
+++ b/arch/x86/kernel/cpu/mtrr/cleanup.c
@@ -670,7 +670,7 @@ int __init mtrr_cleanup(void)
if (!cpu_feature_enabled(X86_FEATURE_MTRR) || enable_mtrr_cleanup < 1)
return 0;
- rdmsrq(MSR_MTRRdefType, def);
+ def = rdmsrq(MSR_MTRRdefType);
def &= 0xff;
if (def != MTRR_TYPE_UNCACHABLE)
return 0;
@@ -870,7 +870,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
if (!cpu_feature_enabled(X86_FEATURE_MTRR) || disable_mtrr_trim)
return 0;
- rdmsrq(MSR_MTRRdefType, def);
+ def = rdmsrq(MSR_MTRRdefType);
def &= MTRR_DEF_TYPE_TYPE;
if (def != MTRR_TYPE_UNCACHABLE)
return 0;
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 67cf69f24b00..4d8034a7fdc8 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -112,7 +112,7 @@ static inline void k8_check_syscfg_dram_mod_en(void)
if (cc_platform_has(CC_ATTR_HOST_SEV_SNP))
return;
- rdmsrq(MSR_AMD64_SYSCFG, val.q);
+ val.q = rdmsrq(MSR_AMD64_SYSCFG);
if (val.l & K8_MTRRFIXRANGE_DRAM_MODIFY) {
pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
" not cleared by BIOS, clearing this bit\n",
@@ -559,10 +559,10 @@ get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
{
struct msr val;
- rdmsrq(MTRRphysBase_MSR(index), val.q);
+ val.q = rdmsrq(MTRRphysBase_MSR(index));
vr->base_lo = val.l;
vr->base_hi = val.h;
- rdmsrq(MTRRphysMask_MSR(index), val.q);
+ val.q = rdmsrq(MTRRphysMask_MSR(index));
vr->mask_lo = val.l;
vr->mask_hi = val.h;
}
@@ -588,12 +588,12 @@ static void get_fixed_ranges(mtrr_type *frs)
k8_check_syscfg_dram_mod_en();
- rdmsrq(MSR_MTRRfix64K_00000, p[0]);
+ p[0] = rdmsrq(MSR_MTRRfix64K_00000);
for (i = 0; i < 2; i++)
- rdmsrq(MSR_MTRRfix16K_80000 + i, p[1 + i]);
+ p[1 + i] = rdmsrq(MSR_MTRRfix16K_80000 + i);
for (i = 0; i < 8; i++)
- rdmsrq(MSR_MTRRfix4K_C0000 + i, p[3 + i]);
+ p[3 + i] = rdmsrq(MSR_MTRRfix4K_C0000 + i);
}
void mtrr_save_fixed_ranges(void *info)
@@ -700,7 +700,7 @@ bool __init get_mtrr_state(void)
vrs = mtrr_state.var_ranges;
- rdmsrq(MSR_MTRRcap, q);
+ q = rdmsrq(MSR_MTRRcap);
mtrr_state.have_fixed = q & MTRR_CAP_FIX;
for (i = 0; i < num_var_ranges; i++)
@@ -708,13 +708,13 @@ bool __init get_mtrr_state(void)
if (mtrr_state.have_fixed)
get_fixed_ranges(mtrr_state.fixed_ranges);
- rdmsrq(MSR_MTRRdefType, q);
+ q = rdmsrq(MSR_MTRRdefType);
mtrr_state.def_type = q & MTRR_DEF_TYPE_TYPE;
mtrr_state.enabled = (q & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT;
if (amd_special_default_mtrr()) {
/* TOP_MEM2 */
- rdmsrq(MSR_K8_TOP_MEM2, mtrr_tom2);
+ mtrr_tom2 = rdmsrq(MSR_K8_TOP_MEM2);
mtrr_tom2 &= 0xffffff800000ULL;
}
@@ -770,7 +770,7 @@ static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
{
struct msr val;
- rdmsrq(msr, val.q);
+ val.q = rdmsrq(msr);
if (val.l != msrwords[0] || val.h != msrwords[1]) {
mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
@@ -818,7 +818,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
*/
get_cpu();
- rdmsrq(MTRRphysMask_MSR(reg), mask);
+ mask = rdmsrq(MTRRphysMask_MSR(reg));
if (!(mask & MTRR_PHYSMASK_V)) {
/* Invalid (i.e. free) range */
@@ -828,7 +828,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
goto out_put_cpu;
}
- rdmsrq(MTRRphysBase_MSR(reg), base_msr);
+ base_msr = rdmsrq(MTRRphysBase_MSR(reg));
/* Work out the shifted address mask: */
tmp = mask & PAGE_MASK;
@@ -889,7 +889,7 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
bool changed = false;
struct msr val;
- rdmsrq(MTRRphysBase_MSR(index), val.q);
+ val.q = rdmsrq(MTRRphysBase_MSR(index));
if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) != (val.l & ~MTRR_PHYSBASE_RSVD)
|| (vr->base_hi & ~phys_hi_rsvd) != (val.h & ~phys_hi_rsvd)) {
@@ -897,7 +897,7 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
changed = true;
}
- rdmsrq(MTRRphysMask_MSR(index), val.q);
+ val.q = rdmsrq(MTRRphysMask_MSR(index));
if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) != (val.l & ~MTRR_PHYSMASK_RSVD)
|| (vr->mask_hi & ~phys_hi_rsvd) != (val.h & ~phys_hi_rsvd)) {
@@ -952,7 +952,7 @@ void mtrr_disable(void)
struct msr val;
/* Save MTRR state */
- rdmsrq(MSR_MTRRdefType, val.q);
+ val.q = rdmsrq(MSR_MTRRdefType);
deftype_lo = val.l;
deftype_hi = val.h;
@@ -1065,7 +1065,7 @@ static int generic_have_wrcomb(void)
{
u64 config;
- rdmsrq(MSR_MTRRcap, config);
+ config = rdmsrq(MSR_MTRRcap);
return config & MTRR_CAP_WC;
}
diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c
index 468c53b20acf..9b7abd58b677 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.c
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.c
@@ -571,7 +571,7 @@ void __init mtrr_bp_init(void)
if (mtrr_enabled()) {
/* Get the number of variable MTRR ranges. */
if (mtrr_if == &generic_mtrr_ops)
- rdmsrq(MSR_MTRRcap, config);
+ config = rdmsrq(MSR_MTRRcap);
else
config = mtrr_if->var_regs;
num_var_ranges = config & MTRR_CAP_VCNT;
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index f452e8ce4cef..d4fc3964a4f1 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -165,7 +165,7 @@ static inline void cache_alloc_hsw_probe(void)
if (wrmsrq_safe(MSR_IA32_L3_CBM_BASE, max_cbm))
return;
- rdmsrq(MSR_IA32_L3_CBM_BASE, l3_cbm_0);
+ l3_cbm_0 = rdmsrq(MSR_IA32_L3_CBM_BASE);
/* If all the bits were set in MSR, return success */
if (l3_cbm_0 != max_cbm)
diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c
index 153dc5a268a4..591f4837ae1a 100644
--- a/arch/x86/kernel/cpu/resctrl/monitor.c
+++ b/arch/x86/kernel/cpu/resctrl/monitor.c
@@ -147,7 +147,7 @@ static int __rmid_read_phys(u32 prmid, enum resctrl_event_id eventid, u64 *val)
* are error bits.
*/
wrmsrq(MSR_IA32_QM_EVTSEL, msr_val.q);
- rdmsrq(MSR_IA32_QM_CTR, msr_val.q);
+ msr_val.q = rdmsrq(MSR_IA32_QM_CTR);
if (msr_val.q & RMID_VAL_ERROR)
return -EIO;
@@ -305,7 +305,7 @@ static int __cntr_id_read(u32 cntr_id, u64 *val)
* is set if the counter data is unavailable.
*/
wrmsrq(MSR_IA32_QM_EVTSEL, msr_val.q);
- rdmsrq(MSR_IA32_QM_CTR, msr_val.q);
+ msr_val.q = rdmsrq(MSR_IA32_QM_CTR);
if (msr_val.q & RMID_VAL_ERROR)
return -EIO;
diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
index d7caab0409b6..0408ac7f66fd 100644
--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
@@ -250,7 +250,7 @@ int resctrl_arch_measure_cycles_lat_fn(void *_plr)
/*
* Disable hardware prefetchers.
*/
- rdmsrq(MSR_MISC_FEATURE_CONTROL, saved);
+ saved = rdmsrq(MSR_MISC_FEATURE_CONTROL);
wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);
mem_r = READ_ONCE(plr->kmem);
/*
@@ -346,7 +346,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
/*
* Disable hardware prefetchers.
*/
- rdmsrq(MSR_MISC_FEATURE_CONTROL, saved);
+ saved = rdmsrq(MSR_MISC_FEATURE_CONTROL);
wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);
/* Initialize rest of local variables */
diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
index 885026468440..6f7efe2a7c12 100644
--- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
+++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
@@ -96,7 +96,7 @@ void resctrl_arch_mon_event_config_read(void *_config_info)
pr_warn_once("Invalid event id %d\n", config_info->evtid);
return;
}
- rdmsrq(MSR_IA32_EVT_CFG_BASE + index, msrval);
+ msrval = rdmsrq(MSR_IA32_EVT_CFG_BASE + index);
/* Report only the valid event configuration bits */
config_info->mon_config = msrval & MAX_EVT_CONFIG_BITS;
diff --git a/arch/x86/kernel/cpu/topology.c b/arch/x86/kernel/cpu/topology.c
index 4913b64ec592..68337da5aa09 100644
--- a/arch/x86/kernel/cpu/topology.c
+++ b/arch/x86/kernel/cpu/topology.c
@@ -151,7 +151,7 @@ static __init bool check_for_real_bsp(u32 apic_id)
* kernel must rely on the firmware enumeration order.
*/
if (has_apic_base) {
- rdmsrq(MSR_IA32_APICBASE, msr);
+ msr = rdmsrq(MSR_IA32_APICBASE);
is_bsp = !!(msr & MSR_IA32_APICBASE_BSP);
}
diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topology_amd.c
index da080d732e10..2e05f21be2da 100644
--- a/arch/x86/kernel/cpu/topology_amd.c
+++ b/arch/x86/kernel/cpu/topology_amd.c
@@ -140,7 +140,7 @@ static void parse_fam10h_node_id(struct topo_scan *tscan)
if (!boot_cpu_has(X86_FEATURE_NODEID_MSR))
return;
- rdmsrq(MSR_FAM10H_NODE_ID, nid.msr);
+ nid.msr = rdmsrq(MSR_FAM10H_NODE_ID);
store_node(tscan, nid.nodes_per_pkg + 1, nid.node_id);
tscan->c->topo.llc_id = nid.node_id;
}
@@ -168,7 +168,7 @@ static void topoext_fixup(struct topo_scan *tscan)
MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT) <= 0)
return;
- rdmsrq(MSR_AMD64_CPUID_EXT_FEAT, msrval);
+ msrval = rdmsrq(MSR_AMD64_CPUID_EXT_FEAT);
if (msrval & MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT) {
set_cpu_cap(c, X86_FEATURE_TOPOEXT);
pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c
index c670fbb6ee50..6c2755acc7f1 100644
--- a/arch/x86/kernel/cpu/transmeta.c
+++ b/arch/x86/kernel/cpu/transmeta.c
@@ -87,7 +87,7 @@ static void init_transmeta(struct cpuinfo_x86 *c)
}
/* Unhide possibly hidden capability flags */
- rdmsrq(0x80860004, msr);
+ msr = rdmsrq(0x80860004);
wrmsrq(0x80860004, msr | ~0U);
c->x86_capability[CPUID_1_EDX] = cpuid_edx(0x00000001);
wrmsrq(0x80860004, msr);
diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c
index 209b5a22d880..b500845d2049 100644
--- a/arch/x86/kernel/cpu/tsx.c
+++ b/arch/x86/kernel/cpu/tsx.c
@@ -35,7 +35,7 @@ static void tsx_disable(void)
{
u64 tsx;
- rdmsrq(MSR_IA32_TSX_CTRL, tsx);
+ tsx = rdmsrq(MSR_IA32_TSX_CTRL);
/* Force all transactions to immediately abort */
tsx |= TSX_CTRL_RTM_DISABLE;
@@ -55,7 +55,7 @@ static void tsx_enable(void)
{
u64 tsx;
- rdmsrq(MSR_IA32_TSX_CTRL, tsx);
+ tsx = rdmsrq(MSR_IA32_TSX_CTRL);
/* Enable the RTM feature in the cpu */
tsx &= ~TSX_CTRL_RTM_DISABLE;
@@ -126,11 +126,11 @@ static void tsx_clear_cpuid(void)
*/
if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) &&
boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
- rdmsrq(MSR_TSX_FORCE_ABORT, msr);
+ msr = rdmsrq(MSR_TSX_FORCE_ABORT);
msr |= MSR_TFA_TSX_CPUID_CLEAR;
wrmsrq(MSR_TSX_FORCE_ABORT, msr);
} else if (cpu_feature_enabled(X86_FEATURE_MSR_TSX_CTRL)) {
- rdmsrq(MSR_IA32_TSX_CTRL, msr);
+ msr = rdmsrq(MSR_IA32_TSX_CTRL);
msr |= TSX_CTRL_CPUID_CLEAR;
wrmsrq(MSR_IA32_TSX_CTRL, msr);
}
@@ -157,7 +157,7 @@ static void tsx_dev_mode_disable(void)
!cpu_feature_enabled(X86_FEATURE_SRBDS_CTRL))
return;
- rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_opt_ctrl);
+ mcu_opt_ctrl = rdmsrq(MSR_IA32_MCU_OPT_CTRL);
if (mcu_opt_ctrl & RTM_ALLOW) {
mcu_opt_ctrl &= ~RTM_ALLOW;
diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c
index e4a31c536642..8c3cf0f95e9a 100644
--- a/arch/x86/kernel/cpu/umwait.c
+++ b/arch/x86/kernel/cpu/umwait.c
@@ -218,7 +218,7 @@ static int __init umwait_init(void)
* changed. This is the only place where orig_umwait_control_cached
* is modified.
*/
- rdmsrq(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached);
+ orig_umwait_control_cached = rdmsrq(MSR_IA32_UMWAIT_CONTROL);
ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "umwait:online",
umwait_cpu_online, umwait_cpu_offline);
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index fe504fd43c77..f89aec38a349 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -29,7 +29,7 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
/* Enable ACE unit, if present and disabled */
if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
- rdmsrq(MSR_ZHAOXIN_FCR57, msr);
+ msr = rdmsrq(MSR_ZHAOXIN_FCR57);
/* Enable ACE unit */
wrmsrq(MSR_ZHAOXIN_FCR57, msr | ACE_FCR);
pr_info("CPU: Enabled ACE h/w crypto\n");
@@ -37,7 +37,7 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
/* Enable RNG unit, if present and disabled */
if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
- rdmsrq(MSR_ZHAOXIN_FCR57, msr);
+ msr = rdmsrq(MSR_ZHAOXIN_FCR57);
/* Enable RNG unit */
wrmsrq(MSR_ZHAOXIN_FCR57, msr | RNG_ENABLE);
pr_info("CPU: Enabled h/w RNG\n");
diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c
index 584fb9913be4..322398aa83bf 100644
--- a/arch/x86/kernel/fpu/core.c
+++ b/arch/x86/kernel/fpu/core.c
@@ -364,7 +364,7 @@ void fpu_sync_guest_vmexit_xfd_state(void)
lockdep_assert_irqs_disabled();
if (fpu_state_size_dynamic()) {
- rdmsrq(MSR_IA32_XFD, fpstate->xfd);
+ fpstate->xfd = rdmsrq(MSR_IA32_XFD);
__this_cpu_write(xfd_state, fpstate->xfd);
}
}
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 8dc7b710e125..8a27b9ae9fc7 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -971,7 +971,7 @@ static bool __init hpet_is_pc10_damaged(void)
return false;
/* Check whether PC10 is enabled in PKG C-state limit */
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, pcfg);
+ pcfg = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
if ((pcfg & 0xF) < 8)
return false;
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index dcef84da304b..e773e94c14ea 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -738,7 +738,7 @@ static int kvm_suspend(void *data)
#ifdef CONFIG_ARCH_CPUIDLE_HALTPOLL
if (kvm_para_has_feature(KVM_FEATURE_POLL_CONTROL))
- rdmsrq(MSR_KVM_POLL_CONTROL, val);
+ val = rdmsrq(MSR_KVM_POLL_CONTROL);
has_guest_poll = !(val & 1);
#endif
return 0;
diff --git a/arch/x86/kernel/mmconf-fam10h_64.c b/arch/x86/kernel/mmconf-fam10h_64.c
index ef6104e7cc72..348ac8fce3ad 100644
--- a/arch/x86/kernel/mmconf-fam10h_64.c
+++ b/arch/x86/kernel/mmconf-fam10h_64.c
@@ -97,7 +97,7 @@ static void get_fam10h_pci_mmconf_base(void)
/* SYS_CFG */
address = MSR_AMD64_SYSCFG;
- rdmsrq(address, val);
+ val = rdmsrq(address);
/* TOP_MEM2 is not enabled? */
if (!(val & (1<<21))) {
@@ -105,7 +105,7 @@ static void get_fam10h_pci_mmconf_base(void)
} else {
/* TOP_MEM2 */
address = MSR_K8_TOP_MEM2;
- rdmsrq(address, val);
+ val = rdmsrq(address);
tom2 = max(val & 0xffffff800000ULL, 1ULL << 32);
}
@@ -177,7 +177,7 @@ void fam10h_check_enable_mmcfg(void)
return;
address = MSR_FAM10H_MMIO_CONF_BASE;
- rdmsrq(address, val);
+ val = rdmsrq(address);
/* try to make sure that AP's setting is identical to BSP setting */
if (val & FAM10H_MMIO_CONF_ENABLE) {
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 85435044e33c..2fcf872f9854 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -730,7 +730,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
arch_has_block_step()) {
unsigned long debugctl, msk;
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
+ debugctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
debugctl &= ~DEBUGCTLMSR_BTF;
msk = tifn & _TIF_BLOCKSTEP;
debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
@@ -980,7 +980,7 @@ void __init arch_post_acpi_subsys_init(void)
* the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
* MSR_K8_INT_PENDING_MSG.
*/
- rdmsrq(MSR_K8_INT_PENDING_MSG, val);
+ val = rdmsrq(MSR_K8_INT_PENDING_MSG);
if (!(val & K8_INTP_C1E_ACTIVE_MASK))
return;
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index d44afbe005bb..cec5aba41776 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -97,8 +97,8 @@ void __show_regs(struct pt_regs *regs, enum show_regs_mode mode,
return;
if (mode == SHOW_REGS_USER) {
- rdmsrq(MSR_FS_BASE, fs);
- rdmsrq(MSR_KERNEL_GS_BASE, shadowgs);
+ fs = rdmsrq(MSR_FS_BASE);
+ shadowgs = rdmsrq(MSR_KERNEL_GS_BASE);
printk("%sFS: %016lx GS: %016lx\n",
log_lvl, fs, shadowgs);
return;
@@ -109,9 +109,9 @@ void __show_regs(struct pt_regs *regs, enum show_regs_mode mode,
savesegment(fs, fsindex);
savesegment(gs, gsindex);
- rdmsrq(MSR_FS_BASE, fs);
- rdmsrq(MSR_GS_BASE, gs);
- rdmsrq(MSR_KERNEL_GS_BASE, shadowgs);
+ fs = rdmsrq(MSR_FS_BASE);
+ gs = rdmsrq(MSR_GS_BASE);
+ shadowgs = rdmsrq(MSR_KERNEL_GS_BASE);
cr0 = read_cr0();
cr2 = read_cr2();
@@ -197,7 +197,7 @@ static noinstr unsigned long __rdgsbase_inactive(void)
native_swapgs();
} else {
instrumentation_begin();
- rdmsrq(MSR_KERNEL_GS_BASE, gsbase);
+ gsbase = rdmsrq(MSR_KERNEL_GS_BASE);
instrumentation_end();
}
@@ -463,7 +463,7 @@ unsigned long x86_gsbase_read_cpu_inactive(void)
gsbase = __rdgsbase_inactive();
local_irq_restore(flags);
} else {
- rdmsrq(MSR_KERNEL_GS_BASE, gsbase);
+ gsbase = rdmsrq(MSR_KERNEL_GS_BASE);
}
return gsbase;
diff --git a/arch/x86/kernel/shstk.c b/arch/x86/kernel/shstk.c
index 0ca64900192f..f3d1f385c626 100644
--- a/arch/x86/kernel/shstk.c
+++ b/arch/x86/kernel/shstk.c
@@ -231,7 +231,7 @@ static unsigned long get_user_shstk_addr(void)
fpregs_lock_and_load();
- rdmsrq(MSR_IA32_PL3_SSP, ssp);
+ ssp = rdmsrq(MSR_IA32_PL3_SSP);
fpregs_unlock();
@@ -248,7 +248,7 @@ int shstk_pop(u64 *val)
fpregs_lock_and_load();
- rdmsrq(MSR_IA32_PL3_SSP, ssp);
+ ssp = rdmsrq(MSR_IA32_PL3_SSP);
if (val && get_user(*val, (__user u64 *)ssp))
ret = -EFAULT;
else
@@ -268,7 +268,7 @@ int shstk_push(u64 val)
fpregs_lock_and_load();
- rdmsrq(MSR_IA32_PL3_SSP, ssp);
+ ssp = rdmsrq(MSR_IA32_PL3_SSP);
ssp -= SS_FRAME_SIZE;
ret = write_user_shstk_64((__user void *)ssp, val);
if (!ret)
@@ -497,7 +497,7 @@ static int wrss_control(bool enable)
return 0;
fpregs_lock_and_load();
- rdmsrq(MSR_IA32_U_CET, msrval);
+ msrval = rdmsrq(MSR_IA32_U_CET);
if (enable) {
features_set(ARCH_SHSTK_WRSS);
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 30aa8369957e..9cd11dc7bb17 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -1250,7 +1250,7 @@ static noinstr void exc_debug_kernel(struct pt_regs *regs, unsigned long dr6)
*/
unsigned long debugctl;
- rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
+ debugctl = rdmsrq(MSR_IA32_DEBUGCTLMSR);
debugctl |= DEBUGCTLMSR_BTF;
wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
}
@@ -1509,7 +1509,7 @@ static bool handle_xfd_event(struct pt_regs *regs)
if (!IS_ENABLED(CONFIG_X86_64) || !cpu_feature_enabled(X86_FEATURE_XFD))
return false;
- rdmsrq(MSR_IA32_XFD_ERR, xfd_err);
+ xfd_err = rdmsrq(MSR_IA32_XFD_ERR);
if (!xfd_err)
return false;
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 723347e2cf7f..39baee2307c3 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1088,7 +1088,7 @@ static void __init detect_art(void)
if (art_base_clk.denominator < ART_MIN_DENOMINATOR)
return;
- rdmsrq(MSR_IA32_TSC_ADJUST, art_base_clk.offset);
+ art_base_clk.offset = rdmsrq(MSR_IA32_TSC_ADJUST);
/* Make this sticky over multiple CPU init calls */
setup_force_cpu_cap(X86_FEATURE_ART);
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index d74743c8d2a4..6a1d22e8b846 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -179,15 +179,15 @@ unsigned long cpu_khz_from_msr(void)
freq_desc = (struct freq_desc *)id->driver_data;
if (freq_desc->use_msr_plat) {
- rdmsrq(MSR_PLATFORM_INFO, val.q);
+ val.q = rdmsrq(MSR_PLATFORM_INFO);
ratio = (val.l >> 8) & 0xff;
} else {
- rdmsrq(MSR_IA32_PERF_STATUS, val.q);
+ val.q = rdmsrq(MSR_IA32_PERF_STATUS);
ratio = (val.h >> 8) & 0x1f;
}
/* Get FSB FREQ ID */
- rdmsrq(MSR_FSB_FREQ, val.q);
+ val.q = rdmsrq(MSR_FSB_FREQ);
index = val.l & freq_desc->mask;
md = &freq_desc->muldiv[index];
diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index ec3aa340d351..a21ea3c85f6f 100644
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -66,7 +66,7 @@ void tsc_verify_tsc_adjust(bool resume)
adj->nextcheck = jiffies + HZ;
- rdmsrq(MSR_IA32_TSC_ADJUST, curval);
+ curval = rdmsrq(MSR_IA32_TSC_ADJUST);
if (adj->adjusted == curval)
return;
@@ -166,7 +166,7 @@ bool __init tsc_store_and_check_tsc_adjust(bool bootcpu)
if (check_tsc_unstable())
return false;
- rdmsrq(MSR_IA32_TSC_ADJUST, bootval);
+ bootval = rdmsrq(MSR_IA32_TSC_ADJUST);
cur->bootval = bootval;
cur->nextcheck = jiffies + HZ;
tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), bootcpu);
@@ -188,7 +188,7 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu)
if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
return false;
- rdmsrq(MSR_IA32_TSC_ADJUST, bootval);
+ bootval = rdmsrq(MSR_IA32_TSC_ADJUST);
cur->bootval = bootval;
cur->nextcheck = jiffies + HZ;
cur->warned = false;
diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c
index c18286545a7a..5ebee82dba84 100644
--- a/arch/x86/kvm/svm/pmu.c
+++ b/arch/x86/kvm/svm/pmu.c
@@ -249,7 +249,7 @@ static void amd_mediated_pmu_load(struct kvm_vcpu *vcpu)
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
u64 global_status;
- rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, global_status);
+ global_status = rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS);
/* Clear host global_status MSR if non-zero. */
if (global_status)
wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, global_status);
@@ -263,7 +263,7 @@ static void amd_mediated_pmu_put(struct kvm_vcpu *vcpu)
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);
- rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, pmu->global_status);
+ pmu->global_status = rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS);
/* Clear global status bits if non-zero */
if (pmu->global_status)
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 9658ce4e0294..977112d8713c 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -4619,7 +4619,7 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu, u64 run_flags)
kvm_clear_available_registers(vcpu, SVM_REGS_LAZY_LOAD_SET);
if (!msr_write_intercepted(svm, MSR_AMD64_PERF_CNTR_GLOBAL_CTL))
- rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, vcpu_to_pmu(vcpu)->global_ctrl);
+ vcpu_to_pmu(vcpu)->global_ctrl = rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL);
trace_kvm_exit(vcpu, KVM_ISA_SVM);
@@ -5482,7 +5482,7 @@ static __init void svm_adjust_mmio_mask(void)
return;
/* If memory encryption is not enabled, use existing mask */
- rdmsrq(MSR_AMD64_SYSCFG, msr);
+ msr = rdmsrq(MSR_AMD64_SYSCFG);
if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
return;
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 6957bb6f5cf7..920521796743 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -7352,8 +7352,8 @@ static void nested_vmx_setup_cr_fixed(struct nested_vmx_msrs *msrs)
msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON;
/* These MSRs specify bits which the guest must keep fixed off. */
- rdmsrq(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1);
- rdmsrq(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1);
+ msrs->cr0_fixed1 = rdmsrq(MSR_IA32_VMX_CR0_FIXED1);
+ msrs->cr4_fixed1 = rdmsrq(MSR_IA32_VMX_CR4_FIXED1);
if (vmx_umip_emulated())
msrs->cr4_fixed1 |= X86_CR4_UMIP;
diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 1944939c4139..5eb5636704bc 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -320,7 +320,7 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
int err = 0;
if (read)
- rdmsrq(index, msr_info->data);
+ msr_info->data = rdmsrq(index);
else
err = wrmsrq_safe(index, msr_info->data);
__set_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
@@ -772,7 +772,7 @@ static bool intel_pmu_is_mediated_pmu_supported(struct x86_pmu_capability *host_
u64 host_perf_cap = 0;
if (boot_cpu_has(X86_FEATURE_PDCM))
- rdmsrq(MSR_IA32_PERF_CAPABILITIES, host_perf_cap);
+ host_perf_cap = rdmsrq(MSR_IA32_PERF_CAPABILITIES);
/*
* Require v4+ for MSR_CORE_PERF_GLOBAL_STATUS_SET, and full-width
@@ -802,7 +802,7 @@ static void intel_mediated_pmu_load(struct kvm_vcpu *vcpu)
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
u64 global_status, toggle;
- rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, global_status);
+ global_status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
toggle = pmu->global_status ^ global_status;
if (global_status & toggle)
wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, global_status & toggle);
@@ -817,7 +817,7 @@ static void intel_mediated_pmu_put(struct kvm_vcpu *vcpu)
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
/* MSR_CORE_PERF_GLOBAL_CTRL is already saved at VM-exit. */
- rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, pmu->global_status);
+ pmu->global_status = rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS);
/* Clear hardware MSR_CORE_PERF_GLOBAL_STATUS MSR, if non-zero. */
if (pmu->global_status)
diff --git a/arch/x86/kvm/vmx/sgx.c b/arch/x86/kvm/vmx/sgx.c
index 771c75a58343..765cac151023 100644
--- a/arch/x86/kvm/vmx/sgx.c
+++ b/arch/x86/kvm/vmx/sgx.c
@@ -420,9 +420,9 @@ void setup_default_sgx_lepubkeyhash(void)
sgx_pubkey_hash[3] = 0xd4f8c05909f9bb3bULL;
} else {
/* MSR_IA32_SGXLEPUBKEYHASH0 is read above */
- rdmsrq(MSR_IA32_SGXLEPUBKEYHASH1, sgx_pubkey_hash[1]);
- rdmsrq(MSR_IA32_SGXLEPUBKEYHASH2, sgx_pubkey_hash[2]);
- rdmsrq(MSR_IA32_SGXLEPUBKEYHASH3, sgx_pubkey_hash[3]);
+ sgx_pubkey_hash[1] = rdmsrq(MSR_IA32_SGXLEPUBKEYHASH1);
+ sgx_pubkey_hash[2] = rdmsrq(MSR_IA32_SGXLEPUBKEYHASH2);
+ sgx_pubkey_hash[3] = rdmsrq(MSR_IA32_SGXLEPUBKEYHASH3);
}
}
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 49948bbaf2de..3d53b5bb6914 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -1246,13 +1246,13 @@ static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
{
u32 i;
- rdmsrq(MSR_IA32_RTIT_STATUS, ctx->status);
- rdmsrq(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
- rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
- rdmsrq(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
+ ctx->status = rdmsrq(MSR_IA32_RTIT_STATUS);
+ ctx->output_base = rdmsrq(MSR_IA32_RTIT_OUTPUT_BASE);
+ ctx->output_mask = rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK);
+ ctx->cr3_match = rdmsrq(MSR_IA32_RTIT_CR3_MATCH);
for (i = 0; i < addr_range; i++) {
- rdmsrq(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
- rdmsrq(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
+ ctx->addr_a[i] = rdmsrq(MSR_IA32_RTIT_ADDR0_A + i * 2);
+ ctx->addr_b[i] = rdmsrq(MSR_IA32_RTIT_ADDR0_B + i * 2);
}
}
@@ -1265,7 +1265,7 @@ static void pt_guest_enter(struct vcpu_vmx *vmx)
* GUEST_IA32_RTIT_CTL is already set in the VMCS.
* Save host state before VM entry.
*/
- rdmsrq(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
+ vmx->pt_desc.host.ctl = rdmsrq(MSR_IA32_RTIT_CTL);
if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
wrmsrq(MSR_IA32_RTIT_CTL, 0);
pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges);
@@ -1403,7 +1403,7 @@ static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
++vmx->vcpu.stat.host_state_reload;
#ifdef CONFIG_X86_64
- rdmsrq(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
+ vmx->msr_guest_kernel_gs_base = rdmsrq(MSR_KERNEL_GS_BASE);
#endif
if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
kvm_load_ldt(host_state->ldt_sel);
@@ -2679,7 +2679,7 @@ static int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, u32 msr, u32 *result)
struct msr vmx_msr;
u32 ctl = ctl_min | ctl_opt;
- rdmsrq(msr, vmx_msr.q);
+ vmx_msr.q = rdmsrq(msr);
ctl &= vmx_msr.h; /* bit == 0 in high word ==> must be zero */
ctl |= vmx_msr.l; /* bit == 1 in low word ==> must be one */
@@ -2696,7 +2696,7 @@ static u64 adjust_vmx_controls64(u64 ctl_opt, u32 msr)
{
u64 allowed;
- rdmsrq(msr, allowed);
+ allowed = rdmsrq(msr);
return ctl_opt & allowed;
}
@@ -2882,7 +2882,7 @@ static int setup_vmcs_config(struct vmcs_config *vmcs_conf,
break;
}
- rdmsrq(MSR_IA32_VMX_BASIC, basic_msr);
+ basic_msr = rdmsrq(MSR_IA32_VMX_BASIC);
/* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
if (vmx_basic_vmcs_size(basic_msr) > PAGE_SIZE)
@@ -2902,7 +2902,7 @@ static int setup_vmcs_config(struct vmcs_config *vmcs_conf,
if (vmx_basic_vmcs_mem_type(basic_msr) != X86_MEMTYPE_WB)
return -EIO;
- rdmsrq(MSR_IA32_VMX_MISC, misc_msr);
+ misc_msr = rdmsrq(MSR_IA32_VMX_MISC);
vmcs_conf->basic = basic_msr;
vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
@@ -4478,7 +4478,7 @@ void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
- rdmsrq(MSR_IA32_SYSENTER_CS, val.q);
+ val.q = rdmsrq(MSR_IA32_SYSENTER_CS);
vmcs_write32(HOST_IA32_SYSENTER_CS, val.l);
/*
@@ -4490,11 +4490,11 @@ void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
if (!IS_ENABLED(CONFIG_IA32_EMULATION) && !IS_ENABLED(CONFIG_X86_32))
vmcs_writel(HOST_IA32_SYSENTER_ESP, 0);
- rdmsrq(MSR_IA32_SYSENTER_EIP, tmpl);
+ tmpl = rdmsrq(MSR_IA32_SYSENTER_EIP);
vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
- rdmsrq(MSR_IA32_CR_PAT, val.q);
+ val.q = rdmsrq(MSR_IA32_CR_PAT);
vmcs_write64(HOST_IA32_PAT, val.q);
}
@@ -7152,7 +7152,7 @@ static void handle_nm_fault_irqoff(struct kvm_vcpu *vcpu)
* the #NM exception.
*/
if (is_xfd_nm_fault(vcpu))
- rdmsrq(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
+ vcpu->arch.guest_fpu.xfd_err = rdmsrq(MSR_IA32_XFD_ERR);
}
static void handle_exception_irqoff(struct kvm_vcpu *vcpu, u32 intr_info)
@@ -8043,7 +8043,7 @@ static __init u64 vmx_get_perf_capabilities(void)
return 0;
if (boot_cpu_has(X86_FEATURE_PDCM))
- rdmsrq(MSR_IA32_PERF_CAPABILITIES, host_perf_cap);
+ host_perf_cap = rdmsrq(MSR_IA32_PERF_CAPABILITIES);
if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) &&
!enable_mediated_pmu) {
@@ -8600,7 +8600,7 @@ __init int vmx_hardware_setup(void)
vmx_setup_user_return_msrs();
if (boot_cpu_has(X86_FEATURE_MPX)) {
- rdmsrq(MSR_IA32_BNDCFGS, host_bndcfgs);
+ host_bndcfgs = rdmsrq(MSR_IA32_BNDCFGS);
WARN_ONCE(host_bndcfgs, "BNDCFGS in host will be lost");
}
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 9b645563ece9..7abe482efe46 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -3859,7 +3859,7 @@ static __always_inline void kvm_access_xstate_msr(struct kvm_vcpu *vcpu,
kvm_fpu_get();
if (access == MSR_TYPE_R)
- rdmsrq(msr_info->index, msr_info->data);
+ msr_info->data = rdmsrq(msr_info->index);
else
wrmsrq(msr_info->index, msr_info->data);
kvm_fpu_put();
@@ -10098,7 +10098,7 @@ int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
}
if (boot_cpu_has(X86_FEATURE_SHSTK) || boot_cpu_has(X86_FEATURE_IBT)) {
- rdmsrq(MSR_IA32_S_CET, kvm_host.s_cet);
+ kvm_host.s_cet = rdmsrq(MSR_IA32_S_CET);
/*
* Linux doesn't yet support supervisor shadow stacks (SSS), so
* KVM doesn't save/restore the associated MSRs, i.e. KVM may
@@ -10130,7 +10130,7 @@ int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
}
if (boot_cpu_has(X86_FEATURE_XSAVES)) {
- rdmsrq(MSR_IA32_XSS, kvm_host.xss);
+ kvm_host.xss = rdmsrq(MSR_IA32_XSS);
kvm_caps.supported_xss = kvm_host.xss & KVM_SUPPORTED_XSS;
}
@@ -10142,7 +10142,7 @@ int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
kvm_init_pmu_capability(ops->pmu_ops);
if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
- rdmsrq(MSR_IA32_ARCH_CAPABILITIES, kvm_host.arch_capabilities);
+ kvm_host.arch_capabilities = rdmsrq(MSR_IA32_ARCH_CAPABILITIES);
WARN_ON_ONCE(kvm_nr_uret_msrs);
diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c
index e03eeec55cfe..b9db2012a75e 100644
--- a/arch/x86/lib/insn-eval.c
+++ b/arch/x86/lib/insn-eval.c
@@ -709,16 +709,16 @@ unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx)
unsigned long base;
if (seg_reg_idx == INAT_SEG_REG_FS) {
- rdmsrq(MSR_FS_BASE, base);
+ base = rdmsrq(MSR_FS_BASE);
} else if (seg_reg_idx == INAT_SEG_REG_GS) {
/*
* swapgs was called at the kernel entry point. Thus,
* MSR_KERNEL_GS_BASE will have the user-space GS base.
*/
if (user_mode(regs))
- rdmsrq(MSR_KERNEL_GS_BASE, base);
+ base = rdmsrq(MSR_KERNEL_GS_BASE);
else
- rdmsrq(MSR_GS_BASE, base);
+ base = rdmsrq(MSR_GS_BASE);
} else {
base = 0;
}
diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c
index 7b6cfc2c0970..ddff68050322 100644
--- a/arch/x86/lib/msr-smp.c
+++ b/arch/x86/lib/msr-smp.c
@@ -15,7 +15,7 @@ static void __rdmsr_on_cpu(void *info)
else
reg = &rv->reg;
- rdmsrq(rv->msr_no, reg->q);
+ reg->q = rdmsrq(rv->msr_no);
}
static void __wrmsr_on_cpu(void *info)
diff --git a/arch/x86/mm/pat/memtype.c b/arch/x86/mm/pat/memtype.c
index cf94fb561310..114853c212ed 100644
--- a/arch/x86/mm/pat/memtype.c
+++ b/arch/x86/mm/pat/memtype.c
@@ -257,7 +257,7 @@ void __init pat_bp_init(void)
if (!cpu_feature_enabled(X86_FEATURE_PAT))
pat_disable("PAT not supported by the CPU.");
else
- rdmsrq(MSR_IA32_CR_PAT, pat_msr_val);
+ pat_msr_val = rdmsrq(MSR_IA32_CR_PAT);
if (!pat_msr_val) {
pat_disable("PAT support disabled by the firmware.");
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index 99b1727136c1..342371081f60 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -202,7 +202,7 @@ static int __init early_root_info_init(void)
/* need to take out [0, TOM) for RAM*/
address = MSR_K8_TOP_MEM1;
- rdmsrq(address, val);
+ val = rdmsrq(address);
end = (val & 0xffffff800000ULL);
printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
if (end < (1ULL<<32))
@@ -293,12 +293,12 @@ static int __init early_root_info_init(void)
/* need to take out [4G, TOM2) for RAM*/
/* SYS_CFG */
address = MSR_AMD64_SYSCFG;
- rdmsrq(address, val);
+ val = rdmsrq(address);
/* TOP_MEM2 is enabled? */
if (val & (1<<21)) {
/* TOP_MEM2 */
address = MSR_K8_TOP_MEM2;
- rdmsrq(address, val);
+ val = rdmsrq(address);
end = (val & 0xffffff800000ULL);
printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
subtract_range(range, RANGE_NUM, 1ULL<<32, end);
@@ -341,7 +341,7 @@ static int amd_bus_cpu_online(unsigned int cpu)
{
u64 reg;
- rdmsrq(MSR_AMD64_NB_CFG, reg);
+ reg = rdmsrq(MSR_AMD64_NB_CFG);
if (!(reg & ENABLE_CF8_EXT_CFG)) {
reg |= ENABLE_CF8_EXT_CFG;
wrmsrq(MSR_AMD64_NB_CFG, reg);
diff --git a/arch/x86/platform/olpc/olpc-xo1-rtc.c b/arch/x86/platform/olpc/olpc-xo1-rtc.c
index ee77d57bcab7..95dfd90b1f05 100644
--- a/arch/x86/platform/olpc/olpc-xo1-rtc.c
+++ b/arch/x86/platform/olpc/olpc-xo1-rtc.c
@@ -64,9 +64,9 @@ static int __init xo1_rtc_init(void)
of_node_put(node);
pr_info("olpc-xo1-rtc: Initializing OLPC XO-1 RTC\n");
- rdmsrq(MSR_RTC_DOMA_OFFSET, rtc_info.rtc_day_alarm);
- rdmsrq(MSR_RTC_MONA_OFFSET, rtc_info.rtc_mon_alarm);
- rdmsrq(MSR_RTC_CEN_OFFSET, rtc_info.rtc_century);
+ rtc_info.rtc_day_alarm = rdmsrq(MSR_RTC_DOMA_OFFSET);
+ rtc_info.rtc_mon_alarm = rdmsrq(MSR_RTC_MONA_OFFSET);
+ rtc_info.rtc_century = rdmsrq(MSR_RTC_CEN_OFFSET);
r = platform_device_register(&xo1_rtc_device);
if (r)
diff --git a/arch/x86/platform/olpc/olpc-xo1-sci.c b/arch/x86/platform/olpc/olpc-xo1-sci.c
index 97eb4738d602..b2e12d780e58 100644
--- a/arch/x86/platform/olpc/olpc-xo1-sci.c
+++ b/arch/x86/platform/olpc/olpc-xo1-sci.c
@@ -316,7 +316,7 @@ static int setup_sci_interrupt(struct platform_device *pdev)
u32 sts;
int r;
- rdmsrq(0x51400020, msr);
+ msr = rdmsrq(0x51400020);
sci_irq = (msr >> 20) & 15;
if (sci_irq) {
diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index 702f30eaf9c4..f44ebe2fe099 100644
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -45,7 +45,7 @@ static void msr_save_context(struct saved_context *ctxt)
while (msr < end) {
if (msr->valid)
- rdmsrq(msr->info.msr_no, msr->info.reg.q);
+ msr->info.reg.q = rdmsrq(msr->info.msr_no);
msr++;
}
}
@@ -111,12 +111,12 @@ static void __save_processor_state(struct saved_context *ctxt)
savesegment(ds, ctxt->ds);
savesegment(es, ctxt->es);
- rdmsrq(MSR_FS_BASE, ctxt->fs_base);
- rdmsrq(MSR_GS_BASE, ctxt->kernelmode_gs_base);
- rdmsrq(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
+ ctxt->fs_base = rdmsrq(MSR_FS_BASE);
+ ctxt->kernelmode_gs_base = rdmsrq(MSR_GS_BASE);
+ ctxt->usermode_gs_base = rdmsrq(MSR_KERNEL_GS_BASE);
mtrr_save_fixed_ranges(NULL);
- rdmsrq(MSR_EFER, ctxt->efer);
+ ctxt->efer = rdmsrq(MSR_EFER);
#endif
/*
diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c
index 694d80a5c68e..469f2aa8e105 100644
--- a/arch/x86/realmode/init.c
+++ b/arch/x86/realmode/init.c
@@ -147,7 +147,7 @@ static void __init setup_real_mode(void)
* Some AMD processors will #GP(0) if EFER.LMA is set in WRMSR
* so we need to mask it out.
*/
- rdmsrq(MSR_EFER, efer);
+ efer = rdmsrq(MSR_EFER);
trampoline_header->efer = efer & ~EFER_LMA;
trampoline_header->start = (u64) secondary_startup_64;
diff --git a/arch/x86/virt/hw.c b/arch/x86/virt/hw.c
index 7e9091c640be..a2e4b99d7276 100644
--- a/arch/x86/virt/hw.c
+++ b/arch/x86/virt/hw.c
@@ -178,7 +178,7 @@ static __init int __x86_vmx_init(void)
if (!cpu_feature_enabled(X86_FEATURE_VMX))
return -EOPNOTSUPP;
- rdmsrq(MSR_IA32_VMX_BASIC, basic_msr);
+ basic_msr = rdmsrq(MSR_IA32_VMX_BASIC);
/* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
if (WARN_ON_ONCE(vmx_basic_vmcs_size(basic_msr) > PAGE_SIZE))
@@ -230,7 +230,7 @@ static int x86_svm_enable_virtualization_cpu(void)
{
u64 efer;
- rdmsrq(MSR_EFER, efer);
+ efer = rdmsrq(MSR_EFER);
if (efer & EFER_SVME)
return -EBUSY;
@@ -253,7 +253,7 @@ static int x86_svm_disable_virtualization_cpu(void)
r = 0;
fault:
- rdmsrq(MSR_EFER, efer);
+ efer = rdmsrq(MSR_EFER);
wrmsrq(MSR_EFER, efer & ~EFER_SVME);
return r;
}
@@ -264,7 +264,7 @@ static void x86_svm_emergency_disable_virtualization_cpu(void)
virt_rebooting = true;
- rdmsrq(MSR_EFER, efer);
+ efer = rdmsrq(MSR_EFER);
if (!(efer & EFER_SVME))
return;
diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c
index 8bcdce98f6dc..124566c56e59 100644
--- a/arch/x86/virt/svm/sev.c
+++ b/arch/x86/virt/svm/sev.c
@@ -150,7 +150,7 @@ static void snp_enable(void *arg)
if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP))
return;
- rdmsrq(MSR_AMD64_SYSCFG, val);
+ val = rdmsrq(MSR_AMD64_SYSCFG);
val |= MSR_AMD64_SYSCFG_SNP_EN;
val |= MSR_AMD64_SYSCFG_SNP_VMPL_EN;
@@ -254,7 +254,7 @@ static void clear_rmp(void)
return;
/* Clearing the RMP while SNP is enabled will cause an exception */
- rdmsrq(MSR_AMD64_SYSCFG, val);
+ val = rdmsrq(MSR_AMD64_SYSCFG);
if (WARN_ON_ONCE(val & MSR_AMD64_SYSCFG_SNP_EN))
return;
@@ -520,7 +520,7 @@ int snp_prepare(void)
* Check if SEV-SNP is already enabled, this can happen in case of
* kexec boot.
*/
- rdmsrq(MSR_AMD64_SYSCFG, val);
+ val = rdmsrq(MSR_AMD64_SYSCFG);
if (val & MSR_AMD64_SYSCFG_SNP_EN)
return 0;
@@ -559,7 +559,7 @@ void snp_shutdown(void)
{
u64 syscfg;
- rdmsrq(MSR_AMD64_SYSCFG, syscfg);
+ syscfg = rdmsrq(MSR_AMD64_SYSCFG);
if (syscfg & MSR_AMD64_SYSCFG_SNP_EN)
return;
@@ -606,8 +606,8 @@ static bool probe_contiguous_rmptable_info(void)
{
u64 rmp_sz, rmp_base, rmp_end;
- rdmsrq(MSR_AMD64_RMP_BASE, rmp_base);
- rdmsrq(MSR_AMD64_RMP_END, rmp_end);
+ rmp_base = rdmsrq(MSR_AMD64_RMP_BASE);
+ rmp_end = rdmsrq(MSR_AMD64_RMP_END);
if (!(rmp_base & RMP_ADDR_MASK) || !(rmp_end & RMP_ADDR_MASK)) {
pr_err("Memory for the RMP table has not been reserved by BIOS\n");
@@ -640,13 +640,13 @@ static bool probe_segmented_rmptable_info(void)
unsigned int eax, ebx, segment_shift, segment_shift_min, segment_shift_max;
u64 rmp_base, rmp_end;
- rdmsrq(MSR_AMD64_RMP_BASE, rmp_base);
+ rmp_base = rdmsrq(MSR_AMD64_RMP_BASE);
if (!(rmp_base & RMP_ADDR_MASK)) {
pr_err("Memory for the RMP table has not been reserved by BIOS\n");
return false;
}
- rdmsrq(MSR_AMD64_RMP_END, rmp_end);
+ rmp_end = rdmsrq(MSR_AMD64_RMP_END);
WARN_ONCE(rmp_end & RMP_ADDR_MASK,
"Segmented RMP enabled but RMP_END MSR is non-zero\n");
@@ -682,7 +682,7 @@ static bool probe_segmented_rmptable_info(void)
bool snp_probe_rmptable_info(void)
{
if (cpu_feature_enabled(X86_FEATURE_SEGMENTED_RMP))
- rdmsrq(MSR_AMD64_RMP_CFG, rmp_cfg);
+ rmp_cfg = rdmsrq(MSR_AMD64_RMP_CFG);
if (rmp_cfg & MSR_AMD64_SEG_RMP_ENABLED)
return probe_segmented_rmptable_info();
diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c
index 1b9ff749dd8e..9839f5b8dcc3 100644
--- a/arch/x86/virt/vmx/tdx/tdx.c
+++ b/arch/x86/virt/vmx/tdx/tdx.c
@@ -1523,7 +1523,7 @@ static void __init check_tdx_erratum(void)
* Some TDX-capable CPUs have an erratum where the current VMCS is
* cleared after calling into P-SEAMLDR.
*/
- rdmsrq(MSR_IA32_VMX_BASIC, basic_msr);
+ basic_msr = rdmsrq(MSR_IA32_VMX_BASIC);
if (!(basic_msr & VMX_BASIC_NO_SEAMRET_INVD_VMCS))
setup_force_cpu_bug(X86_BUG_SEAMRET_INVD_VMCS);
}
diff --git a/arch/x86/xen/suspend.c b/arch/x86/xen/suspend.c
index ba2f17e64321..b0e1152aa80e 100644
--- a/arch/x86/xen/suspend.c
+++ b/arch/x86/xen/suspend.c
@@ -56,7 +56,7 @@ static void xen_vcpu_notify_suspend(void *data)
tick_suspend_local();
if (xen_pv_domain() && boot_cpu_has(X86_FEATURE_SPEC_CTRL)) {
- rdmsrq(MSR_IA32_SPEC_CTRL, tmp);
+ tmp = rdmsrq(MSR_IA32_SPEC_CTRL);
this_cpu_write(spec_ctrl, tmp);
wrmsrq(MSR_IA32_SPEC_CTRL, 0);
}
diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c
index 9e25d6124efd..535a0f9dd2cf 100644
--- a/drivers/acpi/processor_perflib.c
+++ b/drivers/acpi/processor_perflib.c
@@ -296,7 +296,7 @@ static void amd_fixup_frequency(struct acpi_processor_px *px, int i)
if ((boot_cpu_data.x86 == 0x10 && boot_cpu_data.x86_model < 10) ||
boot_cpu_data.x86 == 0x11) {
- rdmsrq(MSR_AMD_PSTATE_DEF_BASE + index, val.q);
+ val.q = rdmsrq(MSR_AMD_PSTATE_DEF_BASE + index);
/*
* MSR C001_0064+:
* Bit 63: PstateEn. Read-write. If set, the P-state is valid.
diff --git a/drivers/ata/pata_cs5535.c b/drivers/ata/pata_cs5535.c
index da98390cc49e..e38eecaea1b0 100644
--- a/drivers/ata/pata_cs5535.c
+++ b/drivers/ata/pata_cs5535.c
@@ -110,7 +110,7 @@ static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
pio_cmd_timings[cmdmode] << 16 | pio_timings[mode]);
/* Set the PIO "format 1" bit in the DMA timing register */
- rdmsrq(ATAC_CH0D0_DMA + 2 * adev->devno, reg);
+ reg = rdmsrq(ATAC_CH0D0_DMA + 2 * adev->devno);
wrmsrq(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL);
}
@@ -132,7 +132,7 @@ static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
u32 reg;
int mode = adev->dma_mode;
- rdmsrq(ATAC_CH0D0_DMA + 2 * adev->devno, reg);
+ reg = rdmsrq(ATAC_CH0D0_DMA + 2 * adev->devno);
reg &= 0x80000000UL;
if (mode >= XFER_UDMA_0)
reg |= udma_timings[mode - XFER_UDMA_0];
diff --git a/drivers/ata/pata_cs5536.c b/drivers/ata/pata_cs5536.c
index 61d232a82b5e..eca97dce1e85 100644
--- a/drivers/ata/pata_cs5536.c
+++ b/drivers/ata/pata_cs5536.c
@@ -84,7 +84,7 @@ static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
{
#ifdef MAYBE_USE_MSR
if (unlikely(use_msr)) {
- rdmsrq(MSR_IDE_CFG + reg, *val);
+ *val = rdmsrq(MSR_IDE_CFG + reg);
return 0;
}
#endif
diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c
index 3e760bc00afa..f646f1854981 100644
--- a/drivers/char/agp/nvidia-agp.c
+++ b/drivers/char/agp/nvidia-agp.c
@@ -72,8 +72,8 @@ static int nvidia_init_iorr(u32 base, u32 size)
/* If not found, determine the uppermost available iorr */
free_iorr_addr = AMD_K7_NUM_IORR;
for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
- rdmsrq(IORR_BASE0 + 2 * iorr_addr, base_msr.q);
- rdmsrq(IORR_MASK0 + 2 * iorr_addr, mask_msr.q);
+ base_msr.q = rdmsrq(IORR_BASE0 + 2 * iorr_addr);
+ mask_msr.q = rdmsrq(IORR_MASK0 + 2 * iorr_addr);
if ((base_msr.l & 0xfffff000) == (base & 0xfffff000))
break;
@@ -94,7 +94,7 @@ static int nvidia_init_iorr(u32 base, u32 size)
wrmsrq(IORR_BASE0 + 2 * iorr_addr, base_msr.q);
wrmsrq(IORR_MASK0 + 2 * iorr_addr, mask_msr.q);
- rdmsrq(SYSCFG, sys_msr.q);
+ sys_msr.q = rdmsrq(SYSCFG);
sys_msr.l |= 0x00100000;
wrmsrq(SYSCFG, sys_msr.q);
diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c
index b718e78d3c1c..a0a3488a6947 100644
--- a/drivers/char/hw_random/via-rng.c
+++ b/drivers/char/hw_random/via-rng.c
@@ -151,7 +151,7 @@ static int via_rng_init(struct hwrng *rng)
* does not say to write them as zero, so I make a guess that
* we restore the values we find in the register.
*/
- rdmsrq(MSR_VIA_RNG, val.q);
+ val.q = rdmsrq(MSR_VIA_RNG);
old_lo = val.l;
val.l &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
@@ -175,7 +175,7 @@ static int via_rng_init(struct hwrng *rng)
/* perhaps-unnecessary sanity check; remove after testing if
unneeded */
- rdmsrq(MSR_VIA_RNG, val.q);
+ val.q = rdmsrq(MSR_VIA_RNG);
if ((val.l & VIA_RNG_ENABLE) == 0) {
pr_err(PFX "cannot enable VIA C3 RNG, aborting\n");
return -ENODEV;
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index b40fa99b5ab2..cb59ed6926f2 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -110,7 +110,7 @@ static int boost_set_msr(bool enable)
return -EINVAL;
}
- rdmsrq(msr_addr, val);
+ val = rdmsrq(msr_addr);
if (enable)
val &= ~msr_mask;
@@ -248,7 +248,7 @@ static u32 cpu_freq_read_intel(struct acpi_pct_register *not_used)
{
u64 val;
- rdmsrq(MSR_IA32_PERF_CTL, val);
+ val = rdmsrq(MSR_IA32_PERF_CTL);
return (u32)val;
}
@@ -256,7 +256,7 @@ static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val)
{
struct msr msrval;
- rdmsrq(MSR_IA32_PERF_CTL, msrval.q);
+ msrval.q = rdmsrq(MSR_IA32_PERF_CTL);
msrval.h = (msrval.h & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE);
wrmsrq(MSR_IA32_PERF_CTL, msrval.q);
}
@@ -265,7 +265,7 @@ static u32 cpu_freq_read_amd(struct acpi_pct_register *not_used)
{
u64 val;
- rdmsrq(MSR_AMD_PERF_CTL, val);
+ val = rdmsrq(MSR_AMD_PERF_CTL);
return (u32)val;
}
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index a74a4cf99d22..acccceb5abf5 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -607,8 +607,8 @@ static inline bool amd_pstate_sample(struct amd_cpudata *cpudata)
unsigned long flags;
local_irq_save(flags);
- rdmsrq(MSR_IA32_APERF, aperf);
- rdmsrq(MSR_IA32_MPERF, mperf);
+ aperf = rdmsrq(MSR_IA32_APERF);
+ mperf = rdmsrq(MSR_IA32_MPERF);
tsc = rdtsc();
if (cpudata->prev.mperf == mperf || cpudata->prev.tsc == tsc) {
diff --git a/drivers/cpufreq/e_powersaver.c b/drivers/cpufreq/e_powersaver.c
index 13709f9667ea..5cd68b51bc7a 100644
--- a/drivers/cpufreq/e_powersaver.c
+++ b/drivers/cpufreq/e_powersaver.c
@@ -99,7 +99,7 @@ static unsigned int eps_get(unsigned int cpu)
return 0;
/* Return current frequency */
- rdmsrq(MSR_IA32_PERF_STATUS, val);
+ val = rdmsrq(MSR_IA32_PERF_STATUS);
return centaur->fsb * ((val >> 8) & 0xff);
}
@@ -111,11 +111,11 @@ static int eps_set_state(struct eps_cpu_data *centaur,
int i;
/* Wait while CPU is busy */
- rdmsrq(MSR_IA32_PERF_STATUS, val);
+ val = rdmsrq(MSR_IA32_PERF_STATUS);
i = 0;
while (val & ((1 << 16) | (1 << 17))) {
udelay(16);
- rdmsrq(MSR_IA32_PERF_STATUS, val);
+ val = rdmsrq(MSR_IA32_PERF_STATUS);
i++;
if (unlikely(i > 64)) {
return -ENODEV;
@@ -127,7 +127,7 @@ static int eps_set_state(struct eps_cpu_data *centaur,
i = 0;
do {
udelay(16);
- rdmsrq(MSR_IA32_PERF_STATUS, val);
+ val = rdmsrq(MSR_IA32_PERF_STATUS);
i++;
if (unlikely(i > 64)) {
return -ENODEV;
@@ -139,7 +139,7 @@ static int eps_set_state(struct eps_cpu_data *centaur,
u8 current_multiplier, current_voltage;
/* Print voltage and multiplier */
- rdmsrq(MSR_IA32_PERF_STATUS, val);
+ val = rdmsrq(MSR_IA32_PERF_STATUS);
current_voltage = val & 0xff;
pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700);
current_multiplier = (val >> 8) & 0xff;
@@ -195,12 +195,12 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
switch (c->x86_model) {
case 10:
- rdmsrq(0x1153, val);
+ val = rdmsrq(0x1153);
brand = (((val >> 2) ^ val) >> 18) & 3;
pr_cont("Model A ");
break;
case 13:
- rdmsrq(0x1154, val);
+ val = rdmsrq(0x1154);
brand = (((val >> 4) ^ (val >> 2))) & 0x000000ff;
pr_cont("Model D ");
break;
@@ -224,12 +224,12 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
return -ENODEV;
}
/* Enable Enhanced PowerSaver */
- rdmsrq(MSR_IA32_MISC_ENABLE, val);
+ val = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
val |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
wrmsrq(MSR_IA32_MISC_ENABLE, val);
/* Can be locked at 0 */
- rdmsrq(MSR_IA32_MISC_ENABLE, val);
+ val = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
pr_info("Can't enable Enhanced PowerSaver\n");
return -ENODEV;
@@ -237,7 +237,7 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
}
/* Print voltage and multiplier */
- rdmsrq(MSR_IA32_PERF_STATUS, status.q);
+ status.q = rdmsrq(MSR_IA32_PERF_STATUS);
current_voltage = status.l & 0xff;
pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700);
current_multiplier = (status.l >> 8) & 0xff;
diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 5a0eeb84d382..7328ba57df50 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -608,7 +608,7 @@ static bool turbo_is_disabled(void)
{
u64 misc_en;
- rdmsrq(MSR_IA32_MISC_ENABLE, misc_en);
+ misc_en = rdmsrq(MSR_IA32_MISC_ENABLE);
return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
}
@@ -1395,7 +1395,7 @@ static void set_power_ctl_ee_state(bool input)
guard(mutex)(&intel_pstate_driver_lock);
- rdmsrq(MSR_IA32_POWER_CTL, power_ctl);
+ power_ctl = rdmsrq(MSR_IA32_POWER_CTL);
if (input) {
power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
power_ctl_ee_state = POWER_CTL_EE_ENABLE;
@@ -1772,7 +1772,7 @@ static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribut
u64 power_ctl;
int enable;
- rdmsrq(MSR_IA32_POWER_CTL, power_ctl);
+ power_ctl = rdmsrq(MSR_IA32_POWER_CTL);
enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
return sprintf(buf, "%d\n", !enable);
}
@@ -2066,7 +2066,7 @@ static int atom_get_min_pstate(int not_used)
{
u64 value;
- rdmsrq(MSR_ATOM_CORE_RATIOS, value);
+ value = rdmsrq(MSR_ATOM_CORE_RATIOS);
return (value >> 8) & 0x7F;
}
@@ -2074,7 +2074,7 @@ static int atom_get_max_pstate(int not_used)
{
u64 value;
- rdmsrq(MSR_ATOM_CORE_RATIOS, value);
+ value = rdmsrq(MSR_ATOM_CORE_RATIOS);
return (value >> 16) & 0x7F;
}
@@ -2082,7 +2082,7 @@ static int atom_get_turbo_pstate(int not_used)
{
u64 value;
- rdmsrq(MSR_ATOM_CORE_TURBO_RATIOS, value);
+ value = rdmsrq(MSR_ATOM_CORE_TURBO_RATIOS);
return value & 0x7F;
}
@@ -2113,7 +2113,7 @@ static int silvermont_get_scaling(void)
static int silvermont_freq_table[] = {
83300, 100000, 133300, 116700, 80000};
- rdmsrq(MSR_FSB_FREQ, value);
+ value = rdmsrq(MSR_FSB_FREQ);
i = value & 0x7;
WARN_ON(i > 4);
@@ -2129,7 +2129,7 @@ static int airmont_get_scaling(void)
83300, 100000, 133300, 116700, 80000,
93300, 90000, 88900, 87500};
- rdmsrq(MSR_FSB_FREQ, value);
+ value = rdmsrq(MSR_FSB_FREQ);
i = value & 0xF;
WARN_ON(i > 8);
@@ -2140,7 +2140,7 @@ static void atom_get_vid(struct cpudata *cpudata)
{
u64 value;
- rdmsrq(MSR_ATOM_CORE_VIDS, value);
+ value = rdmsrq(MSR_ATOM_CORE_VIDS);
cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
cpudata->vid.ratio = div_fp(
@@ -2148,7 +2148,7 @@ static void atom_get_vid(struct cpudata *cpudata)
int_tofp(cpudata->pstate.max_pstate -
cpudata->pstate.min_pstate));
- rdmsrq(MSR_ATOM_CORE_TURBO_VIDS, value);
+ value = rdmsrq(MSR_ATOM_CORE_TURBO_VIDS);
cpudata->vid.turbo = value & 0x7f;
}
@@ -2483,8 +2483,8 @@ static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
u64 tsc;
local_irq_save(flags);
- rdmsrq(MSR_IA32_APERF, aperf);
- rdmsrq(MSR_IA32_MPERF, mperf);
+ aperf = rdmsrq(MSR_IA32_APERF);
+ mperf = rdmsrq(MSR_IA32_MPERF);
tsc = rdtsc();
if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
local_irq_restore(flags);
@@ -3634,7 +3634,7 @@ static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
id = x86_match_cpu(intel_pstate_cpu_oob_ids);
if (id) {
- rdmsrq(MSR_MISC_PWR_MGMT, misc_pwr);
+ misc_pwr = rdmsrq(MSR_MISC_PWR_MGMT);
if (misc_pwr & BITMASK_OOB) {
pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
@@ -3690,7 +3690,7 @@ static bool intel_pstate_hwp_is_enabled(void)
{
u64 value;
- rdmsrq(MSR_PM_ENABLE, value);
+ value = rdmsrq(MSR_PM_ENABLE);
return !!(value & 0x1);
}
@@ -3755,7 +3755,7 @@ static bool hwp_check_dec(void)
{
u64 power_ctl;
- rdmsrq(MSR_IA32_POWER_CTL, power_ctl);
+ power_ctl = rdmsrq(MSR_IA32_POWER_CTL);
return !!(power_ctl & BIT(POWER_CTL_DEC_ENABLE));
}
diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c
index 4c2599264333..9bc0acc0ea69 100644
--- a/drivers/cpufreq/longhaul.c
+++ b/drivers/cpufreq/longhaul.c
@@ -121,7 +121,7 @@ static int longhaul_get_cpu_mult(void)
unsigned long invalue = 0;
u64 val;
- rdmsrq(MSR_IA32_EBL_CR_POWERON, val);
+ val = rdmsrq(MSR_IA32_EBL_CR_POWERON);
invalue = (val & (1<<22|1<<23|1<<24|1<<25))>>22;
if (longhaul_version == TYPE_LONGHAUL_V2 ||
longhaul_version == TYPE_POWERSAVER) {
@@ -137,7 +137,7 @@ static void do_longhaul1(unsigned int mults_index)
{
union msr_bcr2 bcr2;
- rdmsrq(MSR_VIA_BCR2, bcr2.val);
+ bcr2.val = rdmsrq(MSR_VIA_BCR2);
/* Enable software clock multiplier */
bcr2.bits.ESOFTBF = 1;
bcr2.bits.CLOCKMUL = mults_index & 0xff;
@@ -152,7 +152,7 @@ static void do_longhaul1(unsigned int mults_index)
/* Disable software clock multiplier */
local_irq_disable();
- rdmsrq(MSR_VIA_BCR2, bcr2.val);
+ bcr2.val = rdmsrq(MSR_VIA_BCR2);
bcr2.bits.ESOFTBF = 0;
wrmsrq(MSR_VIA_BCR2, bcr2.val);
}
@@ -165,7 +165,7 @@ static void do_powersaver(int cx_address, unsigned int mults_index,
union msr_longhaul longhaul;
u32 t;
- rdmsrq(MSR_VIA_LONGHAUL, longhaul.val);
+ longhaul.val = rdmsrq(MSR_VIA_LONGHAUL);
/* Setup new frequency */
if (!revid_errata)
longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
@@ -534,7 +534,7 @@ static void longhaul_setup_voltagescaling(void)
unsigned int j, speed, pos, kHz_step, numvscales;
int min_vid_speed;
- rdmsrq(MSR_VIA_LONGHAUL, longhaul.val);
+ longhaul.val = rdmsrq(MSR_VIA_LONGHAUL);
if (!(longhaul.bits.RevisionID & 1)) {
pr_info("Voltage scaling not supported by CPU\n");
return;
@@ -836,7 +836,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
}
/* Check Longhaul ver. 2 */
if (longhaul_version == TYPE_LONGHAUL_V2) {
- rdmsrq(MSR_VIA_LONGHAUL, val);
+ val = rdmsrq(MSR_VIA_LONGHAUL);
if (val == 0)
/* Looks like MSR isn't present */
longhaul_version = TYPE_LONGHAUL_V1;
diff --git a/drivers/cpufreq/longrun.c b/drivers/cpufreq/longrun.c
index 99abef32e7e5..f63cbb679575 100644
--- a/drivers/cpufreq/longrun.c
+++ b/drivers/cpufreq/longrun.c
@@ -37,14 +37,14 @@ static void longrun_get_policy(struct cpufreq_policy *policy)
{
struct msr msr;
- rdmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LONGRUN_FLAGS);
pr_debug("longrun flags are %x - %x\n", msr.l, msr.h);
if (msr.l & 0x01)
policy->policy = CPUFREQ_POLICY_PERFORMANCE;
else
policy->policy = CPUFREQ_POLICY_POWERSAVE;
- rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LONGRUN_CTRL);
pr_debug("longrun ctrl is %x - %x\n", msr.l, msr.h);
msr.l &= 0x0000007F;
msr.h &= 0x0000007F;
@@ -93,7 +93,7 @@ static int longrun_set_policy(struct cpufreq_policy *policy)
pctg_lo = pctg_hi;
/* performance or economy mode */
- rdmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LONGRUN_FLAGS);
msr.l &= 0xFFFFFFFE;
switch (policy->policy) {
case CPUFREQ_POLICY_PERFORMANCE:
@@ -105,7 +105,7 @@ static int longrun_set_policy(struct cpufreq_policy *policy)
wrmsrq(MSR_TMTA_LONGRUN_FLAGS, msr.q);
/* lower and upper boundary */
- rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LONGRUN_CTRL);
msr.l &= 0xFFFFFF80;
msr.h &= 0xFFFFFF80;
msr.l |= pctg_lo;
@@ -178,16 +178,16 @@ static int longrun_determine_freqs(unsigned int *low_freq,
* For maximum frequency, read out level zero.
*/
/* minimum */
- rdmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LRTI_READOUT);
msr.l = msr.h;
wrmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
- rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ);
*low_freq = msr.l * 1000; /* to kHz */
/* maximum */
msr.l = 0;
wrmsrq(MSR_TMTA_LRTI_READOUT, msr.q);
- rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LRTI_VOLT_MHZ);
*high_freq = msr.l * 1000; /* to kHz */
pr_debug("longrun table interface told %u - %u kHz\n",
@@ -204,7 +204,7 @@ static int longrun_determine_freqs(unsigned int *low_freq,
pr_debug("high frequency is %u kHz\n", *high_freq);
/* get current borders */
- rdmsrq(MSR_TMTA_LONGRUN_CTRL, msr.q);
+ msr.q = rdmsrq(MSR_TMTA_LONGRUN_CTRL);
save_lo = msr.l & 0x0000007F;
save_hi = msr.h & 0x0000007F;
diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c
index 6a930d7e6a5c..1df2a8f365a3 100644
--- a/drivers/cpufreq/powernow-k7.c
+++ b/drivers/cpufreq/powernow-k7.c
@@ -220,7 +220,7 @@ static void change_FID(int fid)
{
union msr_fidvidctl fidvidctl;
- rdmsrq(MSR_K7_FID_VID_CTL, fidvidctl.val);
+ fidvidctl.val = rdmsrq(MSR_K7_FID_VID_CTL);
if (fidvidctl.bits.FID != fid) {
fidvidctl.bits.SGTC = latency;
fidvidctl.bits.FID = fid;
@@ -235,7 +235,7 @@ static void change_VID(int vid)
{
union msr_fidvidctl fidvidctl;
- rdmsrq(MSR_K7_FID_VID_CTL, fidvidctl.val);
+ fidvidctl.val = rdmsrq(MSR_K7_FID_VID_CTL);
if (fidvidctl.bits.VID != vid) {
fidvidctl.bits.SGTC = latency;
fidvidctl.bits.VID = vid;
@@ -261,7 +261,7 @@ static int powernow_target(struct cpufreq_policy *policy, unsigned int index)
fid = powernow_table[index].driver_data & 0xFF;
vid = (powernow_table[index].driver_data & 0xFF00) >> 8;
- rdmsrq(MSR_K7_FID_VID_STATUS, fidvidstatus.val);
+ fidvidstatus.val = rdmsrq(MSR_K7_FID_VID_STATUS);
cfid = fidvidstatus.bits.CFID;
freqs.old = fsb * fid_codes[cfid] / 10;
@@ -558,7 +558,7 @@ static unsigned int powernow_get(unsigned int cpu)
if (cpu)
return 0;
- rdmsrq(MSR_K7_FID_VID_STATUS, fidvidstatus.val);
+ fidvidstatus.val = rdmsrq(MSR_K7_FID_VID_STATUS);
cfid = fidvidstatus.bits.CFID;
return fsb * fid_codes[cfid] / 10;
@@ -599,7 +599,7 @@ static int powernow_cpu_init(struct cpufreq_policy *policy)
if (policy->cpu != 0)
return -ENODEV;
- rdmsrq(MSR_K7_FID_VID_STATUS, fidvidstatus.val);
+ fidvidstatus.val = rdmsrq(MSR_K7_FID_VID_STATUS);
recalibrate_cpu_khz();
diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c
index fe1f499b4fc0..a5a986ce8f3e 100644
--- a/drivers/cpufreq/powernow-k8.c
+++ b/drivers/cpufreq/powernow-k8.c
@@ -89,7 +89,7 @@ static int pending_bit_stuck(void)
{
u64 msr;
- rdmsrq(MSR_FIDVID_STATUS, msr);
+ msr = rdmsrq(MSR_FIDVID_STATUS);
return msr & MSR_S_LO_CHANGE_PENDING ? 1 : 0;
}
@@ -107,7 +107,7 @@ static int query_current_values_with_pending_wait(struct powernow_k8_data *data)
pr_debug("detected change pending stuck\n");
return 1;
}
- rdmsrq(MSR_FIDVID_STATUS, msr.q);
+ msr.q = rdmsrq(MSR_FIDVID_STATUS);
} while (msr.l & MSR_S_LO_CHANGE_PENDING);
data->currvid = msr.h & MSR_S_HI_CURRENT_VID;
@@ -134,7 +134,7 @@ static void fidvid_msr_init(void)
struct msr msr;
u8 fid, vid;
- rdmsrq(MSR_FIDVID_STATUS, msr.q);
+ msr.q = rdmsrq(MSR_FIDVID_STATUS);
vid = msr.h & MSR_S_HI_CURRENT_VID;
fid = msr.l & MSR_S_LO_CURRENT_FID;
msr.l = fid | (vid << MSR_C_LO_VID_SHIFT);
@@ -293,7 +293,7 @@ static int core_voltage_pre_transition(struct powernow_k8_data *data,
if ((savefid < LO_FID_TABLE_TOP) && (reqfid < LO_FID_TABLE_TOP))
rvomult = 2;
rvosteps *= rvomult;
- rdmsrq(MSR_FIDVID_STATUS, msr.q);
+ msr.q = rdmsrq(MSR_FIDVID_STATUS);
maxvid = 0x1f & (msr.h >> 16);
pr_debug("ph1 maxvid=0x%x\n", maxvid);
if (reqvid < maxvid) /* lower numbers are higher voltages */
diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c
index de50fb367c6b..2e90b658bfc2 100644
--- a/drivers/cpufreq/speedstep-centrino.c
+++ b/drivers/cpufreq/speedstep-centrino.c
@@ -378,7 +378,7 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
/* Check to see if Enhanced SpeedStep is enabled, and try to
enable it if not. */
- rdmsrq(MSR_IA32_MISC_ENABLE, q);
+ q = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(q & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
q |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
@@ -386,7 +386,7 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
wrmsrq(MSR_IA32_MISC_ENABLE, q);
/* check to see if it stuck */
- rdmsrq(MSR_IA32_MISC_ENABLE, q);
+ q = rdmsrq(MSR_IA32_MISC_ENABLE);
if (!(q & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
pr_info("couldn't enable Enhanced SpeedStep\n");
return -ENODEV;
diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
index 2afc3f177a29..188d459c7e2a 100644
--- a/drivers/cpufreq/speedstep-lib.c
+++ b/drivers/cpufreq/speedstep-lib.c
@@ -74,7 +74,7 @@ static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
int i = 0, j = 0;
/* read MSR 0x2a - we only need the low 32 bits */
- rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
+ msr.q = rdmsrq(MSR_IA32_EBL_CR_POWERON);
pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr.l, msr.h);
msr_tmp = msr_lo = msr.l;
@@ -112,7 +112,7 @@ static unsigned int pentiumM_get_frequency(void)
struct msr msr;
u32 msr_tmp;
- rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
+ msr.q = rdmsrq(MSR_IA32_EBL_CR_POWERON);
pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr.l, msr.h);
/* see table B-2 of 24547212.pdf */
@@ -136,7 +136,7 @@ static unsigned int pentium_core_get_frequency(void)
u32 msr_tmp;
int ret;
- rdmsrq(MSR_FSB_FREQ, msr.q);
+ msr.q = rdmsrq(MSR_FSB_FREQ);
/* see table B-2 of 25366920.pdf */
switch (msr.l & 0x07) {
case 5:
@@ -161,7 +161,7 @@ static unsigned int pentium_core_get_frequency(void)
pr_err("PCORE - MSR_FSB_FREQ undefined value\n");
}
- rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
+ msr.q = rdmsrq(MSR_IA32_EBL_CR_POWERON);
pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
msr.l, msr.h);
@@ -191,7 +191,7 @@ static unsigned int pentium4_get_frequency(void)
if (c->x86_model < 2)
return cpu_khz;
- rdmsrq(0x2c, msr.q);
+ msr.q = rdmsrq(0x2c);
pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr.l, msr.h);
@@ -348,7 +348,7 @@ enum speedstep_processor speedstep_detect_processor(void)
/* all mobile PIII Coppermines have FSB 100 MHz
* ==> sort out a few desktop PIIIs. */
- rdmsrq(MSR_IA32_EBL_CR_POWERON, msr.q);
+ msr.q = rdmsrq(MSR_IA32_EBL_CR_POWERON);
pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
msr.l, msr.h);
msr.l &= 0x00c0000;
@@ -361,7 +361,7 @@ enum speedstep_processor speedstep_detect_processor(void)
* it has SpeedStep technology if either
* bit 56 or 57 is set
*/
- rdmsrq(MSR_IA32_PLATFORM_ID, msr.q);
+ msr.q = rdmsrq(MSR_IA32_PLATFORM_ID);
pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
msr.l, msr.h);
if ((msr.h & (1<<18)) &&
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c6aa69dbd9fb..ef2fc2be954a 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2956,13 +2956,13 @@ static void dct_read_mc_regs(struct amd64_pvt *pvt)
* Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
* those are Read-As-Zero.
*/
- rdmsrq(MSR_K8_TOP_MEM1, pvt->top_mem);
+ pvt->top_mem = rdmsrq(MSR_K8_TOP_MEM1);
edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);
/* Check first whether TOP_MEM2 is enabled: */
- rdmsrq(MSR_AMD64_SYSCFG, msr_val);
+ msr_val = rdmsrq(MSR_AMD64_SYSCFG);
if (msr_val & BIT(21)) {
- rdmsrq(MSR_K8_TOP_MEM2, pvt->top_mem2);
+ pvt->top_mem2 = rdmsrq(MSR_K8_TOP_MEM2);
edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
} else {
edac_dbg(0, " TOP_MEM2 disabled\n");
diff --git a/drivers/gpio/gpio-cs5535.c b/drivers/gpio/gpio-cs5535.c
index a97ec7561889..e9cc577e94b7 100644
--- a/drivers/gpio/gpio-cs5535.c
+++ b/drivers/gpio/gpio-cs5535.c
@@ -148,7 +148,7 @@ int cs5535_gpio_set_irq(unsigned group, unsigned irq)
if (group > 7 || irq > 15)
return -EINVAL;
- rdmsrq(MSR_PIC_ZSEL_HIGH, val.q);
+ val.q = rdmsrq(MSR_PIC_ZSEL_HIGH);
val.l &= ~(0xF << (group * 4));
val.l |= (irq & 0xF) << (group * 4);
diff --git a/drivers/hv/mshv_vtl_main.c b/drivers/hv/mshv_vtl_main.c
index 0d3d4161974f..e1e4bce49113 100644
--- a/drivers/hv/mshv_vtl_main.c
+++ b/drivers/hv/mshv_vtl_main.c
@@ -598,7 +598,7 @@ static int mshv_vtl_get_set_reg(struct hv_register_assoc *regs, bool set)
if (set)
wrmsrq(reg_table[i].msr_addr, *reg64);
else
- rdmsrq(reg_table[i].msr_addr, *reg64);
+ *reg64 = rdmsrq(reg_table[i].msr_addr);
}
return 0;
}
diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c
index dee42c163d92..cfb3a2975de4 100644
--- a/drivers/hwmon/hwmon-vid.c
+++ b/drivers/hwmon/hwmon-vid.c
@@ -243,10 +243,10 @@ static u8 get_via_model_d_vrm(void)
"C7-M", "C7", "Eden", "C7-D"
};
- rdmsrq(0x198, msr);
+ msr = rdmsrq(0x198);
vid = (msr >> 32) & 0xff;
- rdmsrq(0x1154, msr);
+ msr = rdmsrq(0x1154);
brand = ((msr >> 4) ^ (msr >> 2)) & 0x03;
if (vid > 0x3f) {
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index d74b478db280..94668cad683b 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -1999,35 +1999,35 @@ static void __init bxt_idle_state_table_update(void)
unsigned long long msr;
unsigned int usec;
- rdmsrq(MSR_PKGC6_IRTL, msr);
+ msr = rdmsrq(MSR_PKGC6_IRTL);
usec = irtl_2_usec(msr);
if (usec) {
bxt_cstates[2].exit_latency = usec;
bxt_cstates[2].target_residency = usec;
}
- rdmsrq(MSR_PKGC7_IRTL, msr);
+ msr = rdmsrq(MSR_PKGC7_IRTL);
usec = irtl_2_usec(msr);
if (usec) {
bxt_cstates[3].exit_latency = usec;
bxt_cstates[3].target_residency = usec;
}
- rdmsrq(MSR_PKGC8_IRTL, msr);
+ msr = rdmsrq(MSR_PKGC8_IRTL);
usec = irtl_2_usec(msr);
if (usec) {
bxt_cstates[4].exit_latency = usec;
bxt_cstates[4].target_residency = usec;
}
- rdmsrq(MSR_PKGC9_IRTL, msr);
+ msr = rdmsrq(MSR_PKGC9_IRTL);
usec = irtl_2_usec(msr);
if (usec) {
bxt_cstates[5].exit_latency = usec;
bxt_cstates[5].target_residency = usec;
}
- rdmsrq(MSR_PKGC10_IRTL, msr);
+ msr = rdmsrq(MSR_PKGC10_IRTL);
usec = irtl_2_usec(msr);
if (usec) {
bxt_cstates[6].exit_latency = usec;
@@ -2055,7 +2055,7 @@ static void __init sklh_idle_state_table_update(void)
if ((mwait_substates & (0xF << 28)) == 0)
return;
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr);
+ msr = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
/* PC10 is not enabled in PKG C-state limit */
if ((msr & 0xF) != 8)
@@ -2067,7 +2067,7 @@ static void __init sklh_idle_state_table_update(void)
/* if SGX is present */
if (ebx & (1 << 2)) {
- rdmsrq(MSR_IA32_FEAT_CTL, msr);
+ msr = rdmsrq(MSR_IA32_FEAT_CTL);
/* if SGX is enabled */
if (msr & (1 << 18))
@@ -2087,7 +2087,7 @@ static bool __init skx_is_pc6_disabled(void)
{
u64 msr;
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr);
+ msr = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
/*
* 000b: C0/C1 (no package C-state support)
@@ -2341,7 +2341,7 @@ static void auto_demotion_disable(void)
{
unsigned long long msr_bits;
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
+ msr_bits = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
msr_bits &= ~auto_demotion_disable_flags;
wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
}
@@ -2350,7 +2350,7 @@ static void c1e_promotion_enable(void)
{
unsigned long long msr_bits;
- rdmsrq(MSR_IA32_POWER_CTL, msr_bits);
+ msr_bits = rdmsrq(MSR_IA32_POWER_CTL);
msr_bits |= 0x2;
wrmsrq(MSR_IA32_POWER_CTL, msr_bits);
}
@@ -2359,7 +2359,7 @@ static void c1e_promotion_disable(void)
{
unsigned long long msr_bits;
- rdmsrq(MSR_IA32_POWER_CTL, msr_bits);
+ msr_bits = rdmsrq(MSR_IA32_POWER_CTL);
msr_bits &= ~0x2;
wrmsrq(MSR_IA32_POWER_CTL, msr_bits);
}
@@ -2428,7 +2428,7 @@ static void intel_c1_demotion_toggle(void *enable)
{
unsigned long long msr_val;
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val);
+ msr_val = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
/*
* Enable/disable C1 undemotion along with C1 demotion, as this is the
* most sensible configuration in general.
@@ -2468,7 +2468,7 @@ static ssize_t intel_c1_demotion_show(struct device *dev,
* Read the MSR value for a CPU and assume it is the same for all CPUs. Any other
* configuration would be a BIOS bug.
*/
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val);
+ msr_val = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
return sysfs_emit(buf, "%d\n", !!(msr_val & NHM_C1_AUTO_DEMOTE));
}
static DEVICE_ATTR_RW(intel_c1_demotion);
diff --git a/drivers/misc/cs5535-mfgpt.c b/drivers/misc/cs5535-mfgpt.c
index 9abfc44f70f4..9006b59858ff 100644
--- a/drivers/misc/cs5535-mfgpt.c
+++ b/drivers/misc/cs5535-mfgpt.c
@@ -83,7 +83,7 @@ int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
return -EIO;
}
- rdmsrq(msr, val.q);
+ val.q = rdmsrq(msr);
if (enable)
val.l |= mask;
@@ -114,7 +114,7 @@ int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq,
* IRQ of the 1st. This can only happen if forcing an IRQ, calling this
* with *irq==0 is safe. Currently there _are_ no 2 drivers.
*/
- rdmsrq(MSR_PIC_ZSEL_LOW, zsel.q);
+ zsel.q = rdmsrq(MSR_PIC_ZSEL_LOW);
shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer->nr % 4) * 4;
if (((zsel.l >> shift) & 0xF) == 2)
return -EIO;
@@ -128,7 +128,7 @@ int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq,
/* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */
if (*irq < 1 || *irq == 2 || *irq > 15)
return -EIO;
- rdmsrq(MSR_PIC_IRQM_LPC, lpc.q);
+ lpc.q = rdmsrq(MSR_PIC_IRQM_LPC);
if (lpc.l & (1 << *irq))
return -EIO;
diff --git a/drivers/mtd/nand/raw/cs553x_nand.c b/drivers/mtd/nand/raw/cs553x_nand.c
index 0b872b1e3b04..2ed13666b48f 100644
--- a/drivers/mtd/nand/raw/cs553x_nand.c
+++ b/drivers/mtd/nand/raw/cs553x_nand.c
@@ -351,20 +351,20 @@ static int __init cs553x_init(void)
return -ENXIO;
/* If it doesn't have the CS553[56], abort */
- rdmsrq(MSR_DIVIL_GLD_CAP, val);
+ val = rdmsrq(MSR_DIVIL_GLD_CAP);
val &= ~0xFFULL;
if (val != CAP_CS5535 && val != CAP_CS5536)
return -ENXIO;
/* If it doesn't have the NAND controller enabled, abort */
- rdmsrq(MSR_DIVIL_BALL_OPTS, val);
+ val = rdmsrq(MSR_DIVIL_BALL_OPTS);
if (val & PIN_OPT_IDE) {
pr_info("CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
return -ENXIO;
}
for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
- rdmsrq(MSR_DIVIL_LBAR_FLSH0 + i, val);
+ val = rdmsrq(MSR_DIVIL_LBAR_FLSH0 + i);
if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
diff --git a/drivers/platform/x86/intel/ifs/load.c b/drivers/platform/x86/intel/ifs/load.c
index 50f1fdf7dfed..6320a0e45d38 100644
--- a/drivers/platform/x86/intel/ifs/load.c
+++ b/drivers/platform/x86/intel/ifs/load.c
@@ -129,7 +129,7 @@ static void copy_hashes_authenticate_chunks(struct work_struct *work)
msrs = ifs_get_test_msrs(dev);
/* run scan hash copy */
wrmsrq(msrs->copy_hashes, ifs_hash_ptr);
- rdmsrq(msrs->copy_hashes_status, hashes_status.data);
+ hashes_status.data = rdmsrq(msrs->copy_hashes_status);
/* enumerate the scan image information */
num_chunks = hashes_status.num_chunks;
@@ -151,7 +151,7 @@ static void copy_hashes_authenticate_chunks(struct work_struct *work)
linear_addr |= i;
wrmsrq(msrs->copy_chunks, linear_addr);
- rdmsrq(msrs->copy_chunks_status, chunk_status.data);
+ chunk_status.data = rdmsrq(msrs->copy_chunks_status);
ifsd->valid_chunks = chunk_status.valid_chunks;
err_code = chunk_status.error_code;
@@ -197,7 +197,7 @@ static int copy_hashes_authenticate_chunks_gen2(struct device *dev)
if (need_copy_scan_hashes(ifsd)) {
wrmsrq(msrs->copy_hashes, ifs_hash_ptr);
- rdmsrq(msrs->copy_hashes_status, hashes_status.data);
+ hashes_status.data = rdmsrq(msrs->copy_hashes_status);
/* enumerate the scan image information */
chunk_size = hashes_status.chunk_size * SZ_1K;
@@ -218,7 +218,7 @@ static int copy_hashes_authenticate_chunks_gen2(struct device *dev)
if (ifsd->generation >= IFS_GEN_STRIDE_AWARE) {
wrmsrq(msrs->test_ctrl, INVALIDATE_STRIDE);
- rdmsrq(msrs->copy_chunks_status, chunk_status.data);
+ chunk_status.data = rdmsrq(msrs->copy_chunks_status);
if (chunk_status.valid_chunks != 0) {
dev_err(dev, "Couldn't invalidate installed stride - %d\n",
chunk_status.valid_chunks);
@@ -241,7 +241,7 @@ static int copy_hashes_authenticate_chunks_gen2(struct device *dev)
local_irq_disable();
wrmsrq(msrs->copy_chunks, (u64)chunk_table);
local_irq_enable();
- rdmsrq(msrs->copy_chunks_status, chunk_status.data);
+ chunk_status.data = rdmsrq(msrs->copy_chunks_status);
err_code = chunk_status.error_code;
} while (err_code == AUTH_INTERRUPTED_ERROR && --retry_count);
diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c
index dfc119d7354d..46e1ea944ce7 100644
--- a/drivers/platform/x86/intel/ifs/runtest.c
+++ b/drivers/platform/x86/intel/ifs/runtest.c
@@ -211,7 +211,7 @@ static int doscan(void *data)
* are processed in a single pass) before it retires.
*/
wrmsrq(MSR_ACTIVATE_SCAN, params->activate->data);
- rdmsrq(MSR_SCAN_STATUS, status.data);
+ status.data = rdmsrq(MSR_SCAN_STATUS);
trace_ifs_status(ifsd->cur_batch, start, stop, status.data);
@@ -324,7 +324,7 @@ static int do_array_test(void *data)
if (cpu == first) {
wrmsrq(MSR_ARRAY_BIST, command->data);
/* Pass back the result of the test */
- rdmsrq(MSR_ARRAY_BIST, command->data);
+ command->data = rdmsrq(MSR_ARRAY_BIST);
}
return 0;
@@ -376,7 +376,7 @@ static int do_array_test_gen1(void *status)
if (cpu == first) {
wrmsrq(MSR_ARRAY_TRIGGER, ARRAY_GEN1_TEST_ALL_ARRAYS);
- rdmsrq(MSR_ARRAY_STATUS, *((u64 *)status));
+ *((u64 *)status) = rdmsrq(MSR_ARRAY_STATUS);
}
return 0;
@@ -528,7 +528,7 @@ static int dosbaf(void *data)
* during the "execution" of the WRMSR.
*/
wrmsrq(MSR_ACTIVATE_SBAF, run_params->activate->data);
- rdmsrq(MSR_SBAF_STATUS, status.data);
+ status.data = rdmsrq(MSR_SBAF_STATUS);
trace_ifs_sbaf(ifsd->cur_batch, *run_params->activate, status);
/* Pass back the result of the test */
diff --git a/drivers/platform/x86/intel/pmc/cnp.c b/drivers/platform/x86/intel/pmc/cnp.c
index efea4e1ba52b..44979e680361 100644
--- a/drivers/platform/x86/intel/pmc/cnp.c
+++ b/drivers/platform/x86/intel/pmc/cnp.c
@@ -228,7 +228,7 @@ static void disable_c1_auto_demote(void *unused)
int cpunum = smp_processor_id();
u64 val;
- rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, val);
+ val = rdmsrq(MSR_PKG_CST_CONFIG_CONTROL);
per_cpu(pkg_cst_config, cpunum) = val;
val &= ~NHM_C1_AUTO_DEMOTE;
wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, val);
diff --git a/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c b/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c
index 22745b217c6f..909c9e25112d 100644
--- a/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c
+++ b/drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c
@@ -40,7 +40,7 @@ static int isst_if_send_mbox_cmd(u8 command, u8 sub_command, u32 parameter,
/* Poll for rb bit == 0 */
retries = OS_MAILBOX_RETRY_COUNT;
do {
- rdmsrq(MSR_OS_MAILBOX_INTERFACE, data);
+ data = rdmsrq(MSR_OS_MAILBOX_INTERFACE);
if (data & BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT)) {
ret = -EBUSY;
continue;
@@ -65,7 +65,7 @@ static int isst_if_send_mbox_cmd(u8 command, u8 sub_command, u32 parameter,
/* Poll for rb bit == 0 */
retries = OS_MAILBOX_RETRY_COUNT;
do {
- rdmsrq(MSR_OS_MAILBOX_INTERFACE, data);
+ data = rdmsrq(MSR_OS_MAILBOX_INTERFACE);
if (data & BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT)) {
ret = -EBUSY;
continue;
@@ -75,7 +75,7 @@ static int isst_if_send_mbox_cmd(u8 command, u8 sub_command, u32 parameter,
return -ENXIO;
if (response_data) {
- rdmsrq(MSR_OS_MAILBOX_DATA, data);
+ data = rdmsrq(MSR_OS_MAILBOX_DATA);
*response_data = data;
}
ret = 0;
diff --git a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
index 24334ae70d82..6f8648cc0445 100644
--- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
+++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
@@ -561,7 +561,7 @@ static bool disable_dynamic_sst_features(void)
if (!static_cpu_has(X86_FEATURE_HWP))
return true;
- rdmsrq(MSR_PM_ENABLE, value);
+ value = rdmsrq(MSR_PM_ENABLE);
return !(value & 0x1);
}
diff --git a/drivers/platform/x86/intel_ips.c b/drivers/platform/x86/intel_ips.c
index b1b2d9caba7b..79c07f23ba0b 100644
--- a/drivers/platform/x86/intel_ips.c
+++ b/drivers/platform/x86/intel_ips.c
@@ -370,7 +370,7 @@ static void ips_cpu_raise(struct ips_driver *ips)
if (!ips->cpu_turbo_enabled)
return;
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);
+ turbo_override = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
cur_tdp_limit = turbo_override & TURBO_TDP_MASK;
new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */
@@ -405,7 +405,7 @@ static void ips_cpu_lower(struct ips_driver *ips)
u64 turbo_override;
u16 cur_limit, new_limit;
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);
+ turbo_override = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
cur_limit = turbo_override & TURBO_TDP_MASK;
new_limit = cur_limit - 8; /* 1W decrease */
@@ -437,7 +437,7 @@ static void do_enable_cpu_turbo(void *data)
{
u64 perf_ctl;
- rdmsrq(IA32_PERF_CTL, perf_ctl);
+ perf_ctl = rdmsrq(IA32_PERF_CTL);
if (perf_ctl & IA32_PERF_TURBO_DIS) {
perf_ctl &= ~IA32_PERF_TURBO_DIS;
wrmsrq(IA32_PERF_CTL, perf_ctl);
@@ -475,7 +475,7 @@ static void do_disable_cpu_turbo(void *data)
{
u64 perf_ctl;
- rdmsrq(IA32_PERF_CTL, perf_ctl);
+ perf_ctl = rdmsrq(IA32_PERF_CTL);
if (!(perf_ctl & IA32_PERF_TURBO_DIS)) {
perf_ctl |= IA32_PERF_TURBO_DIS;
wrmsrq(IA32_PERF_CTL, perf_ctl);
@@ -1215,7 +1215,7 @@ static int cpu_clamp_show(struct seq_file *m, void *data)
u64 turbo_override;
int tdp, tdc;
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);
+ turbo_override = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
tdp = (int)(turbo_override & TURBO_TDP_MASK);
tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT);
@@ -1290,7 +1290,7 @@ static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips)
return NULL;
}
- rdmsrq(IA32_MISC_ENABLE, misc_en);
+ misc_en = rdmsrq(IA32_MISC_ENABLE);
/*
* If the turbo enable bit isn't set, we shouldn't try to enable/disable
* turbo manually or we'll get an illegal MSR access, even though
@@ -1312,7 +1312,7 @@ static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips)
return NULL;
}
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_power);
+ turbo_power = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
tdp = turbo_power & TURBO_TDP_MASK;
/* Sanity check TDP against CPU */
@@ -1496,7 +1496,7 @@ static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id)
* Check PLATFORM_INFO MSR to make sure this chip is
* turbo capable.
*/
- rdmsrq(PLATFORM_INFO, platform_info);
+ platform_info = rdmsrq(PLATFORM_INFO);
if (!(platform_info & PLATFORM_TDP)) {
dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n");
return -ENODEV;
@@ -1529,7 +1529,7 @@ static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id)
ips->mgta_val = thm_readw(THM_MGTA);
/* Save turbo limits & ratios */
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
+ ips->orig_turbo_limit = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
ips_disable_cpu_turbo(ips);
ips->cpu_turbo_enabled = false;
@@ -1596,7 +1596,7 @@ static void ips_remove(struct pci_dev *dev)
if (ips->gpu_turbo_disable)
symbol_put(i915_gpu_turbo_disable);
- rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);
+ turbo_override = rdmsrq(TURBO_POWER_CURRENT_LIMIT);
turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN);
wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override);
wrmsrq(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rapl_msr.c
index a34543e66446..5d840de67c2b 100644
--- a/drivers/powercap/intel_rapl_msr.c
+++ b/drivers/powercap/intel_rapl_msr.c
@@ -176,7 +176,7 @@ static int rapl_msr_read_raw(int cpu, struct reg_action *ra, bool pmu_ctx)
* from any CPU in the package.
*/
if (pmu_ctx) {
- rdmsrq(ra->reg.msr, ra->value);
+ ra->value = rdmsrq(ra->reg.msr);
goto out;
}
diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c
index 3273b8fe3d4d..6b2801aaa745 100644
--- a/drivers/thermal/intel/intel_hfi.c
+++ b/drivers/thermal/intel/intel_hfi.c
@@ -285,7 +285,7 @@ void intel_hfi_process_event(__u64 pkg_therm_status_msr_val)
if (!raw_spin_trylock(&hfi_instance->event_lock))
return;
- rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS, msr);
+ msr = rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS);
hfi = msr & PACKAGE_THERM_STATUS_HFI_UPDATED;
if (!hfi) {
raw_spin_unlock(&hfi_instance->event_lock);
@@ -357,7 +357,7 @@ static void hfi_enable(void)
{
u64 msr_val;
- rdmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val);
+ msr_val = rdmsrq(MSR_IA32_HW_FEEDBACK_CONFIG);
msr_val |= HW_FEEDBACK_CONFIG_HFI_ENABLE_BIT;
wrmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val);
}
@@ -378,7 +378,7 @@ static void hfi_disable(void)
u64 msr_val;
int i;
- rdmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val);
+ msr_val = rdmsrq(MSR_IA32_HW_FEEDBACK_CONFIG);
msr_val &= ~HW_FEEDBACK_CONFIG_HFI_ENABLE_BIT;
wrmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val);
@@ -389,7 +389,7 @@ static void hfi_disable(void)
* memory.
*/
for (i = 0; i < 2000; i++) {
- rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
+ msr_val = rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS);
if (msr_val & PACKAGE_THERM_STATUS_HFI_UPDATED)
break;
diff --git a/drivers/thermal/intel/therm_throt.c b/drivers/thermal/intel/therm_throt.c
index 0b46a727ca7a..d12f124ef8d9 100644
--- a/drivers/thermal/intel/therm_throt.c
+++ b/drivers/thermal/intel/therm_throt.c
@@ -288,7 +288,7 @@ static void get_therm_status(int level, bool *proc_hot, u8 *temp)
else
msr = MSR_IA32_PACKAGE_THERM_STATUS;
- rdmsrq(msr, msr_val);
+ msr_val = rdmsrq(msr);
if (msr_val & THERM_STATUS_PROCHOT_LOG)
*proc_hot = true;
else
@@ -660,7 +660,7 @@ void intel_thermal_interrupt(void)
if (static_cpu_has(X86_FEATURE_HWP))
notify_hwp_interrupt();
- rdmsrq(MSR_IA32_THERM_STATUS, msr_val);
+ msr_val = rdmsrq(MSR_IA32_THERM_STATUS);
/* Check for violation of core thermal thresholds*/
notify_thresholds(msr_val);
@@ -675,7 +675,7 @@ void intel_thermal_interrupt(void)
CORE_LEVEL);
if (this_cpu_has(X86_FEATURE_PTS)) {
- rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
+ msr_val = rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS);
/* check violations of package thermal thresholds */
notify_package_thresholds(msr_val);
therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
@@ -733,7 +733,7 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
* be some SMM goo which handles it, so we can't even put a handler
* since it might be delivered via SMI already:
*/
- rdmsrq(MSR_IA32_MISC_ENABLE, val.q);
+ val.q = rdmsrq(MSR_IA32_MISC_ENABLE);
val.h = lvtthmr_init;
/*
@@ -759,7 +759,7 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
/* early Pentium M models use different method for enabling TM2 */
if (cpu_has(c, X86_FEATURE_TM2)) {
if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
- rdmsrq(MSR_THERM2_CTL, val.q);
+ val.q = rdmsrq(MSR_THERM2_CTL);
if (val.l & MSR_THERM2_CTL_TM_SELECT)
tm2 = 1;
} else if (val.l & MSR_IA32_MISC_ENABLE_TM2)
@@ -773,7 +773,7 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
thermal_intr_init_core_clear_mask();
thermal_intr_init_pkg_clear_mask();
- rdmsrq(MSR_IA32_THERM_INTERRUPT, val.q);
+ val.q = rdmsrq(MSR_IA32_THERM_INTERRUPT);
if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
val.l = (val.l | THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE) &
~THERM_INT_PLN_ENABLE;
@@ -785,7 +785,7 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
wrmsrq(MSR_IA32_THERM_INTERRUPT, val.q);
if (cpu_has(c, X86_FEATURE_PTS)) {
- rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
+ val.q = rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT);
if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
val.l = (val.l | PACKAGE_THERM_INT_LOW_ENABLE |
PACKAGE_THERM_INT_HIGH_ENABLE) &
@@ -800,13 +800,13 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
if (cpu_has(c, X86_FEATURE_HFI)) {
- rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
+ val.q = rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT);
wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT,
val.q | PACKAGE_THERM_INT_HFI_ENABLE);
}
}
- rdmsrq(MSR_IA32_MISC_ENABLE, val.q);
+ val.q = rdmsrq(MSR_IA32_MISC_ENABLE);
wrmsrq(MSR_IA32_MISC_ENABLE, val.q | MSR_IA32_MISC_ENABLE_TM1);
pr_info_once("CPU0: Thermal monitoring enabled (%s)\n",
diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c
index 43fd5bdf1d8d..11ca647802dc 100644
--- a/drivers/thermal/intel/x86_pkg_temp_thermal.c
+++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c
@@ -187,7 +187,7 @@ static inline void enable_pkg_thres_interrupt(void)
u8 thres_0, thres_1;
struct msr val;
- rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
+ val.q = rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT);
/* only enable/disable if it had valid threshold value */
thres_0 = (val.l & THERM_MASK_THRESHOLD0) >> THERM_SHIFT_THRESHOLD0;
thres_1 = (val.l & THERM_MASK_THRESHOLD1) >> THERM_SHIFT_THRESHOLD1;
@@ -203,7 +203,7 @@ static inline void disable_pkg_thres_interrupt(void)
{
struct msr val;
- rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
+ val.q = rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT);
val.l &= ~(THERM_INT_THRESHOLD0_ENABLE | THERM_INT_THRESHOLD1_ENABLE);
wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q);
@@ -356,7 +356,7 @@ static int pkg_temp_thermal_device_add(unsigned int cpu)
goto out_unregister_tz;
/* Store MSR value for package thermal interrupt, to restore at exit */
- rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, zonedev->msr_pkg_therm);
+ zonedev->msr_pkg_therm = rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT);
cpumask_set_cpu(cpu, &zonedev->cpumask);
raw_spin_lock_irq(&pkg_temp_lock);
diff --git a/drivers/video/fbdev/geode/display_gx.c b/drivers/video/fbdev/geode/display_gx.c
index b93aa21a1d2b..511cb7bf98e9 100644
--- a/drivers/video/fbdev/geode/display_gx.c
+++ b/drivers/video/fbdev/geode/display_gx.c
@@ -26,7 +26,7 @@ unsigned int gx_frame_buffer_size(void)
struct msr msr;
/* The number of pages is (PMAX - PMIN)+1 */
- rdmsrq(MSR_GLIU_P2D_RO0, msr.q);
+ msr.q = rdmsrq(MSR_GLIU_P2D_RO0);
/* PMAX */
val = ((msr.h & 0xff) << 12) | ((msr.l & 0xfff00000) >> 20);
diff --git a/drivers/video/fbdev/geode/gxfb_core.c b/drivers/video/fbdev/geode/gxfb_core.c
index 8d69be7c9d31..e0a3447f2b1b 100644
--- a/drivers/video/fbdev/geode/gxfb_core.c
+++ b/drivers/video/fbdev/geode/gxfb_core.c
@@ -378,7 +378,7 @@ static int gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
/* Figure out if this is a TFT or CRT part */
- rdmsrq(MSR_GX_GLD_MSR_CONFIG, val);
+ val = rdmsrq(MSR_GX_GLD_MSR_CONFIG);
if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP)
par->enable_crt = 0;
diff --git a/drivers/video/fbdev/geode/lxfb_ops.c b/drivers/video/fbdev/geode/lxfb_ops.c
index f5f1134cae9a..980a782214a2 100644
--- a/drivers/video/fbdev/geode/lxfb_ops.c
+++ b/drivers/video/fbdev/geode/lxfb_ops.c
@@ -127,7 +127,7 @@ static void lx_set_dotpll(u32 pllval)
struct msr dotpll;
int i;
- rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
+ dotpll.q = rdmsrq(MSR_GLCP_DOTPLL);
if ((dotpll.l & MSR_GLCP_DOTPLL_LOCK) && (dotpll.h == pllval))
return;
@@ -145,7 +145,7 @@ static void lx_set_dotpll(u32 pllval)
/* Now, loop for the lock bit */
for (i = 0; i < 1000; i++) {
- rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
+ dotpll.q = rdmsrq(MSR_GLCP_DOTPLL);
if (dotpll.l & MSR_GLCP_DOTPLL_LOCK)
break;
}
@@ -316,7 +316,7 @@ unsigned int lx_framebuffer_size(void)
struct msr msr;
/* The number of pages is (PMAX - PMIN)+1 */
- rdmsrq(MSR_GLIU_P2D_RO0, msr.q);
+ msr.q = rdmsrq(MSR_GLIU_P2D_RO0);
/* PMAX */
val = ((msr.h & 0xff) << 12) | ((msr.l & 0xfff00000) >> 20);
@@ -359,7 +359,7 @@ void lx_set_mode(struct fb_info *info)
/* Set output mode */
- rdmsrq(MSR_LX_GLD_MSR_CONFIG, msrval);
+ msrval = rdmsrq(MSR_LX_GLD_MSR_CONFIG);
msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT;
if (par->output & OUTPUT_PANEL) {
@@ -420,7 +420,7 @@ void lx_set_mode(struct fb_info *info)
/* Set default watermark values */
- rdmsrq(MSR_LX_SPARE_MSR, msrval);
+ msrval = rdmsrq(MSR_LX_SPARE_MSR);
msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO
| MSR_LX_SPARE_MSR_VFIFO_ARB_SEL
@@ -592,10 +592,10 @@ static void lx_save_regs(struct lxfb_par *par)
} while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE));
/* save MSRs */
- rdmsrq(MSR_LX_MSR_PADSEL, par->msr.padsel);
- rdmsrq(MSR_GLCP_DOTPLL, par->msr.dotpll);
- rdmsrq(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
- rdmsrq(MSR_LX_SPARE_MSR, par->msr.dcspare);
+ par->msr.padsel = rdmsrq(MSR_LX_MSR_PADSEL);
+ par->msr.dotpll = rdmsrq(MSR_GLCP_DOTPLL);
+ par->msr.dfglcfg = rdmsrq(MSR_LX_GLD_MSR_CONFIG);
+ par->msr.dcspare = rdmsrq(MSR_LX_SPARE_MSR);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
diff --git a/drivers/video/fbdev/geode/suspend_gx.c b/drivers/video/fbdev/geode/suspend_gx.c
index 6c0a526ee8a2..2fa20acba62e 100644
--- a/drivers/video/fbdev/geode/suspend_gx.c
+++ b/drivers/video/fbdev/geode/suspend_gx.c
@@ -21,8 +21,8 @@ static void gx_save_regs(struct gxfb_par *par)
} while (i & (GP_BLT_STATUS_BLT_PENDING | GP_BLT_STATUS_BLT_BUSY));
/* save MSRs */
- rdmsrq(MSR_GX_MSR_PADSEL, par->msr.padsel);
- rdmsrq(MSR_GLCP_DOTPLL, par->msr.dotpll);
+ par->msr.padsel = rdmsrq(MSR_GX_MSR_PADSEL);
+ par->msr.dotpll = rdmsrq(MSR_GLCP_DOTPLL);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
@@ -43,7 +43,7 @@ static void gx_set_dotpll(uint32_t dotpll_hi)
struct msr dotpll;
int i;
- rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
+ dotpll.q = rdmsrq(MSR_GLCP_DOTPLL);
dotpll.l |= MSR_GLCP_DOTPLL_DOTRESET;
dotpll.l &= ~MSR_GLCP_DOTPLL_BYPASS;
dotpll.h = dotpll_hi;
@@ -51,7 +51,7 @@ static void gx_set_dotpll(uint32_t dotpll_hi)
/* wait for the PLL to lock */
for (i = 0; i < 200; i++) {
- rdmsrq(MSR_GLCP_DOTPLL, dotpll.q);
+ dotpll.q = rdmsrq(MSR_GLCP_DOTPLL);
if (dotpll.l & MSR_GLCP_DOTPLL_LOCK)
break;
udelay(1);
diff --git a/drivers/video/fbdev/geode/video_gx.c b/drivers/video/fbdev/geode/video_gx.c
index 5717c3356949..b2cfadaf3ff8 100644
--- a/drivers/video/fbdev/geode/video_gx.c
+++ b/drivers/video/fbdev/geode/video_gx.c
@@ -142,8 +142,8 @@ void gx_set_dclk_frequency(struct fb_info *info)
}
}
- rdmsrq(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
- rdmsrq(MSR_GLCP_DOTPLL, dotpll);
+ sys_rstpll = rdmsrq(MSR_GLCP_SYS_RSTPLL);
+ dotpll = rdmsrq(MSR_GLCP_DOTPLL);
/* Program new M, N and P. */
dotpll &= 0x00000000ffffffffull;
@@ -167,7 +167,7 @@ void gx_set_dclk_frequency(struct fb_info *info)
/* Wait for LOCK bit. */
do {
- rdmsrq(MSR_GLCP_DOTPLL, dotpll);
+ dotpll = rdmsrq(MSR_GLCP_DOTPLL);
} while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
}
@@ -180,7 +180,7 @@ gx_configure_tft(struct fb_info *info)
/* Set up the DF pad select MSR */
- rdmsrq(MSR_GX_MSR_PADSEL, val);
+ val = rdmsrq(MSR_GX_MSR_PADSEL);
val &= ~MSR_GX_MSR_PADSEL_MASK;
val |= MSR_GX_MSR_PADSEL_TFT;
wrmsrq(MSR_GX_MSR_PADSEL, val);
diff --git a/include/linux/cs5535.h b/include/linux/cs5535.h
index 5ec2aca537bb..fef236cab7d8 100644
--- a/include/linux/cs5535.h
+++ b/include/linux/cs5535.h
@@ -51,7 +51,7 @@ static inline int cs5535_pic_unreqz_select_high(unsigned int group,
{
struct msr val;
- rdmsrq(MSR_PIC_ZSEL_HIGH, val.q);
+ val.q = rdmsrq(MSR_PIC_ZSEL_HIGH);
val.l &= ~(0xF << (group * 4));
val.l |= (irq & 0xF) << (group * 4);
wrmsrq(MSR_PIC_ZSEL_HIGH, val.q);
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v6 04/17] pinctrl: airoha: an7583: there is no mux to enable the second i2c bus
From: Krzysztof Kozlowski @ 2026-06-29 6:38 UTC (permalink / raw)
To: Mikhail Kshevetskiy
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
In-Reply-To: <20260628143733.273651-5-mikhail.kshevetskiy@iopsys.eu>
On Sun, Jun 28, 2026 at 05:37:20PM +0300, Mikhail Kshevetskiy wrote:
> In the AN7583 case there is no mux bit to enable the second i2c bus,
> so remove it.
But you do not remove second i2c bus, but the i2c bus.
> Also remove i2c pin function from device tree binding schema.
Why?
>
> Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
> .../bindings/pinctrl/airoha,an7583-pinctrl.yaml | 10 +---------
> drivers/pinctrl/airoha/pinctrl-airoha.c | 1 -
> 2 files changed, 1 insertion(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
> index f52802a3ad79..8d8ec6adb97d 100644
> --- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml
> @@ -60,7 +60,7 @@ patternProperties:
> function:
> description:
> A string containing the name of the function to mux to the group.
> - enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi,
> + enum: [pon, tod_1pps, sipo, mdio, uart, jtag, pcm, spi,
> pcm_spi, emmc, pnand, pcie_reset, pwm, phy1_led0,
> phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1,
> phy3_led1, phy4_led1]
> @@ -117,14 +117,6 @@ patternProperties:
> enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts,
> uart4, uart5]
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v6 04/17] pinctrl: airoha: an7583: there is no mux to enable the second i2c bus
From: Krzysztof Kozlowski @ 2026-06-29 6:40 UTC (permalink / raw)
To: Mikhail Kshevetskiy
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
In-Reply-To: <20260629-prehistoric-unstoppable-galago-c519da@quoll>
On 29/06/2026 08:38, Krzysztof Kozlowski wrote:
> On Sun, Jun 28, 2026 at 05:37:20PM +0300, Mikhail Kshevetskiy wrote:
>> In the AN7583 case there is no mux bit to enable the second i2c bus,
>> so remove it.
>
> But you do not remove second i2c bus, but the i2c bus.
>
>> Also remove i2c pin function from device tree binding schema.
>
> Why?
>
>>
>> Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
>> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
>> ---
>> .../bindings/pinctrl/airoha,an7583-pinctrl.yaml | 10 +---------
>> drivers/pinctrl/airoha/pinctrl-airoha.c | 1 -
Also:
Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v6 06/17] pinctrl: airoha: an7583: fix muxing of non-gpio default pins
From: Krzysztof Kozlowski @ 2026-06-29 6:41 UTC (permalink / raw)
To: Mikhail Kshevetskiy
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
In-Reply-To: <20260628143733.273651-7-mikhail.kshevetskiy@iopsys.eu>
On Sun, Jun 28, 2026 at 05:37:22PM +0300, Mikhail Kshevetskiy wrote:
> Current an7583 pinmux implementation have following issues:
> * pins 51 and 52 can't be set as pcie_reset, current pcie_reset code
> will sets pins to gpio mode instead.
> * there is no proper way to set pins 41--54 to gpio mode.
> * pins 41--53 can't be actually set as pwm pins. These pins must be
> muxed to gpio mode as well.
>
> This patch fixes above issues. Also device tree binding schema
> was updated.
Also was updated? "Also" is a sign you are mixing two commits into one.
Describe WHY you are doing things, not what you did. And describe in
details, becayse "binding was updated" brings no information.
>
> Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> ---
> .../pinctrl/airoha,an7583-pinctrl.yaml | 14 ++-
> drivers/pinctrl/airoha/pinctrl-airoha.c | 99 ++++++++++++++++---
Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v6 05/17] pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins
From: Krzysztof Kozlowski @ 2026-06-29 6:42 UTC (permalink / raw)
To: Mikhail Kshevetskiy
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi, Christian Marangi, AngeloGioacchino Del Regno,
Benjamin Larsson, linux-gpio, devicetree, linux-kernel,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
In-Reply-To: <20260628143733.273651-6-mikhail.kshevetskiy@iopsys.eu>
On Sun, Jun 28, 2026 at 05:37:21PM +0300, Mikhail Kshevetskiy wrote:
> In the an7581 case
> * gpio47 and pcie_reset0 shares pin 60,
> * gpio48 and pcie_reset1 shares pin 61,
> * gpio49 and pcie_reset2 shares pin 62.
> but current driver treat them as pins 61--63. This is wrong.
>
> Also current an7581 pinmux implementation have following issues:
> * current pcie_reset pin function actually sets corresponding
> pins as gpios.
> * there is no proper way to set pcie_reset pins as gpios.
> * there is no way to set pcie_reset pins as pwm.
>
> This patch fixes above issues. Also device tree binding schema
> was updated.
Same comment.
Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.
Best regards,
Krzysztof
^ permalink raw reply
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