* [PATCH v8 6/8] PCI: of: Use fw_devlink_set_device()
From: Herve Codina @ 2026-06-30 10:28 UTC (permalink / raw)
To: Andrew Lunn, Rob Herring, Saravana Kannan, Greg Kroah-Hartman,
Rafael J. Wysocki, Danilo Krummrich, Bjorn Helgaas, David Rhodes,
Richard Fitzgerald, Charles Keepax, Linus Walleij, Len Brown,
Andy Shevchenko, Daniel Scally, Heikki Krogerus, Sakari Ailus,
Davidlohr Bueso, Jonathan Cameron, Dave Jiang, Alison Schofield,
Vishal Verma, Dan Williams, Ira Weiny, Li Ming, Lizhi Hou,
Herve Codina
Cc: driver-core, linux-kernel, linux-pci, linux-sound, patches,
linux-gpio, linux-acpi, linux-cxl, Allan Nielsen, Horatiu Vultur,
Daniel Machon, Steen Hegelund, Luca Ceresoli, Thomas Petazzoni,
stable
In-Reply-To: <20260630102804.413563-1-herve.codina@bootlin.com>
The code set directly fwnode.dev field.
Use the dedicated fw_devlink_set_device() helper to perform this
operation.
Cc: stable@vger.kernel.org
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
---
Cc stable because used by other patches with Fixes + Cc stable
---
drivers/pci/of.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index 8b18c4ba845c..ee9eb384b377 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -803,7 +803,7 @@ void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge)
* bus. Avoid any new device creation.
*/
of_node_set_flag(np, OF_POPULATED);
- np->fwnode.dev = &bridge->dev;
+ fw_devlink_set_device(&np->fwnode, &bridge->dev);
fwnode_dev_initialized(&np->fwnode, true);
ret = of_changeset_apply(cset);
--
2.54.0
^ permalink raw reply related
* [PATCH v8 7/8] PCI: of: Set fwnode device of newly created PCI device nodes
From: Herve Codina @ 2026-06-30 10:28 UTC (permalink / raw)
To: Andrew Lunn, Rob Herring, Saravana Kannan, Greg Kroah-Hartman,
Rafael J. Wysocki, Danilo Krummrich, Bjorn Helgaas, David Rhodes,
Richard Fitzgerald, Charles Keepax, Linus Walleij, Len Brown,
Andy Shevchenko, Daniel Scally, Heikki Krogerus, Sakari Ailus,
Davidlohr Bueso, Jonathan Cameron, Dave Jiang, Alison Schofield,
Vishal Verma, Dan Williams, Ira Weiny, Li Ming, Lizhi Hou,
Herve Codina
Cc: driver-core, linux-kernel, linux-pci, linux-sound, patches,
linux-gpio, linux-acpi, linux-cxl, Allan Nielsen, Horatiu Vultur,
Daniel Machon, Steen Hegelund, Luca Ceresoli, Thomas Petazzoni,
stable
In-Reply-To: <20260630102804.413563-1-herve.codina@bootlin.com>
Device-tree node can be created when CONFIG_PCI_DYNAMIC_OF_NODES. Those
nodes are created and filled based on PCI core information but the
fwnode device field is not set.
When later an overlay is applied, this confuses fw_devlink. Indeed,
without any device attached to the node, fw_devlink considers that this
node will never become a device. When this node is pointed as a
supplier, devlink looks at its ancestors in order to find a node with a
device that could be used as the supplier.
In the PCI use case, this leads to links that wrongly use the PCI root
bridge device as the supplier instead of the expected PCI device.
Setting the fwnode device to the device of the PCI device allows devlink
to use this device as a supplier and so, correct links are created.
Fixes: 407d1a51921e ("PCI: Create device tree node for bridge")
Cc: stable@vger.kernel.org
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/of.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index ee9eb384b377..eda14cefca5e 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -709,6 +709,13 @@ void of_pci_make_dev_node(struct pci_dev *pdev)
if (ret)
goto out_free_node;
+ /*
+ * Set the fwnode device in order to have fw_devlink creating links
+ * pointing to this PCI device instead of walking up to the PCI host
+ * bridge.
+ */
+ fw_devlink_set_device(&np->fwnode, &pdev->dev);
+
ret = of_changeset_apply(cset);
if (ret)
goto out_free_node;
--
2.54.0
^ permalink raw reply related
* [PATCH v8 8/8] PCI: of: Remove fwnode_dev_initialized() call for a PCI root bridge node
From: Herve Codina @ 2026-06-30 10:28 UTC (permalink / raw)
To: Andrew Lunn, Rob Herring, Saravana Kannan, Greg Kroah-Hartman,
Rafael J. Wysocki, Danilo Krummrich, Bjorn Helgaas, David Rhodes,
Richard Fitzgerald, Charles Keepax, Linus Walleij, Len Brown,
Andy Shevchenko, Daniel Scally, Heikki Krogerus, Sakari Ailus,
Davidlohr Bueso, Jonathan Cameron, Dave Jiang, Alison Schofield,
Vishal Verma, Dan Williams, Ira Weiny, Li Ming, Lizhi Hou,
Herve Codina
Cc: driver-core, linux-kernel, linux-pci, linux-sound, patches,
linux-gpio, linux-acpi, linux-cxl, Allan Nielsen, Horatiu Vultur,
Daniel Machon, Steen Hegelund, Luca Ceresoli, Thomas Petazzoni,
stable
In-Reply-To: <20260630102804.413563-1-herve.codina@bootlin.com>
During the instantiation of devices described by a device-tree overlay
applied on a PCI device, devlink displays the following kind of debug
messages instead of creating the expected links:
'Not linking xxxx - might never become dev'
Without those expected links, the device removal order cannot be
correct.
Those debug traces are printed by fw_devlink_create_devlink(). In our
use case, they are all printed because the supplier of the link has at
least one of its ancestor with its fwnode flag FWNODE_FLAG_INITIALIZED
set.
The culprit ancestor is the PCI root bridge.
The fwnode related to the PCI root bridge is created dynamically by the
of_pci_make_host_bridge_node() function. During this creation
fwnode_dev_initialized() is called which set the FWNODE_FLAG_INITIALIZED
flag.
Calling fwnode_dev_initialized() tells devlink that the device related
to this node is handled out of the driver core. This is not correct in
our case. Indeed the device related to this firmware node is handled
using driver core mechanisms and is fully compliant devlink
expectations.
Simply remove the fwnode_dev_initialized() call. With that done, the
devlink debug messages are no more displayed and links that were missing
are correctly created.
Fixes: 1f340724419e ("PCI: of: Create device tree PCI host bridge node")
Cc: stable@vger.kernel.org
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/of.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index eda14cefca5e..3e12f70fe538 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -811,7 +811,6 @@ void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge)
*/
of_node_set_flag(np, OF_POPULATED);
fw_devlink_set_device(&np->fwnode, &bridge->dev);
- fwnode_dev_initialized(&np->fwnode, true);
ret = of_changeset_apply(cset);
if (ret)
--
2.54.0
^ permalink raw reply related
* Re: [PATCH 0/2] ASoC: rt5677: add GPIO get_direction and enable standalone compilation
From: Mark Brown @ 2026-06-29 18:41 UTC (permalink / raw)
To: Oder Chiou, Liam Girdwood, Jaroslav Kysela, Takashi Iwai,
Linus Walleij, Bartosz Golaszewski, Diogo Ivo
Cc: linux-sound, linux-kernel, linux-gpio
In-Reply-To: <20260620-smaug-audio-v1-0-e318acdf5abd@bootlin.com>
On Sat, 20 Jun 2026 15:50:57 +0200, Diogo Ivo wrote:
> ASoC: rt5677: add GPIO get_direction and enable standalone compilation
>
> This small series fixes two issues in the RT5677 ASoC codec driver:
>
> - Patch 1 adds the missing GPIO .get_direction() callback, allowing
> the direction of GPIO pins to be queried.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-7.3
Thanks!
[1/2] ASoC: rt5677: Add GPIO .get_direction() callback
https://git.kernel.org/broonie/sound/c/99e361b2a504
[2/2] ASoC: rt5677: Enable standalone compilation for generic card use
https://git.kernel.org/broonie/sound/c/a5edc45d9cf6
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* Re: [PATCH v8 6/6] pinctrl: mediatek: Add MT6735 pinctrl driver
From: Linus Walleij @ 2026-06-30 11:17 UTC (permalink / raw)
To: Yassine Oudjana
Cc: Yassine Oudjana, Sean Wang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Andy Teng, linux-mediatek, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <PjcK3j_TxnXwwBQ8ATPAPOO6LJl5b0Laa_6eSBTVfEfqsxIcaeDEVS4q4UkvGQA7CLQbuGxopLF6p3eIh1JAIDTkPFIgwp-hVP-fex_WEqU=@protonmail.com>
On Sat, Jun 13, 2026 at 11:20 AM Yassine Oudjana
<y.oudjana@protonmail.com> wrote:
> On Monday, June 8th, 2026 at 9:41 PM, Linus Walleij <linusw@kernel.org> wrote:
> > > From: Yassine Oudjana <y.oudjana@protonmail.com>
> > >
> > > Add a driver for the MediaTek MT6735 SoC pin controller. This driver
> > > also supports the pin controller on MT6735M, which lacks 6 physical
> > > pins (198-203) used for MSDC2 on MT6735.
> > >
> > > Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> >
> > Sashiko has good comments on this driver, look into them!
>
> Didn't receive any comments and I don't see anything on the mailing list
> archives either. Am I missing something?
https://lore.kernel.org/linux-devicetree/20260530155503.9A6C41F00893@smtp.kernel.org/
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] pinctrl: tb10x: Mark base as __iomem
From: Linus Walleij @ 2026-06-30 11:34 UTC (permalink / raw)
To: Krzysztof Kozlowski; +Cc: linux-gpio, kernel test robot, Linus Walleij
The compile tests are complaining that this is not correctly typed.
Fixes: 1982621decaf ("pinctrl: Allow compile testing for K210, TB10X and ZYNQ")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202606150641.cbQ05ZMM-lkp@intel.com/
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
drivers/pinctrl/pinctrl-tb10x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c
index 3f581404a9b9..b7cbd69dd877 100644
--- a/drivers/pinctrl/pinctrl-tb10x.c
+++ b/drivers/pinctrl/pinctrl-tb10x.c
@@ -479,7 +479,7 @@ struct tb10x_port {
*/
struct tb10x_pinctrl {
struct pinctrl_dev *pctl;
- void *base;
+ void __iomem *base;
const struct tb10x_pinfuncgrp *pingroups;
unsigned int pinfuncgrpcnt;
unsigned int pinfuncnt;
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260630-tb10x-0360d5489542
Best regards,
--
Linus Walleij <linusw@kernel.org>
^ permalink raw reply related
* Re: [PATCH v3 0/2] pinctrl: qcom: Introduce Pinctrl for the upcoming Maili SoC
From: Linus Walleij @ 2026-06-30 11:36 UTC (permalink / raw)
To: Jingyi Wang, Bartosz Golaszewski
Cc: Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang, linux-arm-msm,
linux-gpio, devicetree, linux-kernel, Krzysztof Kozlowski,
Dmitry Baryshkov, Konrad Dybcio
In-Reply-To: <20260622-maili-pinctrl-v3-0-9724e1000471@oss.qualcomm.com>
On Mon, Jun 22, 2026 at 9:35 AM Jingyi Wang
<jingyi.wang@oss.qualcomm.com> wrote:
> Introduce Top Level Mode Multiplexer dt-binding and driver for the
> upcoming Qualcomm Maili SoC. Maili is the new mobile SoC, and its DTS
> will be upstreamed later.
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> Changes in v3:
> - add reviewed-by tag
> - remove comments before msm_pingroup
> - Link to v2: https://lore.kernel.org/r/20260614-maili-pinctrl-v2-0-0db5bfc23d64@oss.qualcomm.com
FWIW looks good to me
Acked-by: Linus Walleij <linusw@kernel.org>
Bartosz is queueing Qualcomm patches now, he will decide on this patch.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3 0/8] x1e80100: Enable PDC wake GPIOs and deepest idle state
From: Linus Walleij @ 2026-06-30 11:42 UTC (permalink / raw)
To: Maulik Shah, Bartosz Golaszewski
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Gleixner, linux-arm-msm, linux-kernel,
devicetree, linux-gpio, Sneh Mankad, Stephan Gerhold
In-Reply-To: <20260616-hamoa_pdc_v3-v3-0-4d8e1504ea75@oss.qualcomm.com>
On Tue, Jun 16, 2026 at 10:26 AM Maulik Shah
<maulik.shah@oss.qualcomm.com> wrote:
> There are two modes PDC irqchip can work in
> - pass through mode
> - secondary controller mode
>
> Secondary mode is supported depending on SoC using PDC HW Version v3.0
> or higher.
>
> +------------------------------------------------------------------------+
> | SoC | SM8350, SM8450 | SM8550, Hamoa | SM8650, SM8750 |
> |----------------------------------------------------------- ------------|
> | Version | v2.7 | v3.0 | v3.2 |
> |------------------------------------------------------------------------|
> | Pass through | Yes | Yes | Yes |
> |------------------------------------------------------------------------|
> | Secondary | No | Yes | Yes |
> +------------------------------------------------------------------------+
I don't know what to do with this hurdle of pin control and irqchip patches,
luckily it will be Bartosz' problem since he's managing Qualcomm pin
controllers now :D
I'll be fine with brining the irqchip patches through pin control if an
irqchip maintainer ACKs them.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3] pinctrl: qcom: Unconditionally mark gpio as wakeup enable
From: Linus Walleij @ 2026-06-30 11:43 UTC (permalink / raw)
To: Sneh Mankad, Bartosz Golaszewski
Cc: Bjorn Andersson, Neil Armstrong, Krzysztof Kozlowski,
linux-arm-msm, linux-gpio, linux-kernel, stable, Maulik Shah
In-Reply-To: <20260616-enable_wakeup_capable_gpios-v3-1-fb59647d89cb@oss.qualcomm.com>
On Tue, Jun 16, 2026 at 12:55 PM Sneh Mankad
<sneh.mankad@oss.qualcomm.com> wrote:
> GPIO interrupts that are wakeup capable need to be forwarded to wakeup
> capable parent irqchip. This is done via writing to it's wakeup_enable bit.
LGTM and Konrad has ACKed it, Bartosz will queue this patch if he's
also happy with it.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v11 0/6] gpio: siul2-s32g2: add initial GPIO driver
From: Linus Walleij @ 2026-06-30 11:50 UTC (permalink / raw)
To: Khristine Andreea Barbulescu
Cc: Bartosz Golaszewski, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chester Lin, Matthias Brugger, Ghennadi Procopciuc,
Larisa Grigore, Lee Jones, Shawn Guo, Sascha Hauer, Fabio Estevam,
Dong Aisheng, Jacky Bai, Greg Kroah-Hartman, Rafael J. Wysocki,
Srinivas Kandagatla, Alberto Ruiz, Christophe Lizzi, devicetree,
Enric Balletbo, Eric Chanudet, imx, linux-arm-kernel, linux-gpio,
linux-kernel, NXP S32 Linux Team, Pengutronix Kernel Team,
Vincent Guittot
In-Reply-To: <20260610132116.1998140-1-khristineandreea.barbulescu@oss.nxp.com>
On Wed, Jun 10, 2026 at 2:21 PM Khristine Andreea Barbulescu
<khristineandreea.barbulescu@oss.nxp.com> wrote:
> This patch series adds support for basic GPIO
> operations using gpio-regmap.
Sorry for my confused comment on jun 10, these patches all go to the
pinctrl subsystem so I should merge them.
Can you make a v12 based on v7.2-rc1 and I will apply them.
Pick up ACKs!
I will not apply the device tree patch, this will need to be queued
in the SoC tree.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 0/2] pinctrl: aspeed: Make AST2700 SoC1 JTAG master TRST optional
From: Linus Walleij @ 2026-06-30 11:52 UTC (permalink / raw)
To: Billy Tsai
Cc: Andrew Jeffery, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, linux-aspeed, openbmc, linux-gpio, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260616-pinctrl-fix-v1-0-621036e45c7c@aspeedtech.com>
On Tue, Jun 16, 2026 at 4:30 AM Billy Tsai <billy_tsai@aspeedtech.com> wrote:
> The JTAGM1 pin group of the AST2700 SoC1 includes ball D12, which
> carries the TRST signal. TRST is an optional signal for a JTAG master:
> designs that do not wire it may need the D12 ball for other functions,
> but with TRST embedded in the group they cannot use the JTAG master at
> all.
>
> Split D12 into a new JTAGM1TRST group under the existing JTAGM1
> function, so TRST is only muxed when a board explicitly requests it.
> Patch 1 adds the new group to the device tree binding and patch 2
> splits the group in the driver.
>
> Note that this changes the meaning of the existing JTAGM1 group: boards
> that do use TRST now need to select both the JTAGM1 and JTAGM1TRST
> groups.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Patches applied!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH RFC] gpio: loongson-64bit: Add back the support for gsi_idx_map
From: Andy Shevchenko @ 2026-06-30 12:07 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: shankerwangmiao, Miao Wang via B4 Relay, Huacai Chen, Jianmin Lv,
WANG Xuerui, Jiaxun Yang, linux-gpio, Yinbo Zhu, Linus Walleij,
Hongchen Zhang, Liu Peibao, Juxin Gao, Mika Westerberg
In-Reply-To: <CAMRc=MdtRj6c3Bg72QMaAEMPovNyUdqWL_qDPGb1p=Cu=cETvA@mail.gmail.com>
On Tue, Jun 30, 2026 at 07:45:52AM +0000, Bartosz Golaszewski wrote:
> On Mon, 29 Jun 2026 23:05:28 +0200, Miao Wang via B4 Relay
> <devnull+shankerwangmiao.gmail.com@kernel.org> said:
> > This patch adds back the support for gsi_idx_map, which is used in the
> > ACPI DSDT table to describe the mapping between the GPIO line number to
> > the index of the interrupt number in the declared interrupt resources.
> >
> > This property was removed in Loongson CPU Universal Specification for
> > Interface Between PC/Server System Firmware and Kernel v4.1 in November,
> > 2023, but still in use in firmwares released this year. A sample of
> > an affected DSDT entry from a 3C6000 board I'm currently using is:
Oh my gosh, can somebody actually try to consult first with the Linux kernel
developers before adding non-standard and wrongly named properties, please?
> > Device (GPO1) {
> > Name (_HID, "LOON000F")
> > Name (_CRS, ResourceTemplate () {
> > QWordMemory ( // Omitted, not related
> > )
> > Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {
> > 0x00000010, 0x00000011, 0x00000012, 0x00000013,
> > 0x00000014, 0x00000015, 0x00000016, 0x00000017,
> > }
> > Name (_DSD, Package (0x02) {
> > ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
> > Package (0x03) {
> > Package (0x02) { "gpio_base", 0x50 } // Ignored by the driver
Yes, it's non-standard property. It's a broken one in terms of the style.
See DT binding documentation.
> > Package (0x02) { "ngpios", 0x20 }
> > Package (0x02) { "gsi_idx_map", Package (0x20) {
> > 0, 1, 2, 3, 4, 5, 6, 7,
> > 0, 1, 2, 3, 4, 5, 6, 7,
> > 0, 1, 2, 3, 4, 5, 6, 7,
> > 0, 1, 2, 3, 4, 5, 6, 7,
> > }}
> > }
> > }
> > }
> >
> > As can be seen in the DSDT entry, the mapping is essential for obtaining
> > the IRQ number from a GPIO line number. Otherwise, when IRQ is requested
> > for the line numbers largers than 7, it will fail with -ENXIO.
This doesn't look good. Why can't we simply hardcode the proper behaviour based
on the _HID? The gsi_idx_map seems quite regular and periodic, do you have some
other examples with different mapping?
> > The code in this patch is mostly picked from the version 5 of Yinbo's
> > original patch.
> Cc'ing ACPI GPIO maintainers.
Thanks, Bart!
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v4 00/14] pinctrl: airoha: split driver on shared code and SoC specific drivers, add supporf of en7523
From: Linus Walleij @ 2026-06-30 12:09 UTC (permalink / raw)
To: Mikhail Kshevetskiy
Cc: Lorenzo Bianconi, Christian Marangi, Benjamin Larsson,
AngeloGioacchino Del Regno, linux-kernel, linux-gpio,
linux-mediatek, Markus Gothe, Matheus Sampaio Queiroga
In-Reply-To: <20260617043654.2790253-1-mikhail.kshevetskiy@iopsys.eu>
On Wed, Jun 17, 2026 at 5:37 AM Mikhail Kshevetskiy
<mikhail.kshevetskiy@iopsys.eu> wrote:
> This patchset
> * fixes more airoha pinctrl issues
> * split combined driver on common code and several SoC specific drivers
> * improves an7583 pinctrl support
> * adds support of en7523 SoC
No comments for two weeks so patches applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] pinctrl: bcm2835: Don't remove an unregistered GPIO chip
From: Linus Walleij @ 2026-06-30 12:10 UTC (permalink / raw)
To: Daniel McCarthy
Cc: Florian Fainelli, Ray Jui, Scott Branden, linux-gpio,
linux-rpi-kernel, linux-arm-kernel, linux-kernel
In-Reply-To: <20260617220451.15298-1-daniel@dragonzap.com>
On Wed, Jun 17, 2026 at 11:05 PM Daniel McCarthy <daniel@dragonzap.com> wrote:
> If the devm_pinctrl_register() function fails,
> bcm2835_pinctrl_probe() calls gpiochip_remove()
> before gpiochip_add_data() has registered the GPIO chip.
>
> This means that upon failure the gpio_chip.gpiodev
> is NULL resulting in a null pointer dereference
> inside the gpiochip_remove() function.
>
> Remove the unnecessary function call to gpiochip_remove().
> No GPIO cleanup is required because the GPIO chip
> has not yet been registered. Without this change there
> is potential for a kernel panic upon registration failure
>
> Fixes: 266423e60ea1 ("pinctrl: bcm2835: Change init order for gpio hogs")
> Signed-off-by: Daniel McCarthy <daniel@dragonzap.com>
Patch applied as nonurgent fix.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2] serial: max310x: implement gpio_chip::get_direction()
From: Linus Walleij @ 2026-06-30 12:13 UTC (permalink / raw)
To: Tapio Reijonen
Cc: Greg Kroah-Hartman, Jiri Slaby, Bartosz Golaszewski,
Alexander Shiyan, linux-kernel, linux-serial, linux-gpio
In-Reply-To: <20260615-b4-serial-max310x-gpio-get-direction-v2-1-4704ba2b181a@vaisala.com>
On Mon, Jun 15, 2026 at 7:38 AM Tapio Reijonen
<tapio.reijonen@vaisala.com> wrote:
> It's strongly recommended for GPIO drivers to always implement the
> .get_direction() callback - even when the direction is tracked in
> software. The GPIO core emits a warning when the callback is missing
> and a user reads the direction of a line, e.g. via
> /sys/kernel/debug/gpio.
>
> The MAX310X keeps the GPIO direction in the GPIOCFG register (a set bit
> selects output), which the existing direction_input/output callbacks
> already program, so the current direction can be read back directly.
>
> Fixes: f65444187a66 ("serial: New serial driver MAX310X")
> Signed-off-by: Tapio Reijonen <tapio.reijonen@vaisala.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] pinctrl: tb10x: Mark base as __iomem
From: Krzysztof Kozlowski @ 2026-06-30 12:24 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, kernel test robot
In-Reply-To: <20260630-tb10x-v1-1-5d08d2dd3240@kernel.org>
On 30/06/2026 13:34, Linus Walleij wrote:
> The compile tests are complaining that this is not correctly typed.
>
> Fixes: 1982621decaf ("pinctrl: Allow compile testing for K210, TB10X and ZYNQ")
I do not think this is a correct fixes tag. The issue was introduced by
whichever commit made iomem memory a plain pointer.
Issue was reproducible earlier, just not on x86.
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202606150641.cbQ05ZMM-lkp@intel.com/
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
> drivers/pinctrl/pinctrl-tb10x.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c
> index 3f581404a9b9..b7cbd69dd877 100644
> --- a/drivers/pinctrl/pinctrl-tb10x.c
> +++ b/drivers/pinctrl/pinctrl-tb10x.c
> @@ -479,7 +479,7 @@ struct tb10x_port {
> */
> struct tb10x_pinctrl {
> struct pinctrl_dev *pctl;
> - void *base;
> + void __iomem *base;
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH RFC] gpio: loongson-64bit: Add back the support for gsi_idx_map
From: Miao Wang @ 2026-06-30 12:42 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Bartosz Golaszewski, Miao Wang via B4 Relay, Huacai Chen,
Jianmin Lv, WANG Xuerui, Jiaxun Yang, linux-gpio, Yinbo Zhu,
Linus Walleij, Hongchen Zhang, Liu Peibao, Juxin Gao,
Mika Westerberg
In-Reply-To: <akOxdBR_-rOweHXB@ashevche-desk.local>
> 2026年6月30日 20:07，Andy Shevchenko <andriy.shevchenko@linux.intel.com> 写道：
>
> On Tue, Jun 30, 2026 at 07:45:52AM +0000, Bartosz Golaszewski wrote:
>> On Mon, 29 Jun 2026 23:05:28 +0200, Miao Wang via B4 Relay
>> <devnull+shankerwangmiao.gmail.com@kernel.org> said:
>
>>> This patch adds back the support for gsi_idx_map, which is used in the
>>> ACPI DSDT table to describe the mapping between the GPIO line number to
>>> the index of the interrupt number in the declared interrupt resources.
>>>
>>> This property was removed in Loongson CPU Universal Specification for
>>> Interface Between PC/Server System Firmware and Kernel v4.1 in November,
>>> 2023, but still in use in firmwares released this year. A sample of
>>> an affected DSDT entry from a 3C6000 board I'm currently using is:
>
> Oh my gosh, can somebody actually try to consult first with the Linux kernel
> developers before adding non-standard and wrongly named properties, please?
Inferred from the time when gsi_idx_map was removed from the spec, I believe
that the removal might be because the maintainers suggestion against introducing
gsi_idx_map. However, the firmwares "in the wild" have not followed the change.
>>> Device (GPO1) {
>>> Name (_HID, "LOON000F")
>>> Name (_CRS, ResourceTemplate () {
>>> QWordMemory ( // Omitted, not related
>>> )
>>> Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {
>>> 0x00000010, 0x00000011, 0x00000012, 0x00000013,
>>> 0x00000014, 0x00000015, 0x00000016, 0x00000017,
>>> }
>>> Name (_DSD, Package (0x02) {
>>> ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
>>> Package (0x03) {
>>> Package (0x02) { "gpio_base", 0x50 } // Ignored by the driver
>
> Yes, it's non-standard property. It's a broken one in terms of the style.
> See DT binding documentation.
To clarify, I agree that this property should be redundant and ignored by
the driver and global gpio numbers should be assigned dynamically by the
kernel.
>>> Package (0x02) { "ngpios", 0x20 }
>>> Package (0x02) { "gsi_idx_map", Package (0x20) {
>>> 0, 1, 2, 3, 4, 5, 6, 7,
>>> 0, 1, 2, 3, 4, 5, 6, 7,
>>> 0, 1, 2, 3, 4, 5, 6, 7,
>>> 0, 1, 2, 3, 4, 5, 6, 7,
>>> }}
>>> }
>>> }
>>> }
>>>
>>> As can be seen in the DSDT entry, the mapping is essential for obtaining
>>> the IRQ number from a GPIO line number. Otherwise, when IRQ is requested
>>> for the line numbers largers than 7, it will fail with -ENXIO.
>
> This doesn't look good. Why can't we simply hardcode the proper behaviour based
> on the _HID? The gsi_idx_map seems quite regular and periodic, do you have some
> other examples with different mapping?
According to the manual, the gpio controllers in HID LOON0007 and LOON000F are
actually embedded into the CPU chip and the interrupt lines are hard wired so
that all the gpio lines of the gpio controller share in total 8 irqs such that
the i-th line is wired to the (i%8)-th irq. So the mapping for these two models
are fixed. I have no idea about the behavior of other kinds of controllers, which
should be answered by Loongson personales.
So far, there are known to be 2 styles of DSDT entries. One is defined by
the latest Firmware Spec, to list all the irq numbers in _CRS, e.g. Name (_CRS,
ResourceTemplate () { Interrupt () { 0x10, 0x11, .., 0x17, 0x10, 0x11, ..., 0x17,
... (in total ngpios entries) } }). The other is defined by the previous Firmware
spec, to use the property `gsi_idx_map` to map the gpio line number to the irq
number listed in the ResourceTemplate. The former should now be compatible with
the current implementation of the driver in the kernel, while the later not. I
believe that although being abandoned by the spec, the later should also be
considered and supported by the driver, since it is used by the firmwares in the
wild.
Looking forward to your advice on this.
>>> The code in this patch is mostly picked from the version 5 of Yinbo's
>>> original patch.
>
>> Cc'ing ACPI GPIO maintainers.
>
> Thanks, Bart!
>
> --
> With Best Regards,
> Andy Shevchenko
Cheers,
Miao Wang
^ permalink raw reply
* [PATCH v6 0/5] Add support for AAEON SRG-IMX8P MCU
From: Thomas Perrot (Schneider Electric) @ 2026-06-30 12:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
Jérémie Dautheribes, Wim Van Sebroeck, Guenter Roeck,
Lee Jones
Cc: devicetree, linux-kernel, linux-gpio, imx, linux-arm-kernel,
linux-watchdog, Thomas Petazzoni, Miquel Raynal,
Thomas Perrot (Schneider Electric), Krzysztof Kozlowski,
Conor Dooley, Bartosz Golaszewski
This patch series introduces support for the AAEON SRG-IMX8P embedded
controller (MCU). The MCU is connected via I2C and provides GPIO and
watchdog functionality for the SRG-IMX8P board.
The series includes:
- Device tree binding for the MFD driver
- MFD driver that serves as the core driver for the MCU
- GPIO driver implementing the GPIO functionality
- Watchdog driver for system monitoring
- MAINTAINERS entry for the new drivers
The drivers follow the standard Linux kernel subsystem patterns, with
the MFD driver registering the sub-devices (GPIO and watchdog) which
are then handled by their respective subsystem drivers.
Signed-off-by: Thomas Perrot (Schneider Electric) <thomas.perrot@bootlin.com>
---
Changes in v6:
- mfd: rename local variable to ddata in probe
- mfd: fix driver name from "aaeon_mcu" to "aaeon-mcu"
- mfd: set I2C_M_DMA_SAFE on all i2c_msg flags so the host driver
skips bounce-buffering the heap-allocated DMA-safe buffers
- mfd: drop COMPILE_TEST
- gpio: replace __set/__clear/__assign_bit with atomic set_bit/
clear_bit/assign_bit to fix potential races on shared bitmaps
- gpio: write output value before switching pin to output mode to
avoid a potential glitch on direction_output
- gpio: add MODULE_ALIAS("platform:aaeon-mcu-gpio")
- watchdog: add WDIOF_SETTIMEOUT and watchdog_init_timeout() so the
software timeout is configurable via ioctl, DT timeout-sec or
the watchdog_timeout boot parameter
- watchdog: add watchdog_stop_on_reboot() to prevent a spurious
reset from the external MCU during system shutdown
- watchdog: add MODULE_ALIAS("platform:aaeon-mcu-wdt")
- Link to v5: https://lore.kernel.org/r/20260408-dev-b4-aaeon-mcu-driver-v5-0-ad98bd481668@bootlin.com
Changes in v5:
- mfd: use heap-allocated DMA-safe buffers for I2C transfers, replacing
stack-allocated buffers in the regmap bus callbacks
- mfd: switch from REGCACHE_NONE to REGCACHE_MAPLE; add volatile_reg
callback marking GPIO input read registers (opcode 0x72) as volatile;
add max_register
- mfd: use PLATFORM_DEVID_AUTO instead of PLATFORM_DEVID_NONE
- mfd: use MFD_CELL_BASIC() macro for cell definitions
- mfd: use dev_err_probe() for regmap initialization error
- Link to v4: https://lore.kernel.org/r/20260324-dev-b4-aaeon-mcu-driver-v4-0-afb011df4794@bootlin.com
Changes in v4:
- mfd: switch to a custom regmap bus; remove aaeon_mcu_i2c_xfer() and the aaeon_mcu_dev struct
- mfd: locking delegated to regmap's built-in mutex; drop explicit mutex
- mfd: remove firmware version reading at probe time
- gpio, watchdog: use regmap_read()/regmap_write() via dev_get_regmap()
- include: replace aaeon_mcu_i2c_xfer() declaration with AAEON_MCU_REG() macro
- dt-bindings: remove unused label from example node
- Link to v3: https://lore.kernel.org/r/20260203-dev-b4-aaeon-mcu-driver-v3-0-0a19432076ac@bootlin.com
Changes in v3:
- Renamed SRG-IMX8PL to SRG-IMX8P
- dt-bindings: add gpio-controller properties as required
- mfd: move struct aaeon_mcu_dev from header to .c file (private)
- mfd: use guard(mutex) and devm_mutex_init() for cleanup
- mfd: firmware version log changed to dev_dbg()
- mfd: add select MFD_CORE to Kconfig
- Kconfig: add || COMPILE_TEST to all three drivers
- watchdog: add comments explaining hardware timeout and WDOG_HW_RUNNING
- watchdog: remove unused platform_set_drvdata()
- watchdog: add a function to query the status
- Link to v2: https://lore.kernel.org/r/20260123-dev-b4-aaeon-mcu-driver-v2-0-9f4c00bfb5cb@bootlin.com
Changes in v2:
- Fold GPIO and watchdog bindings into MFD binding
- Drop OF_GPIO dependency in GPIO Kconfig
- Use __set_bit/__clear_bit/__assign_bit instead of atomic variants
- Various driver cleanups and improvements
- Link to v1: https://lore.kernel.org/r/20251212-dev-b4-aaeon-mcu-driver-v1-0-6bd65bc8ef12@bootlin.com
---
Thomas Perrot (Schneider Electric) (5):
dt-bindings: vendor-prefixes: Add AAEON vendor prefix
dt-bindings: mfd: Add AAEON embedded controller
mfd: aaeon: Add SRG-IMX8P MCU driver
gpio: aaeon: Add GPIO driver for SRG-IMX8P MCU
watchdog: aaeon: Add watchdog driver for SRG-IMX8P MCU
.../bindings/mfd/aaeon,srg-imx8p-mcu.yaml | 67 ++++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 10 +
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-aaeon-mcu.c | 230 +++++++++++++++++++++
drivers/mfd/Kconfig | 11 +
drivers/mfd/Makefile | 1 +
drivers/mfd/aaeon-mcu.c | 205 ++++++++++++++++++
drivers/watchdog/Kconfig | 10 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/aaeon_mcu_wdt.c | 144 +++++++++++++
include/linux/mfd/aaeon-mcu.h | 40 ++++
13 files changed, 731 insertions(+)
---
base-commit: d358e5254674b70f34c847715ca509e46eb81e6f
change-id: 20251211-dev-b4-aaeon-mcu-driver-e0e89ebf4afb
Best regards,
--
Thomas Perrot (Schneider Electric) <thomas.perrot@bootlin.com>
^ permalink raw reply
* [PATCH v6 1/5] dt-bindings: vendor-prefixes: Add AAEON vendor prefix
From: Thomas Perrot (Schneider Electric) @ 2026-06-30 12:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
Jérémie Dautheribes, Wim Van Sebroeck, Guenter Roeck,
Lee Jones
Cc: devicetree, linux-kernel, linux-gpio, imx, linux-arm-kernel,
linux-watchdog, Thomas Petazzoni, Miquel Raynal,
Thomas Perrot (Schneider Electric), Krzysztof Kozlowski
In-Reply-To: <20260630-dev-b4-aaeon-mcu-driver-v6-0-d66b5fcbd2f0@bootlin.com>
Add the AAEON vendor prefix to support the AAEON SRG-IMX8P MCU driver
devicetree bindings.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Thomas Perrot (Schneider Electric) <thomas.perrot@bootlin.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index c7591b2aec2a..0f84ee93b3a8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -32,6 +32,8 @@ patternProperties:
description: 8devices, UAB
"^9tripod,.*":
description: Shenzhen 9Tripod Innovation and Development CO., LTD.
+ "^aaeon,.*":
+ description: AAEON
"^abb,.*":
description: ABB
"^abilis,.*":
--
2.54.0
^ permalink raw reply related
* [PATCH v6 2/5] dt-bindings: mfd: Add AAEON embedded controller
From: Thomas Perrot (Schneider Electric) @ 2026-06-30 12:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
Jérémie Dautheribes, Wim Van Sebroeck, Guenter Roeck,
Lee Jones
Cc: devicetree, linux-kernel, linux-gpio, imx, linux-arm-kernel,
linux-watchdog, Thomas Petazzoni, Miquel Raynal,
Thomas Perrot (Schneider Electric), Conor Dooley
In-Reply-To: <20260630-dev-b4-aaeon-mcu-driver-v6-0-d66b5fcbd2f0@bootlin.com>
Add device tree binding documentation for the AAEON embedded controller
(MCU). This microcontroller is found on AAEON embedded boards, it is
connected via I2C and provides GPIO control and a watchdog timer.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Thomas Perrot (Schneider Electric) <thomas.perrot@bootlin.com>
---
.../bindings/mfd/aaeon,srg-imx8p-mcu.yaml | 67 ++++++++++++++++++++++
MAINTAINERS | 6 ++
2 files changed, 73 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml b/Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml
new file mode 100644
index 000000000000..034fb7b42551
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/aaeon,srg-imx8p-mcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AAEON Embedded Controller
+
+maintainers:
+ - Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
+ - Thomas Perrot <thomas.perrot@bootlin.com>
+
+description:
+ AAEON embeds a microcontroller on Standard RISC Gateway with ARM i.MX8M Plus
+ Quad-Core boards providing GPIO control and watchdog timer.
+
+ This MCU is connected via I2C bus.
+
+ Its GPIO controller provides 7 GPOs and 12 GPIOs.
+
+ Its watchdog has a fixed maximum hardware heartbeat of 25 seconds and supports
+ a timeout of 240 seconds through automatic pinging.
+ The timeout is not programmable and cannot be changed via device tree properties.
+
+properties:
+ compatible:
+ const: aaeon,srg-imx8p-mcu
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-line-names:
+ minItems: 1
+ maxItems: 19
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ embedded-controller@62 {
+ compatible = "aaeon,srg-imx8p-mcu";
+ reg = <0x62>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "gpo-1", "gpo-2", "gpo-3", "gpo-4",
+ "gpo-5", "gpo-6", "gpo-7",
+ "gpio-1", "gpio-2", "gpio-3", "gpio-4",
+ "gpio-5", "gpio-6", "gpio-7", "gpio-8",
+ "gpio-9", "gpio-10", "gpio-11", "gpio-12";
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index c9e416ba74c6..ea9d55f76f35 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -186,6 +186,12 @@ W: http://www.adaptec.com/
F: Documentation/scsi/aacraid.rst
F: drivers/scsi/aacraid/
+AAEON SRG-IMX8P CONTROLLER MFD DRIVER
+M: Thomas Perrot <thomas.perrot@bootlin.com>
+R: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
+S: Maintained
+F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml
+
AAEON UPBOARD FPGA MFD DRIVER
M: Thomas Richard <thomas.richard@bootlin.com>
S: Maintained
--
2.54.0
^ permalink raw reply related
* [PATCH v6 3/5] mfd: aaeon: Add SRG-IMX8P MCU driver
From: Thomas Perrot (Schneider Electric) @ 2026-06-30 12:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
Jérémie Dautheribes, Wim Van Sebroeck, Guenter Roeck,
Lee Jones
Cc: devicetree, linux-kernel, linux-gpio, imx, linux-arm-kernel,
linux-watchdog, Thomas Petazzoni, Miquel Raynal,
Thomas Perrot (Schneider Electric)
In-Reply-To: <20260630-dev-b4-aaeon-mcu-driver-v6-0-d66b5fcbd2f0@bootlin.com>
Add Multi-Function Device (MFD) driver for the Aaeon SRG-IMX8P
embedded controller. This driver provides the core I2C communication
interface and registers child devices (GPIO and watchdog controllers).
The driver implements a custom regmap bus over I2C to match the MCU's
fixed 3-byte command format [opcode, arg, value]. Register addresses
are encoded as 16-bit values (opcode << 8 | arg) using the
AAEON_MCU_REG() macro defined in the shared header. The regmap
instance is shared with child drivers via dev_get_regmap(). Concurrent
I2C accesses from child drivers are serialized by regmap's built-in
locking.
I2C transfers use heap-allocated DMA-safe buffers rather than
stack-allocated ones, as required by I2C controllers that perform DMA.
Regmap caching is enabled (REGCACHE_MAPLE) with a volatile_reg
callback that marks GPIO input read registers (opcode 0x72) and the
watchdog status register (opcode 0x63, arg 0x02) as volatile. All
other registers written by the driver (GPIO direction,
GPO state, watchdog control) are stable and can be safely cached.
Co-developed-by: Jérémie Dautheribes (Schneider Electric) <jeremie.dautheribes@bootlin.com>
Signed-off-by: Jérémie Dautheribes (Schneider Electric) <jeremie.dautheribes@bootlin.com>
Signed-off-by: Thomas Perrot (Schneider Electric) <thomas.perrot@bootlin.com>
---
MAINTAINERS | 2 +
drivers/mfd/Kconfig | 11 +++
drivers/mfd/Makefile | 1 +
drivers/mfd/aaeon-mcu.c | 205 ++++++++++++++++++++++++++++++++++++++++++
include/linux/mfd/aaeon-mcu.h | 40 +++++++++
5 files changed, 259 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ea9d55f76f35..f91b6a1826d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -191,6 +191,8 @@ M: Thomas Perrot <thomas.perrot@bootlin.com>
R: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
S: Maintained
F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml
+F: drivers/mfd/aaeon-mcu.c
+F: include/linux/mfd/aaeon-mcu.h
AAEON UPBOARD FPGA MFD DRIVER
M: Thomas Richard <thomas.richard@bootlin.com>
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index aace5766b38a..ed5169c7a683 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1561,6 +1561,17 @@ config ABX500_CORE
remain unchanged when IC changes. Binding of the functions to
actual register access is done by the IC core driver.
+config MFD_AAEON_MCU
+ tristate "Aaeon SRG-IMX8P MCU Driver"
+ depends on I2C
+ select MFD_CORE
+ select REGMAP
+ help
+ Select this option to enable support for the Aaeon SRG-IMX8P
+ onboard microcontroller (MCU). This driver provides the core
+ functionality to communicate with the MCU over I2C. The MCU
+ provides GPIO and watchdog functionality.
+
config AB8500_CORE
bool "ST-Ericsson AB8500 Mixed Signal Power Management chip"
depends on ABX500_CORE && MFD_DB8500_PRCMU
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index e75e8045c28a..34db5b033584 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o
obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o
obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
obj-$(CONFIG_MFD_88PM886_PMIC) += 88pm886.o
+obj-$(CONFIG_MFD_AAEON_MCU) += aaeon-mcu.o
obj-$(CONFIG_MFD_ACT8945A) += act8945a.o
obj-$(CONFIG_MFD_SM501) += sm501.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o
diff --git a/drivers/mfd/aaeon-mcu.c b/drivers/mfd/aaeon-mcu.c
new file mode 100644
index 000000000000..306aaac1bd60
--- /dev/null
+++ b/drivers/mfd/aaeon-mcu.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Aaeon MCU driver
+ *
+ * Copyright (C) 2026 Bootlin
+ * Author: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
+ * Author: Thomas Perrot <thomas.perrot@bootlin.com>
+ */
+
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/mfd/aaeon-mcu.h>
+#include <linux/mfd/core.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+struct aaeon_mcu {
+ struct i2c_client *client;
+ u8 *cmd; /* DMA-safe 3-byte write buffer [opcode, arg, value] */
+ u8 *response; /* DMA-safe 1-byte read buffer for MCU acknowledgment */
+};
+
+static const struct mfd_cell aaeon_mcu_devs[] = {
+ MFD_CELL_BASIC("aaeon-mcu-wdt", NULL, NULL, 0, 0),
+ MFD_CELL_BASIC("aaeon-mcu-gpio", NULL, NULL, 0, 0),
+};
+
+/* Number of bytes in a MCU command: [opcode, arg, value] */
+#define AAEON_MCU_CMD_LEN 3
+
+/*
+ * Custom regmap bus for the Aaeon MCU I2C protocol.
+ *
+ * The MCU uses a fixed 3-byte command format [opcode, arg, value] followed
+ * by a 1-byte response. It requires a STOP condition between the command
+ * write and the response read, so two separate i2c_transfer() calls are
+ * issued. The regmap lock serialises concurrent accesses from the GPIO
+ * and watchdog child drivers.
+ *
+ * Register addresses are encoded as a 16-bit big-endian value where the
+ * high byte is the opcode and the low byte is the argument, matching the
+ * wire layout produced by regmap for reg_bits=16.
+ */
+
+static int aaeon_mcu_regmap_write(void *context, const void *data, size_t count)
+{
+ struct aaeon_mcu *mcu = context;
+ struct i2c_client *client = mcu->client;
+ struct i2c_msg write_msg;
+ /* The MCU always sends a response byte after each command; discard it. */
+ struct i2c_msg response_msg;
+ int ret;
+
+ memcpy(mcu->cmd, data, count);
+
+ write_msg.addr = client->addr;
+ write_msg.flags = I2C_M_DMA_SAFE;
+ write_msg.buf = mcu->cmd;
+ write_msg.len = count;
+
+ response_msg.addr = client->addr;
+ response_msg.flags = I2C_M_RD | I2C_M_DMA_SAFE;
+ response_msg.buf = mcu->response;
+ response_msg.len = 1;
+
+ ret = i2c_transfer(client->adapter, &write_msg, 1);
+ if (ret < 0)
+ return ret;
+ if (ret != 1)
+ return -EIO;
+
+ ret = i2c_transfer(client->adapter, &response_msg, 1);
+ if (ret < 0)
+ return ret;
+ if (ret != 1)
+ return -EIO;
+
+ return 0;
+}
+
+static int aaeon_mcu_regmap_read(void *context, const void *reg_buf,
+ size_t reg_size, void *val_buf, size_t val_size)
+{
+ struct aaeon_mcu *mcu = context;
+ struct i2c_client *client = mcu->client;
+ struct i2c_msg write_msg;
+ struct i2c_msg read_msg;
+ int ret;
+
+ /*
+ * reg_buf holds the 2-byte big-endian register address [opcode, arg].
+ * Append a trailing 0x00 to form the full 3-byte MCU command.
+ */
+ mcu->cmd[0] = ((u8 *)reg_buf)[0];
+ mcu->cmd[1] = ((u8 *)reg_buf)[1];
+ mcu->cmd[2] = 0x00;
+
+ write_msg.addr = client->addr;
+ write_msg.flags = I2C_M_DMA_SAFE;
+ write_msg.buf = mcu->cmd;
+ write_msg.len = AAEON_MCU_CMD_LEN;
+
+ read_msg.addr = client->addr;
+ read_msg.flags = I2C_M_RD | I2C_M_DMA_SAFE;
+ read_msg.buf = val_buf;
+ read_msg.len = val_size;
+
+ ret = i2c_transfer(client->adapter, &write_msg, 1);
+ if (ret < 0)
+ return ret;
+ if (ret != 1)
+ return -EIO;
+
+ ret = i2c_transfer(client->adapter, &read_msg, 1);
+ if (ret < 0)
+ return ret;
+ if (ret != 1)
+ return -EIO;
+
+ return 0;
+}
+
+static const struct regmap_bus aaeon_mcu_regmap_bus = {
+ .write = aaeon_mcu_regmap_write,
+ .read = aaeon_mcu_regmap_read,
+};
+
+static bool aaeon_mcu_volatile_reg(struct device *dev, unsigned int reg)
+{
+ /*
+ * GPIO input registers are driven by external signals and can change
+ * at any time without CPU involvement, always read from hardware.
+ *
+ * The watchdog status register reflects hardware state and can change
+ * autonomously.
+ *
+ * All other registers are written by the driver and their values are
+ * stable, so they can be safely cached.
+ */
+ if ((reg >> 8) == AAEON_MCU_READ_GPIO_OPCODE)
+ return true;
+ if (reg == AAEON_MCU_REG(AAEON_MCU_CONTROL_WDT_OPCODE, 0x02))
+ return true;
+ return false;
+}
+
+static const struct regmap_config aaeon_mcu_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 8,
+ .reg_format_endian = REGMAP_ENDIAN_BIG,
+ .max_register = AAEON_MCU_MAX_REGISTER,
+ .volatile_reg = aaeon_mcu_volatile_reg,
+ .cache_type = REGCACHE_MAPLE,
+};
+
+static int aaeon_mcu_probe(struct i2c_client *client)
+{
+ struct aaeon_mcu *ddata;
+ struct regmap *regmap;
+
+ ddata = devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL);
+ if (!ddata)
+ return -ENOMEM;
+
+ ddata->client = client;
+
+ ddata->cmd = devm_kzalloc(&client->dev, AAEON_MCU_CMD_LEN * sizeof(*ddata->cmd),
+ GFP_KERNEL);
+ if (!ddata->cmd)
+ return -ENOMEM;
+
+ ddata->response = devm_kzalloc(&client->dev, sizeof(*ddata->response), GFP_KERNEL);
+ if (!ddata->response)
+ return -ENOMEM;
+
+ regmap = devm_regmap_init(&client->dev, &aaeon_mcu_regmap_bus,
+ ddata, &aaeon_mcu_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(&client->dev, PTR_ERR(regmap),
+ "failed to initialize regmap\n");
+
+ return devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO,
+ aaeon_mcu_devs, ARRAY_SIZE(aaeon_mcu_devs),
+ NULL, 0, NULL);
+}
+
+static const struct of_device_id aaeon_mcu_of_match[] = {
+ { .compatible = "aaeon,srg-imx8p-mcu" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, aaeon_mcu_of_match);
+
+static struct i2c_driver aaeon_mcu_driver = {
+ .driver = {
+ .name = "aaeon-mcu",
+ .of_match_table = aaeon_mcu_of_match,
+ },
+ .probe = aaeon_mcu_probe,
+};
+module_i2c_driver(aaeon_mcu_driver);
+
+MODULE_DESCRIPTION("Aaeon MCU Driver");
+MODULE_AUTHOR("Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/aaeon-mcu.h b/include/linux/mfd/aaeon-mcu.h
new file mode 100644
index 000000000000..3a1aeec85d60
--- /dev/null
+++ b/include/linux/mfd/aaeon-mcu.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Aaeon MCU driver definitions
+ *
+ * Copyright (C) 2026 Bootlin
+ * Author: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
+ * Author: Thomas Perrot <thomas.perrot@bootlin.com>
+ */
+
+#ifndef __LINUX_MFD_AAEON_MCU_H
+#define __LINUX_MFD_AAEON_MCU_H
+
+/*
+ * MCU register address: the high byte is the command opcode, the low
+ * byte is the argument. This matches the 3-byte wire format
+ * [opcode, arg, value] used by the MCU I2C protocol.
+ */
+#define AAEON_MCU_REG(op, arg) (((op) << 8) | (arg))
+
+/*
+ * Opcode for GPIO input reads. These registers are volatile, their values
+ * are driven by external signals and can change without CPU involvement.
+ * Used by the MFD driver's volatile_reg callback to bypass the regmap cache.
+ */
+#define AAEON_MCU_READ_GPIO_OPCODE 0x72
+
+/*
+ * Opcode for watchdog control and status commands.
+ * The status register (arg=0x02) reflects hardware state and is volatile.
+ */
+#define AAEON_MCU_CONTROL_WDT_OPCODE 0x63
+
+/*
+ * Highest register address in the MCU register map.
+ * The WRITE_GPIO opcode (0x77) with the highest GPIO argument (0x0B = 11,
+ * i.e. MAX_GPIOS - 1) produces the largest encoded address.
+ */
+#define AAEON_MCU_MAX_REGISTER AAEON_MCU_REG(0x77, 0x0B)
+
+#endif /* __LINUX_MFD_AAEON_MCU_H */
--
2.54.0
^ permalink raw reply related
* [PATCH v6 4/5] gpio: aaeon: Add GPIO driver for SRG-IMX8P MCU
From: Thomas Perrot (Schneider Electric) @ 2026-06-30 12:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
Jérémie Dautheribes, Wim Van Sebroeck, Guenter Roeck,
Lee Jones
Cc: devicetree, linux-kernel, linux-gpio, imx, linux-arm-kernel,
linux-watchdog, Thomas Petazzoni, Miquel Raynal,
Thomas Perrot (Schneider Electric), Bartosz Golaszewski
In-Reply-To: <20260630-dev-b4-aaeon-mcu-driver-v6-0-d66b5fcbd2f0@bootlin.com>
Add GPIO driver for the Aaeon SRG-IMX8P embedded controller. This
driver supports 7 GPO (General Purpose Output) pins and 12 GPIO pins
that can be configured as inputs or outputs.
The driver implements proper state management for GPO pins (which are
output-only) and full direction control for GPIO pins. During probe,
all pins are reset to a known state (GPOs low, GPIOs as inputs) to
prevent undefined behavior across system reboots, as the MCU does not
reset GPIO states on soft reboot.
Co-developed-by: Jérémie Dautheribes (Schneider Electric) <jeremie.dautheribes@bootlin.com>
Signed-off-by: Jérémie Dautheribes (Schneider Electric) <jeremie.dautheribes@bootlin.com>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Thomas Perrot (Schneider Electric) <thomas.perrot@bootlin.com>
---
MAINTAINERS | 1 +
drivers/gpio/Kconfig | 9 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-aaeon-mcu.c | 230 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 241 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f91b6a1826d0..2538f8c4bc14 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -191,6 +191,7 @@ M: Thomas Perrot <thomas.perrot@bootlin.com>
R: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
S: Maintained
F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml
+F: drivers/gpio/gpio-aaeon-mcu.c
F: drivers/mfd/aaeon-mcu.c
F: include/linux/mfd/aaeon-mcu.h
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c74da29253e8..4b37b5a15958 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -157,6 +157,15 @@ config GPIO_74XX_MMIO
8 bits: 74244 (Input), 74273 (Output)
16 bits: 741624 (Input), 7416374 (Output)
+config GPIO_AAEON_MCU
+ tristate "Aaeon MCU GPIO support"
+ depends on MFD_AAEON_MCU
+ help
+ Select this option to enable GPIO support for the Aaeon SRG-IMX8P
+ onboard MCU. This driver provides access to GPIO pins and GPO
+ (General Purpose Output) pins controlled by the microcontroller.
+ The driver handles both input and output configuration.
+
config GPIO_ALTERA
tristate "Altera GPIO"
select GPIOLIB_IRQCHIP
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 2421a8fd3733..1ba6318bc558 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_104_IDI_48) += gpio-104-idi-48.o
obj-$(CONFIG_GPIO_104_IDIO_16) += gpio-104-idio-16.o
obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o
obj-$(CONFIG_GPIO_74XX_MMIO) += gpio-74xx-mmio.o
+obj-$(CONFIG_GPIO_AAEON_MCU) += gpio-aaeon-mcu.o
obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
obj-$(CONFIG_GPIO_ADP5585) += gpio-adp5585.o
diff --git a/drivers/gpio/gpio-aaeon-mcu.c b/drivers/gpio/gpio-aaeon-mcu.c
new file mode 100644
index 000000000000..a9e048c865f5
--- /dev/null
+++ b/drivers/gpio/gpio-aaeon-mcu.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Aaeon MCU GPIO driver
+ *
+ * Copyright (C) 2026 Bootlin
+ * Author: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
+ * Author: Thomas Perrot <thomas.perrot@bootlin.com>
+ */
+
+#include <linux/bitops.h>
+#include <linux/gpio/driver.h>
+#include <linux/mfd/aaeon-mcu.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#define AAEON_MCU_CONFIG_GPIO_INPUT 0x69
+#define AAEON_MCU_CONFIG_GPIO_OUTPUT 0x6F
+#define AAEON_MCU_READ_GPIO 0x72
+#define AAEON_MCU_WRITE_GPIO 0x77
+
+#define AAEON_MCU_CONTROL_GPO 0x6C
+
+#define MAX_GPIOS 12
+#define MAX_GPOS 7
+
+struct aaeon_mcu_gpio {
+ struct gpio_chip gc;
+ struct regmap *regmap;
+ DECLARE_BITMAP(dir_in, MAX_GPOS + MAX_GPIOS);
+ DECLARE_BITMAP(gpo_state, MAX_GPOS);
+};
+
+static int aaeon_mcu_gpio_config_input_cmd(struct aaeon_mcu_gpio *data,
+ unsigned int offset)
+{
+ return regmap_write(data->regmap,
+ AAEON_MCU_REG(AAEON_MCU_CONFIG_GPIO_INPUT, offset - 7),
+ 0);
+}
+
+static int aaeon_mcu_gpo_set_cmd(struct aaeon_mcu_gpio *data, unsigned int offset, int value)
+{
+ return regmap_write(data->regmap,
+ AAEON_MCU_REG(AAEON_MCU_CONTROL_GPO, offset + 1),
+ !!value);
+}
+
+static int aaeon_mcu_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
+{
+ struct aaeon_mcu_gpio *data = gpiochip_get_data(gc);
+ int ret;
+
+ if (offset < MAX_GPOS) {
+ dev_err(gc->parent,
+ "offset %d is a GPO (output-only) pin, cannot be configured as input\n",
+ offset);
+ return -EOPNOTSUPP;
+ }
+
+ ret = aaeon_mcu_gpio_config_input_cmd(data, offset);
+ if (ret < 0)
+ return ret;
+
+ set_bit(offset, data->dir_in);
+
+ return 0;
+}
+
+static int aaeon_mcu_gpio_config_output_cmd(struct aaeon_mcu_gpio *data,
+ unsigned int offset,
+ int value)
+{
+ int ret;
+
+ ret = regmap_write(data->regmap,
+ AAEON_MCU_REG(AAEON_MCU_WRITE_GPIO, offset - 7),
+ !!value);
+ if (ret < 0)
+ return ret;
+
+ return regmap_write(data->regmap,
+ AAEON_MCU_REG(AAEON_MCU_CONFIG_GPIO_OUTPUT, offset - 7),
+ 0);
+}
+
+static int aaeon_mcu_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
+{
+ struct aaeon_mcu_gpio *data = gpiochip_get_data(gc);
+ int ret;
+
+ if (offset < MAX_GPOS) {
+ ret = aaeon_mcu_gpo_set_cmd(data, offset, value);
+ if (ret)
+ return ret;
+ assign_bit(offset, data->gpo_state, value);
+ return 0;
+ }
+
+ ret = aaeon_mcu_gpio_config_output_cmd(data, offset, value);
+ if (ret < 0)
+ return ret;
+
+ clear_bit(offset, data->dir_in);
+
+ return 0;
+}
+
+static int aaeon_mcu_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+ struct aaeon_mcu_gpio *data = gpiochip_get_data(gc);
+
+ return test_bit(offset, data->dir_in) ?
+ GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
+}
+
+static int aaeon_mcu_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct aaeon_mcu_gpio *data = gpiochip_get_data(gc);
+ unsigned int rsp;
+ int ret;
+
+ if (offset < MAX_GPOS)
+ return test_bit(offset, data->gpo_state);
+
+ ret = regmap_read(data->regmap,
+ AAEON_MCU_REG(AAEON_MCU_READ_GPIO, offset - 7),
+ &rsp);
+ if (ret < 0)
+ return ret;
+
+ return rsp;
+}
+
+static int aaeon_mcu_gpio_set_cmd(struct aaeon_mcu_gpio *data, unsigned int offset, int value)
+{
+ return regmap_write(data->regmap,
+ AAEON_MCU_REG(AAEON_MCU_WRITE_GPIO, offset - 7),
+ !!value);
+}
+
+static int aaeon_mcu_gpio_set(struct gpio_chip *gc, unsigned int offset,
+ int value)
+{
+ struct aaeon_mcu_gpio *data = gpiochip_get_data(gc);
+ int ret;
+
+ if (offset >= MAX_GPOS)
+ return aaeon_mcu_gpio_set_cmd(data, offset, value);
+
+ ret = aaeon_mcu_gpo_set_cmd(data, offset, value);
+ if (ret)
+ return ret;
+ assign_bit(offset, data->gpo_state, value);
+ return 0;
+}
+
+static const struct gpio_chip aaeon_mcu_chip = {
+ .label = "gpio-aaeon-mcu",
+ .owner = THIS_MODULE,
+ .get_direction = aaeon_mcu_gpio_get_direction,
+ .direction_input = aaeon_mcu_gpio_direction_input,
+ .direction_output = aaeon_mcu_gpio_direction_output,
+ .get = aaeon_mcu_gpio_get,
+ .set = aaeon_mcu_gpio_set,
+ .base = -1,
+ .ngpio = MAX_GPOS + MAX_GPIOS,
+ .can_sleep = true,
+};
+
+static void aaeon_mcu_gpio_reset(struct aaeon_mcu_gpio *data, struct device *dev)
+{
+ unsigned int i;
+ int ret;
+
+ /* Reset all GPOs */
+ for (i = 0; i < MAX_GPOS; i++) {
+ ret = aaeon_mcu_gpo_set_cmd(data, i, 0);
+ if (ret < 0)
+ dev_warn(dev, "Failed to reset GPO %u state: %d\n", i, ret);
+ clear_bit(i, data->dir_in);
+ }
+
+ /* Reset all GPIOs */
+ for (i = MAX_GPOS; i < MAX_GPOS + MAX_GPIOS; i++) {
+ ret = aaeon_mcu_gpio_config_input_cmd(data, i);
+ if (ret < 0)
+ dev_warn(dev, "Failed to reset GPIO %u state: %d\n", i, ret);
+ set_bit(i, data->dir_in);
+ }
+}
+
+static int aaeon_mcu_gpio_probe(struct platform_device *pdev)
+{
+ struct aaeon_mcu_gpio *data;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!data->regmap)
+ return -ENODEV;
+
+ data->gc = aaeon_mcu_chip;
+ data->gc.parent = pdev->dev.parent;
+
+ /*
+ * Reset all GPIO states to a known configuration. The MCU does not
+ * reset GPIO state on soft reboot, only on power cycle (hard reboot).
+ * Without this reset, GPIOs would retain their previous state across
+ * reboots, which could lead to unexpected behavior.
+ */
+ aaeon_mcu_gpio_reset(data, &pdev->dev);
+
+ return devm_gpiochip_add_data(&pdev->dev, &data->gc, data);
+}
+
+static struct platform_driver aaeon_mcu_gpio_driver = {
+ .driver = {
+ .name = "aaeon-mcu-gpio",
+ },
+ .probe = aaeon_mcu_gpio_probe,
+};
+module_platform_driver(aaeon_mcu_gpio_driver);
+
+MODULE_ALIAS("platform:aaeon-mcu-gpio");
+MODULE_DESCRIPTION("GPIO interface for Aaeon MCU");
+MODULE_AUTHOR("Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH v6 5/5] watchdog: aaeon: Add watchdog driver for SRG-IMX8P MCU
From: Thomas Perrot (Schneider Electric) @ 2026-06-30 12:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
Jérémie Dautheribes, Wim Van Sebroeck, Guenter Roeck,
Lee Jones
Cc: devicetree, linux-kernel, linux-gpio, imx, linux-arm-kernel,
linux-watchdog, Thomas Petazzoni, Miquel Raynal,
Thomas Perrot (Schneider Electric)
In-Reply-To: <20260630-dev-b4-aaeon-mcu-driver-v6-0-d66b5fcbd2f0@bootlin.com>
Add watchdog driver for the Aaeon SRG-IMX8P embedded controller.
This driver provides system monitoring and recovery capabilities
through the MCU's watchdog timer.
The watchdog supports start, stop, and ping operations with a maximum
hardware heartbeat of 25 seconds and a default timeout of 240 seconds.
The software timeout can be changed via the WDIOC_SETTIMEOUT ioctl,
the DT timeout-sec property, or the watchdog_timeout kernel boot
parameter.
Co-developed-by: Jérémie Dautheribes (Schneider Electric) <jeremie.dautheribes@bootlin.com>
Signed-off-by: Jérémie Dautheribes (Schneider Electric) <jeremie.dautheribes@bootlin.com>
Signed-off-by: Thomas Perrot (Schneider Electric) <thomas.perrot@bootlin.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
---
MAINTAINERS | 1 +
drivers/watchdog/Kconfig | 10 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/aaeon_mcu_wdt.c | 144 +++++++++++++++++++++++++++++++++++++++
4 files changed, 156 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2538f8c4bc14..7b92af42c9fd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -193,6 +193,7 @@ S: Maintained
F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml
F: drivers/gpio/gpio-aaeon-mcu.c
F: drivers/mfd/aaeon-mcu.c
+F: drivers/watchdog/aaeon_mcu_wdt.c
F: include/linux/mfd/aaeon-mcu.h
AAEON UPBOARD FPGA MFD DRIVER
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index d3b9df7d466b..f67a0b453316 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -420,6 +420,16 @@ config SL28CPLD_WATCHDOG
# ARM Architecture
+config AAEON_MCU_WATCHDOG
+ tristate "Aaeon MCU Watchdog"
+ depends on MFD_AAEON_MCU
+ select WATCHDOG_CORE
+ help
+ Select this option to enable watchdog timer support for the Aaeon
+ SRG-IMX8P onboard microcontroller (MCU). This driver provides
+ watchdog functionality through the MCU, allowing system monitoring
+ and automatic recovery from system hangs.
+
config AIROHA_WATCHDOG
tristate "Airoha EN7581 Watchdog"
depends on ARCH_AIROHA || COMPILE_TEST
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index ba52099b1253..2deec425d3ea 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o
# ALPHA Architecture
# ARM Architecture
+obj-$(CONFIG_AAEON_MCU_WATCHDOG) += aaeon_mcu_wdt.o
obj-$(CONFIG_ARM_SP805_WATCHDOG) += sp805_wdt.o
obj-$(CONFIG_ARM_SBSA_WATCHDOG) += sbsa_gwdt.o
obj-$(CONFIG_ARMADA_37XX_WATCHDOG) += armada_37xx_wdt.o
diff --git a/drivers/watchdog/aaeon_mcu_wdt.c b/drivers/watchdog/aaeon_mcu_wdt.c
new file mode 100644
index 000000000000..347ee8269bfd
--- /dev/null
+++ b/drivers/watchdog/aaeon_mcu_wdt.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Aaeon MCU Watchdog driver
+ *
+ * Copyright (C) 2026 Bootlin
+ * Author: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
+ * Author: Thomas Perrot <thomas.perrot@bootlin.com>
+ */
+
+#include <linux/mfd/aaeon-mcu.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/watchdog.h>
+
+#define AAEON_MCU_PING_WDT 0x73
+
+#define AAEON_MCU_WDT_TIMEOUT 240
+#define AAEON_MCU_WDT_HEARTBEAT_MS 25000
+#define AAEON_MCU_WDT_MIN_TIMEOUT 1
+#define AAEON_MCU_WDT_MAX_TIMEOUT 3600
+
+static unsigned int timeout;
+module_param(timeout, uint, 0);
+MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
+
+struct aaeon_mcu_wdt {
+ struct watchdog_device wdt;
+ struct regmap *regmap;
+};
+
+static int aaeon_mcu_wdt_cmd(struct aaeon_mcu_wdt *data, u8 opcode, u8 arg)
+{
+ return regmap_write(data->regmap, AAEON_MCU_REG(opcode, arg), 0);
+}
+
+static int aaeon_mcu_wdt_start(struct watchdog_device *wdt)
+{
+ struct aaeon_mcu_wdt *data = watchdog_get_drvdata(wdt);
+
+ return aaeon_mcu_wdt_cmd(data, AAEON_MCU_CONTROL_WDT_OPCODE, 0x01);
+}
+
+static int aaeon_mcu_wdt_status(struct watchdog_device *wdt, bool *enabled)
+{
+ struct aaeon_mcu_wdt *data = watchdog_get_drvdata(wdt);
+ unsigned int rsp;
+ int ret;
+
+ ret = regmap_read(data->regmap,
+ AAEON_MCU_REG(AAEON_MCU_CONTROL_WDT_OPCODE, 0x02),
+ &rsp);
+ if (ret)
+ return ret;
+
+ *enabled = rsp == 0x01;
+ return 0;
+}
+
+static int aaeon_mcu_wdt_stop(struct watchdog_device *wdt)
+{
+ struct aaeon_mcu_wdt *data = watchdog_get_drvdata(wdt);
+
+ return aaeon_mcu_wdt_cmd(data, AAEON_MCU_CONTROL_WDT_OPCODE, 0x00);
+}
+
+static int aaeon_mcu_wdt_ping(struct watchdog_device *wdt)
+{
+ struct aaeon_mcu_wdt *data = watchdog_get_drvdata(wdt);
+
+ return aaeon_mcu_wdt_cmd(data, AAEON_MCU_PING_WDT, 0x00);
+}
+
+static const struct watchdog_info aaeon_mcu_wdt_info = {
+ .identity = "Aaeon MCU Watchdog",
+ .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT
+};
+
+static const struct watchdog_ops aaeon_mcu_wdt_ops = {
+ .owner = THIS_MODULE,
+ .start = aaeon_mcu_wdt_start,
+ .stop = aaeon_mcu_wdt_stop,
+ .ping = aaeon_mcu_wdt_ping,
+};
+
+static int aaeon_mcu_wdt_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct watchdog_device *wdt;
+ struct aaeon_mcu_wdt *data;
+ bool enabled;
+ int ret;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->regmap = dev_get_regmap(dev->parent, NULL);
+ if (!data->regmap)
+ return -ENODEV;
+
+ wdt = &data->wdt;
+ wdt->parent = dev;
+ wdt->info = &aaeon_mcu_wdt_info;
+ wdt->ops = &aaeon_mcu_wdt_ops;
+ /*
+ * The MCU firmware has a fixed hardware timeout of 25 seconds that
+ * cannot be changed. The watchdog core handles automatic pinging to
+ * support software timeouts longer than the hardware limit. The default
+ * software timeout of 240 seconds can be overridden via the DT
+ * timeout-sec property or the watchdog_timeout kernel boot parameter.
+ */
+ wdt->timeout = AAEON_MCU_WDT_TIMEOUT;
+ wdt->min_timeout = AAEON_MCU_WDT_MIN_TIMEOUT;
+ wdt->max_timeout = AAEON_MCU_WDT_MAX_TIMEOUT;
+ wdt->max_hw_heartbeat_ms = AAEON_MCU_WDT_HEARTBEAT_MS;
+ watchdog_init_timeout(wdt, timeout, dev);
+
+ watchdog_set_drvdata(wdt, data);
+ watchdog_stop_on_reboot(wdt);
+
+ ret = aaeon_mcu_wdt_status(wdt, &enabled);
+ if (ret)
+ return ret;
+
+ if (enabled)
+ set_bit(WDOG_HW_RUNNING, &wdt->status);
+
+ return devm_watchdog_register_device(dev, wdt);
+}
+
+static struct platform_driver aaeon_mcu_wdt_driver = {
+ .driver = {
+ .name = "aaeon-mcu-wdt",
+ },
+ .probe = aaeon_mcu_wdt_probe,
+};
+
+module_platform_driver(aaeon_mcu_wdt_driver);
+
+MODULE_ALIAS("platform:aaeon-mcu-wdt");
+MODULE_DESCRIPTION("Aaeon MCU Watchdog Driver");
+MODULE_AUTHOR("Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* Re: [PATCH 0/3] gpio: tb10x: W=1 warning fix and style cleanups
From: Linus Walleij @ 2026-06-30 12:51 UTC (permalink / raw)
To: Igor Putko; +Cc: Bartosz Golaszewski, linux-gpio, linux-kernel
In-Reply-To: <20260618155626.18751-1-igorpetindev@gmail.com>
On Thu, Jun 18, 2026 at 4:56 PM Igor Putko <igorpetindev@gmail.com> wrote:
> This series fixes a kernel-doc warning in the tb10x GPIO driver
> and addresses two minor checkpatch.pl coding style issues.
>
> Patch 1 fixes the kernel-doc structure formatting.
> Patch 2 replaces bare unsigned with unsigned int.
> Patch 3 removes unnecessary braces from a single-statement block.
Patches 2 & 3 applied, a different version of patch 1 was
already applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v12 1/6] pinctrl: s32cc: add/fix some comments
From: Khristine Andreea Barbulescu @ 2026-06-30 12:53 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chester Lin, Matthias Brugger,
Ghennadi Procopciuc, Larisa Grigore, Lee Jones, Shawn Guo,
Sascha Hauer, Fabio Estevam, Dong Aisheng, Jacky Bai,
Greg Kroah-Hartman, Rafael J. Wysocki, Srinivas Kandagatla
Cc: Alberto Ruiz, Christophe Lizzi, devicetree, Enric Balletbo,
Eric Chanudet, imx, linux-arm-kernel, linux-gpio, linux-kernel,
NXP S32 Linux Team, Pengutronix Kernel Team, Vincent Guittot
In-Reply-To: <20260630125403.546375-1-khristineandreea.barbulescu@oss.nxp.com>
Add/fix some comments and print statements.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
---
drivers/pinctrl/nxp/pinctrl-s32cc.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c
index 56be6e8d624e..2a32df932d8a 100644
--- a/drivers/pinctrl/nxp/pinctrl-s32cc.c
+++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c
@@ -60,6 +60,12 @@ static u32 get_pin_func(u32 pinmux)
return pinmux & GENMASK(3, 0);
}
+/*
+ * struct s32_pinctrl_mem_region - memory region for a set of SIUL2 registers
+ * @map: regmap used for this range
+ * @pin_range: the pins controlled by these registers
+ * @name: name of the current range
+ */
struct s32_pinctrl_mem_region {
struct regmap *map;
const struct s32_pin_range *pin_range;
@@ -67,7 +73,7 @@ struct s32_pinctrl_mem_region {
};
/*
- * Holds pin configuration for GPIO's.
+ * struct gpio_pin_config - holds pin configuration for GPIO's
* @pin_id: Pin ID for this GPIO
* @config: Pin settings
* @list: Linked list entry for each gpio pin
@@ -79,20 +85,22 @@ struct gpio_pin_config {
};
/*
- * Pad config save/restore for power suspend/resume.
+ * struct s32_pinctrl_context - pad config save/restore for suspend/resume
+ * @pads: saved values for the pards
*/
struct s32_pinctrl_context {
unsigned int *pads;
};
/*
+ * struct s32_pinctrl - private driver data
* @dev: a pointer back to containing device
* @pctl: a pointer to the pinctrl device structure
* @regions: reserved memory regions with start/end pin
* @info: structure containing information about the pin
- * @gpio_configs: Saved configurations for GPIO pins
- * @gpiop_configs_lock: lock for the `gpio_configs` list
- * @s32_pinctrl_context: Configuration saved over system sleep
+ * @gpio_configs: saved configurations for GPIO pins
+ * @gpio_configs_lock: lock for the `gpio_configs` list
+ * @saved_context: configuration saved over system sleep
*/
struct s32_pinctrl {
struct device *dev;
@@ -970,7 +978,7 @@ int s32_pinctrl_probe(struct platform_device *pdev,
ipctl);
if (IS_ERR(ipctl->pctl))
return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl),
- "could not register s32 pinctrl driver\n");
+ "Could not register s32 pinctrl driver\n");
#ifdef CONFIG_PM_SLEEP
saved_context = &ipctl->saved_context;
--
2.34.1
^ permalink raw reply related
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