[PATCH 0/3] Introduce Exynos5515 pinctrl support

[PATCH 0/3] Introduce Exynos5515 pinctrl support

[Aiden Isik via B4 Relay]

Hi there,

This patchset introduces pinctrl support for the Exynos5515 SoC.

It is very similar to the other Exynos SoCs, therefore we reuse the driver
and for the most part the pinctrl bank macros. A couple
Exynos5515-specific macros are also added.

Kind regards,
- Aiden Isik

Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
Aiden Isik (3):
      dt-bindings: pinctrl: samsung: Add compatible for Exynos5515
      dt-bindings: pinctrl: samsung: add exynos5515-wakeup-eint compatible
      pinctrl: samsung: Add Exynos5515 pinctrl configuration

 .../pinctrl/samsung,pinctrl-wakeup-interrupt.yaml  |   1 +
 .../bindings/pinctrl/samsung,pinctrl.yaml          |   1 +
 drivers/pinctrl/samsung/pinctrl-exynos-arm64.c     | 123 +++++++++++++++++++++
 drivers/pinctrl/samsung/pinctrl-exynos.h           |  20 ++++
 drivers/pinctrl/samsung/pinctrl-samsung.c          |   2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h          |   1 +
 6 files changed, 148 insertions(+)
---
base-commit: 993e1bec85faedf90c5d27480793084e54357c09
change-id: 20261019-for-next-lucky7-pinctrl-64bf54588925

Best regards,
--  
Aiden Isik <aidenisik@member.fsf.org>

[PATCH 1/3] dt-bindings: pinctrl: samsung: Add compatible for Exynos5515

[Aiden Isik via B4 Relay]

From: Aiden Isik <aidenisik@member.fsf.org>

Document the Exynos5515 pinctrl compatible string.

Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
 Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
index 1feb6a6fc690..7e49ca7b560a 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
@@ -49,6 +49,7 @@ properties:
       - samsung,exynos5410-pinctrl
       - samsung,exynos5420-pinctrl
       - samsung,exynos5433-pinctrl
+      - samsung,exynos5515-pinctrl
       - samsung,exynos7-pinctrl
       - samsung,exynos7870-pinctrl
       - samsung,exynos7885-pinctrl

-- 
2.54.0

[PATCH 2/3] dt-bindings: pinctrl: samsung: add exynos5515-wakeup-eint compatible

[Aiden Isik via B4 Relay]

From: Aiden Isik <aidenisik@member.fsf.org>

Add the pinctrl wakeup compatible for the Exynos5515 SoC. It is
register-compatible with Exynos850, so document it as such.

Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
 .../devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
index 802911e23aff..d5200b04a1dd 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
@@ -49,6 +49,7 @@ properties:
           - enum:
               - google,gs101-wakeup-eint
               - samsung,exynos2200-wakeup-eint
+              - samsung,exynos5515-wakeup-eint
               - samsung,exynos9610-wakeup-eint
               - samsung,exynos9810-wakeup-eint
               - samsung,exynos990-wakeup-eint

-- 
2.54.0

[PATCH 3/3] pinctrl: samsung: Add Exynos5515 pinctrl configuration

[Aiden Isik via B4 Relay]

From: Aiden Isik <aidenisik@member.fsf.org>

Add the pinctrl configuration for the Exynos5515 SoC. Reuse the pinctrl
macros from Exynos850 and GS101, and add a few Exynos5515-specific macros.

Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
 drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 123 +++++++++++++++++++++++++
 drivers/pinctrl/samsung/pinctrl-exynos.h       |  20 ++++
 drivers/pinctrl/samsung/pinctrl-samsung.c      |   2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h      |   1 +
 4 files changed, 146 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index 1aa977d2a1f8..def84f7f029e 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -488,6 +488,129 @@ const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = {
 	.num_ctrl	= ARRAY_SIZE(exynos5433_pin_ctrl),
 };
 
+/* pin banks of exynos5515 pin-controller 0 (ALIVE) */
+static const struct samsung_pin_bank_data exynos5515_pin_banks0[] __initconst = {
+	GS101_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00, 0x00),
+	GS101_PIN_BANK_EINTW(7, 0x020, "gpa1", 0x04, 0x08),
+	EXYNOS850_PIN_BANK_EINTN(6, 0x040, "gpq0"),
+	EXYNOS850_PIN_BANK_EINTN(6, 0x060, "etc0"),
+};
+
+/* pin banks of exynos5515 pin-controller 1 (CMGP) */
+static const struct samsung_pin_bank_data exynos5515_pin_banks1[] __initconst = {
+	GS101_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00, 0x00),
+	GS101_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04, 0x04),
+	GS101_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08, 0x08),
+	GS101_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c, 0x0c),
+	GS101_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10, 0x10),
+	GS101_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14, 0x14),
+	GS101_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18, 0x18),
+	GS101_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c, 0x1c),
+	GS101_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20, 0x20),
+	GS101_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24, 0x24),
+	GS101_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28, 0x28),
+	GS101_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2c, 0x2c),
+	GS101_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30, 0x30),
+	GS101_PIN_BANK_EINTW(1, 0x1a0, "gpm13", 0x34, 0x34),
+	GS101_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38, 0x38),
+	GS101_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c, 0x3c),
+	GS101_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40, 0x40),
+	GS101_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44, 0x44),
+	GS101_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48, 0x48),
+	GS101_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4c, 0x4c),
+	EXYNOS5515_PIN_BANK_EINTG(1, 0x280, "gpm20", 0x50, 0x50),
+	EXYNOS5515_PIN_BANK_EINTG(1, 0x2a0, "gpm21", 0x54, 0x54),
+	GS101_PIN_BANK_EINTW(1, 0x2c0, "gpm22", 0x58, 0x58),
+	GS101_PIN_BANK_EINTW(1, 0x2e0, "gpm23", 0x5c, 0x5c),
+	GS101_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x60, 0x60),
+	GS101_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x64, 0x64),
+	GS101_PIN_BANK_EINTW(1, 0x340, "gpm26", 0x68, 0x68),
+};
+
+/* pin banks of exynos5515 pin-controller 2 (DISP) */
+static const struct samsung_pin_bank_data exynos5515_pin_banks2[] __initconst = {
+	EXYNOS5515_PIN_BANK_EINTN(5, 0x000, "gpb0"),
+	EXYNOS5515_PIN_BANK_EINTN(4, 0x020, "gpb1"),
+};
+
+/* pin banks of exynos5515 pin-controller 3 (FSYS) */
+static const struct samsung_pin_bank_data exynos5515_pin_banks3[] __initconst = {
+	EXYNOS5515_PIN_BANK_EINTN(4, 0x000, "gpf0"),
+	EXYNOS5515_PIN_BANK_EINTN(8, 0x020, "gpf1"),
+	EXYNOS5515_PIN_BANK_EINTN(6, 0x040, "gpf2"),
+};
+
+/* pin banks of exynos5515 pin-controller 4 (PERI) */
+static const struct samsung_pin_bank_data exynos5515_pin_banks4[] __initconst = {
+	GS101_PIN_BANK_EINTG(2, 0x000, "gpp0", 0x00, 0x00),
+	GS101_PIN_BANK_EINTG(2, 0x020, "gpp1", 0x04, 0x04),
+	GS101_PIN_BANK_EINTG(2, 0x040, "gpp2", 0x08, 0x08),
+	GS101_PIN_BANK_EINTG(3, 0x060, "gpp3", 0x0c, 0x0c),
+	GS101_PIN_BANK_EINTG(4, 0x080, "gpp4", 0x10, 0x10),
+	GS101_PIN_BANK_EINTG(4, 0x0A0, "gpc0", 0x14, 0x14),
+	GS101_PIN_BANK_EINTG(2, 0x0C0, "gpc1", 0x18, 0x18),
+	GS101_PIN_BANK_EINTG(2, 0x0E0, "gpg0", 0x1c, 0x1c),
+	GS101_PIN_BANK_EINTG(2, 0x100, "gpg1", 0x20, 0x20),
+	GS101_PIN_BANK_EINTG(2, 0x120, "gpg2", 0x24, 0x24),
+	GS101_PIN_BANK_EINTG(2, 0x140, "gpg3", 0x28, 0x28),
+	GS101_PIN_BANK_EINTG(2, 0x160, "gpg4", 0x2c, 0x2c),
+	GS101_PIN_BANK_EINTG(2, 0x180, "gpg5", 0x30, 0x30),
+	GS101_PIN_BANK_EINTG(2, 0x1A0, "gpg6", 0x34, 0x34),
+	GS101_PIN_BANK_EINTG(2, 0x1C0, "gpg7", 0x38, 0x38),
+};
+
+/* pin banks of exynos5515 pin-controller 5 (VTS) */
+static const struct samsung_pin_bank_data exynos5515_pin_banks5[] __initconst = {
+	EXYNOS5515_PIN_BANK_EINTN(2, 0x000, "gpv0"),
+};
+
+static const struct samsung_pin_ctrl exynos5515_pin_ctrl[] __initconst = {
+	{
+		/* pin-controller instance 0 ALIVE data */
+		.pin_banks	= exynos5515_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(exynos5515_pin_banks0),
+		.eint_gpio_init	= exynos_eint_gpio_init,
+		.eint_wkup_init	= exynos_eint_wkup_init,
+		.suspend	= gs101_pinctrl_suspend,
+		.resume		= gs101_pinctrl_resume,
+	}, {
+		/* pin-controller instance 1 CMGP data */
+		.pin_banks	= exynos5515_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(exynos5515_pin_banks1),
+		.eint_gpio_init	= exynos_eint_gpio_init,
+		.eint_wkup_init	= exynos_eint_wkup_init,
+		.suspend	= gs101_pinctrl_suspend,
+		.resume		= gs101_pinctrl_resume,
+	}, {
+		/* pin-controller instance 2 DISP data */
+		.pin_banks	= exynos5515_pin_banks2,
+		.nr_banks	= ARRAY_SIZE(exynos5515_pin_banks2),
+	}, {
+		/* pin-controller instance 3 FSYS data */
+		.pin_banks	= exynos5515_pin_banks3,
+		.nr_banks	= ARRAY_SIZE(exynos5515_pin_banks3),
+		.eint_gpio_init	= exynos_eint_gpio_init,
+		.suspend	= gs101_pinctrl_suspend,
+		.resume		= gs101_pinctrl_resume,
+	}, {
+		/* pin-controller instance 4 PERI data */
+		.pin_banks	= exynos5515_pin_banks4,
+		.nr_banks	= ARRAY_SIZE(exynos5515_pin_banks4),
+		.eint_gpio_init	= exynos_eint_gpio_init,
+		.suspend	= gs101_pinctrl_suspend,
+		.resume		= gs101_pinctrl_resume,
+	}, {
+		/* pin-controller instance 5 VTS data */
+		.pin_banks	= exynos5515_pin_banks5,
+		.nr_banks	= ARRAY_SIZE(exynos5515_pin_banks5),
+	},
+};
+
+const struct samsung_pinctrl_of_match_data exynos5515_of_data __initconst = {
+	.ctrl		= exynos5515_pin_ctrl,
+	.num_ctrl	= ARRAY_SIZE(exynos5515_pin_ctrl),
+};
+
 /* pin banks of exynos7 pin-controller - ALIVE */
 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
 	/* Must start with EINTG banks, ordered by EINT group number. */
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index c9c38f8988dd..92bf8f0f1eb0 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -132,6 +132,26 @@
 		.pctl_res_idx   = pctl_idx,			\
 	}							\
 
+#define EXYNOS5515_PIN_BANK_EINTN(pins, reg, id)		\
+	{							\
+		.type		= &exynos850_bank_type_off,	\
+		.pctl_offset	= reg,				\
+		.nr_pins	= pins,				\
+		.eint_type	= EINT_TYPE_NONE,		\
+		.name		= id				\
+	}
+
+#define EXYNOS5515_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs)	\
+	{								\
+		.type			= &exynos850_bank_type_alive,	\
+		.pctl_offset		= reg,				\
+		.nr_pins		= pins,				\
+		.eint_type		= EINT_TYPE_GPIO,		\
+		.eint_offset		= offs,				\
+		.eint_fltcon_offset	= fltcon_offs,			\
+		.name			= id				\
+	}
+
 #define EXYNOS7870_PIN_BANK_EINTN(pins, reg, id)		\
 	{							\
 		.type		= &exynos7870_bank_type_alive,	\
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 5ecc9ed4c44d..f6b392a84cee 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1492,6 +1492,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
 		.data = &exynos2200_of_data },
 	{ .compatible = "samsung,exynos5433-pinctrl",
 		.data = &exynos5433_of_data },
+	{ .compatible = "samsung,exynos5515-pinctrl",
+		.data = &exynos5515_of_data},
 	{ .compatible = "samsung,exynos7-pinctrl",
 		.data = &exynos7_of_data },
 	{ .compatible = "samsung,exynos7870-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index bb02fb49b2af..7c60375d5924 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -392,6 +392,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5260_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
+extern const struct samsung_pinctrl_of_match_data exynos5515_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos7870_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;

-- 
2.54.0

Re: [PATCH 3/3] pinctrl: samsung: Add Exynos5515 pinctrl configuration

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] pinctrl: samsung: mismatched EINT config for Exynos5515 FSYS controller
- [High] pinctrl: samsung: invalid exynos_eint_gpio_init() on Exynos5515 ALIVE
--

commit 9b9aa666ae93755ccd47b8a80ec9f4fcc81c1eca
Author: Aiden Isik <aidenisik@member.fsf.org>

pinctrl: samsung: Add Exynos5515 pinctrl configuration

This commit adds the pinctrl configuration, pin bank definitions, and
compatible string match data for the Samsung Exynos5515 SoC.

> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index 1aa977d2a1f80..def84f7f029ea 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -488,6 +488,129 @@ const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = {
>  	.num_ctrl	= ARRAY_SIZE(exynos5433_pin_ctrl),
>  };
>  
> +/* pin banks of exynos5515 pin-controller 0 (ALIVE) */
> +static const struct samsung_pin_bank_data exynos5515_pin_banks0[] __initconst = {
> +	GS101_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00, 0x00),
> +	GS101_PIN_BANK_EINTW(7, 0x020, "gpa1", 0x04, 0x08),
> +	EXYNOS850_PIN_BANK_EINTN(6, 0x040, "gpq0"),
> +	EXYNOS850_PIN_BANK_EINTN(6, 0x060, "etc0"),
> +};
> +

[ ... ]

> +/* pin banks of exynos5515 pin-controller 3 (FSYS) */
> +static const struct samsung_pin_bank_data exynos5515_pin_banks3[] __initconst = {
> +	EXYNOS5515_PIN_BANK_EINTN(4, 0x000, "gpf0"),
> +	EXYNOS5515_PIN_BANK_EINTN(8, 0x020, "gpf1"),
> +	EXYNOS5515_PIN_BANK_EINTN(6, 0x040, "gpf2"),
> +};
> +

[ ... ]

> +static const struct samsung_pin_ctrl exynos5515_pin_ctrl[] __initconst = {
> +	{
> +		/* pin-controller instance 0 ALIVE data */
> +		.pin_banks	= exynos5515_pin_banks0,
> +		.nr_banks	= ARRAY_SIZE(exynos5515_pin_banks0),
> +		.eint_gpio_init	= exynos_eint_gpio_init,
> +		.eint_wkup_init	= exynos_eint_wkup_init,
> +		.suspend	= gs101_pinctrl_suspend,
> +		.resume		= gs101_pinctrl_resume,
> +	}, {

[Severity: High]
Should eint_gpio_init be set on the ALIVE controller entry in
exynos5515_pin_ctrl?

exynos5515_pin_banks0 only defines EINT_TYPE_WKUP banks (gpa0 and gpa1 via
GS101_PIN_BANK_EINTW) and EINT_TYPE_NONE banks (gpq0 and etc0 via
EXYNOS850_PIN_BANK_EINTN), with no EINT_TYPE_GPIO banks.

When samsung_pinctrl_probe() calls exynos_eint_gpio_init() for the ALIVE
controller:

drivers/pinctrl/samsung/pinctrl-exynos.c:exynos_eint_gpio_init() {
	if (!d->irq) {
		dev_err(dev, "irq number not available\n");
		return -EINVAL;
	}
}

Because ALIVE wakeup interrupts are described per-bank and handled by
exynos_eint_wkup_init() without a controller-level GPIO interrupt property,
won't d->irq be zero and cause probe of the ALIVE pin controller to fail
with -EINVAL?

[ ... ]

> +	}, {
> +		/* pin-controller instance 3 FSYS data */
> +		.pin_banks	= exynos5515_pin_banks3,
> +		.nr_banks	= ARRAY_SIZE(exynos5515_pin_banks3),
> +		.eint_gpio_init	= exynos_eint_gpio_init,
> +		.suspend	= gs101_pinctrl_suspend,
> +		.resume		= gs101_pinctrl_resume,
> +	}, {

[Severity: High]
Is the EINT configuration for the FSYS controller in exynos5515_pin_ctrl
and exynos5515_pin_banks3 mismatched?

All three banks in exynos5515_pin_banks3 (gpf0, gpf1, and gpf2) are defined
with EXYNOS5515_PIN_BANK_EINTN, which sets eint_type to EINT_TYPE_NONE,
whereas the FSYS entry in exynos5515_pin_ctrl sets eint_gpio_init, suspend,
and resume:

drivers/pinctrl/samsung/pinctrl-exynos.c:exynos_eint_gpio_init() {
	if (!d->irq) {
		dev_err(dev, "irq number not available\n");
		return -EINVAL;
	}

	ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
					0, dev_name(dev), d);
	...
	bank = d->pin_banks;
	for (i = 0; i < d->nr_banks; ++i, ++bank) {
		if (bank->eint_type != EINT_TYPE_GPIO)
			continue;

If the FSYS controller has no GPIO interrupt in Device Tree,
exynos_eint_gpio_init() will fail probe with -EINVAL when checking d->irq.
Conversely, if FSYS does provide an interrupt, exynos_eint_gpio_init() will
register exynos_eint_gpio_irq() and then skip all three banks because their
eint_type is EINT_TYPE_NONE, leaving bank->irq_domain NULL if an interrupt
fires (and gs101_pinctrl_suspend() / gs101_pinctrl_resume() will also skip
every bank).

Should gpf0, gpf1, and gpf2 be defined as EINTG banks, or should
eint_gpio_init, suspend, and resume be omitted from the FSYS entry in
exynos5515_pin_ctrl?

[ ... ]

> +};

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261019-for-next-lucky7-pinctrl-v1-0-0f77e94c70bc@member.fsf.org?part=3