From: Ira Weiny <ira.weiny@intel.com>
To: Dave Jiang <dave.jiang@intel.com>, Fan Ni <fan.ni@samsung.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Jonathan Corbet <corbet@lwn.net>,
Andrew Morton <akpm@linux-foundation.org>,
Kees Cook <kees@kernel.org>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>
Cc: Dan Williams <dan.j.williams@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
linux-cxl@vger.kernel.org, linux-doc@vger.kernel.org,
nvdimm@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-hardening@vger.kernel.org
Subject: [PATCH v8 08/21] cxl/port: Add endpoint decoder DC mode support to sysfs
Date: Tue, 10 Dec 2024 21:42:23 -0600 [thread overview]
Message-ID: <20241210-dcd-type2-upstream-v8-8-812852504400@intel.com> (raw)
In-Reply-To: <20241210-dcd-type2-upstream-v8-0-812852504400@intel.com>
Endpoint decoder mode is used to represent the partition the decoder
points to such as ram or pmem.
Expand the mode to allow a decoder to point to a specific DC partition
(Region).
Based on an original patch by Navneet Singh.
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
Changes:
[Carpenter/smatch: fix cxl_decoder_mode_names array]
---
Documentation/ABI/testing/sysfs-bus-cxl | 25 ++++++++++++------------
drivers/cxl/core/hdm.c | 16 ++++++++++++++++
drivers/cxl/core/port.c | 16 +++++++++++-----
drivers/cxl/cxl.h | 34 +++++++++++++++++----------------
4 files changed, 58 insertions(+), 33 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
index ff3ae83477f0876c0ee2d3955d27a11fa9d16d83..8d990d702f63363879150cf523c0be6229f315e0 100644
--- a/Documentation/ABI/testing/sysfs-bus-cxl
+++ b/Documentation/ABI/testing/sysfs-bus-cxl
@@ -361,23 +361,24 @@ Description:
What: /sys/bus/cxl/devices/decoderX.Y/mode
-Date: May, 2022
-KernelVersion: v6.0
+Date: May, 2022, October 2024
+KernelVersion: v6.0, v6.13 (dcY)
Contact: linux-cxl@vger.kernel.org
Description:
(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
- translates from a host physical address range, to a device local
- address range. Device-local address ranges are further split
- into a 'ram' (volatile memory) range and 'pmem' (persistent
- memory) range. The 'mode' attribute emits one of 'ram', 'pmem',
- 'mixed', or 'none'. The 'mixed' indication is for error cases
- when a decoder straddles the volatile/persistent partition
- boundary, and 'none' indicates the decoder is not actively
- decoding, or no DPA allocation policy has been set.
+ translates from a host physical address range, to a device
+ local address range. Device-local address ranges are further
+ split into a 'ram' (volatile memory) range, 'pmem' (persistent
+ memory) range, and Dynamic Capacity (DC) ranges. The 'mode'
+ attribute emits one of 'ram', 'pmem', 'dcY', 'mixed', or
+ 'none'. The 'mixed' indication is for error cases when a
+ decoder straddles partition boundaries, and 'none' indicates
+ the decoder is not actively decoding, or no DPA allocation
+ policy has been set.
'mode' can be written, when the decoder is in the 'disabled'
- state, with either 'ram' or 'pmem' to set the boundaries for the
- next allocation.
+ state, with 'ram', 'pmem', or 'dcY' to set the boundaries for
+ the next allocation.
What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index e15241f94d17b774aa5befb37fb453af637a17ce..d0c32c3c6564df869d41030144c6d2a7c063747d 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -548,6 +548,7 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,
switch (mode) {
case CXL_DECODER_RAM:
case CXL_DECODER_PMEM:
+ case CXL_DECODER_DC0 ... CXL_DECODER_DC7:
break;
default:
dev_dbg(dev, "unsupported mode: %d\n", mode);
@@ -571,6 +572,21 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,
return -ENXIO;
}
+ if (mode >= CXL_DECODER_DC0 && mode <= CXL_DECODER_DC7) {
+ struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
+ int index;
+
+ index = dc_mode_to_region_index(mode);
+ if (!resource_size(&cxlds->dc_res[index])) {
+ dev_dbg(dev, "no available dynamic capacity\n");
+ return -ENXIO;
+ }
+ if (mds->dc_region[index].shareable) {
+ dev_err(dev, "DC region %d is shareable\n", index);
+ return -EINVAL;
+ }
+ }
+
cxled->mode = mode;
return 0;
}
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 5c0b8ead315f41c4df14918ad4dcdb269990c5dd..7459ca8eae002727405bf1077d0187bcfb579144 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -205,11 +205,17 @@ static ssize_t mode_store(struct device *dev, struct device_attribute *attr,
enum cxl_decoder_mode mode;
ssize_t rc;
- if (sysfs_streq(buf, "pmem"))
- mode = CXL_DECODER_PMEM;
- else if (sysfs_streq(buf, "ram"))
- mode = CXL_DECODER_RAM;
- else
+ for (mode = 0; mode < CXL_DECODER_MODE_MAX; mode++)
+ if (sysfs_streq(buf, cxl_decoder_mode_names[mode]))
+ break;
+
+ if (mode == CXL_DECODER_NONE ||
+ mode == CXL_DECODER_DEAD ||
+ mode == CXL_DECODER_MODE_MAX)
+ return -EINVAL;
+
+ /* Not yet supported */
+ if (mode >= CXL_DECODER_MIXED)
return -EINVAL;
rc = cxl_dpa_set_mode(cxled, mode);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 055c840b6c2856ec77162c3c5f87293f00f8d8ec..79660c87e6be533a1d55311896f9a3c5514648f8 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -389,27 +389,29 @@ enum cxl_decoder_mode {
CXL_DECODER_DC7,
CXL_DECODER_MIXED,
CXL_DECODER_DEAD,
+ CXL_DECODER_MODE_MAX,
+};
+
+static const char * const cxl_decoder_mode_names[] = {
+ [CXL_DECODER_NONE] = "none",
+ [CXL_DECODER_RAM] = "ram",
+ [CXL_DECODER_PMEM] = "pmem",
+ [CXL_DECODER_DC0] = "dc0",
+ [CXL_DECODER_DC1] = "dc1",
+ [CXL_DECODER_DC2] = "dc2",
+ [CXL_DECODER_DC3] = "dc3",
+ [CXL_DECODER_DC4] = "dc4",
+ [CXL_DECODER_DC5] = "dc5",
+ [CXL_DECODER_DC6] = "dc6",
+ [CXL_DECODER_DC7] = "dc7",
+ [CXL_DECODER_MIXED] = "mixed",
+ [CXL_DECODER_DEAD] = "dead",
};
static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode)
{
- static const char * const names[] = {
- [CXL_DECODER_NONE] = "none",
- [CXL_DECODER_RAM] = "ram",
- [CXL_DECODER_PMEM] = "pmem",
- [CXL_DECODER_DC0] = "dc0",
- [CXL_DECODER_DC1] = "dc1",
- [CXL_DECODER_DC2] = "dc2",
- [CXL_DECODER_DC3] = "dc3",
- [CXL_DECODER_DC4] = "dc4",
- [CXL_DECODER_DC5] = "dc5",
- [CXL_DECODER_DC6] = "dc6",
- [CXL_DECODER_DC7] = "dc7",
- [CXL_DECODER_MIXED] = "mixed",
- };
-
if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED)
- return names[mode];
+ return cxl_decoder_mode_names[mode];
return "mixed";
}
--
2.47.1
next prev parent reply other threads:[~2024-12-11 3:42 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-11 3:42 [PATCH v8 00/21] DCD: Add support for Dynamic Capacity Devices (DCD) Ira Weiny
2024-12-11 3:42 ` [PATCH v8 01/21] cxl/mbox: Flag " Ira Weiny
2025-01-03 22:57 ` Dan Williams
2025-01-07 1:10 ` Ira Weiny
2024-12-11 3:42 ` [PATCH v8 02/21] cxl/mem: Read dynamic capacity configuration from the device Ira Weiny
2025-01-15 2:35 ` Dan Williams
2025-01-15 13:55 ` Alejandro Lucero Palau
2025-01-15 20:48 ` Ira Weiny
2025-01-16 6:33 ` Dan Williams
2025-01-15 20:32 ` Ira Weiny
2025-01-15 22:34 ` Dan Williams
2025-01-16 10:32 ` Jonathan Cameron
2025-01-22 21:02 ` Dan Williams
2025-01-22 18:02 ` Ira Weiny
2025-01-22 21:30 ` Dan Williams
2024-12-11 3:42 ` [PATCH v8 03/21] cxl/core: Separate region mode from decoder mode Ira Weiny
2024-12-11 3:42 ` [PATCH v8 04/21] cxl/region: Add dynamic capacity decoder and region modes Ira Weiny
2024-12-11 3:42 ` [PATCH v8 05/21] cxl/hdm: Add dynamic capacity size support to endpoint decoders Ira Weiny
2024-12-11 3:42 ` [PATCH v8 06/21] cxl/cdat: Gather DSMAS data for DCD regions Ira Weiny
2024-12-11 3:42 ` [PATCH v8 07/21] cxl/mem: Expose DCD partition capabilities in sysfs Ira Weiny
2024-12-11 3:42 ` Ira Weiny [this message]
2024-12-11 3:42 ` [PATCH v8 09/21] cxl/region: Add sparse DAX region support Ira Weiny
2024-12-11 3:42 ` [PATCH v8 10/21] cxl/events: Split event msgnum configuration from irq setup Ira Weiny
2024-12-11 3:42 ` [PATCH v8 11/21] cxl/pci: Factor out interrupt policy check Ira Weiny
2024-12-11 3:42 ` [PATCH v8 12/21] cxl/mem: Configure dynamic capacity interrupts Ira Weiny
2024-12-11 3:42 ` [PATCH v8 13/21] cxl/core: Return endpoint decoder information from region search Ira Weiny
2024-12-11 3:42 ` [PATCH v8 14/21] cxl/extent: Process DCD events and realize region extents Ira Weiny
2024-12-11 3:42 ` [PATCH v8 15/21] cxl/region/extent: Expose region extent information in sysfs Ira Weiny
2024-12-11 3:42 ` [PATCH v8 16/21] dax/bus: Factor out dev dax resize logic Ira Weiny
2024-12-11 3:42 ` [PATCH v8 17/21] dax/region: Create resources on sparse DAX regions Ira Weiny
2024-12-11 3:42 ` [PATCH v8 18/21] cxl/region: Read existing extents on region creation Ira Weiny
2024-12-11 3:42 ` [PATCH v8 19/21] cxl/mem: Trace Dynamic capacity Event Record Ira Weiny
2024-12-11 3:42 ` [PATCH v8 20/21] tools/testing/cxl: Make event logs dynamic Ira Weiny
2024-12-11 3:42 ` [PATCH v8 21/21] tools/testing/cxl: Add DC Regions to mock mem data Ira Weiny
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