From: Greg KH <gregkh@linuxfoundation.org>
To: Akshay Gupta <akshay.gupta@amd.com>
Cc: linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org,
linux@roeck-us.net, arnd@arndb.de,
naveenkrishna.chatradhi@amd.com
Subject: Re: [PATCH v3 8/8] misc: amd-sbi: Add document for AMD SB IOCTL description
Date: Wed, 14 Aug 2024 12:33:32 +0200 [thread overview]
Message-ID: <2024081412-snowless-judgingly-ce90@gregkh> (raw)
In-Reply-To: <20240814095954.2359863-9-akshay.gupta@amd.com>
On Wed, Aug 14, 2024 at 09:59:53AM +0000, Akshay Gupta wrote:
> +The following IOCTL is defined:
> +
> +``#define SB_BASE_IOCTL_NR 0xF9``
> +``#define SBRMI_IOCTL_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_message)``
You only have 1 ioctl, so why are you saying that you are reserving
0-1F?
> +Data structure::
> + struct apml_message {
> + /* message ids:
> + * Mailbox Messages: 0x0 ... 0x999
> + * APML_CPUID: 0x1000
> + * APML_MCA_MSR: 0x1001
> + * APML_REG: 0x1002
> + */
> + __u32 cmd;
> + /*
> + * 8 bit data for reg read,
> + * 32 bit data in case of mailbox,
> + * up to 64 bit in case of cpuid and mca msr
> + */
> + union {
> + __u64 cpu_msr_out;
> + __u32 mb_out[2];
> + __u8 reg_out[8];
> + } data_out;
> + /*
> + * [0]...[3] mailbox 32bit input
> + * cpuid & mca msr,
> + * rmi rd/wr: reg_offset
> + * [4][5] cpuid & mca msr: thread
> + * [4] rmi reg wr: value
> + * [6] cpuid: ext function & read eax/ebx or ecx/edx
> + * [7:0] -> bits [7:4] -> ext function &
> + * bit [0] read eax/ebx or ecx/edx
> + * [7] read/write functionality
> + */
> + union {
> + __u64 cpu_msr_in;
> + __u32 mb_in[2];
> + __u8 reg_in[8];
> + } data_in;
> + /*
> + * Status code is returned in case of CPUID/MCA access
> + * Error code is returned in case of soft mailbox
> + */
> + __u32 fw_ret_code;
> + } __attribute__((packed));
This does not need to be here, pull it directly from the .h file using
kernel doc formatting please.
> +The ioctl would return a non-zero on failure; user can read errno to see
> +what happened.
That's not how the ioctl syscall works :(
> The transaction returns 0 on success.
> +
> +User space C-APIs are made available by linking against the esmi_oob_library,
> +which is provided by the E-SMS project https://www.amd.com/en/developer/e-sms.html.
> +Link: https://github.com/amd/esmi_oob_library
What is this last line for?
thanks,
greg k-h
next prev parent reply other threads:[~2024-08-14 10:33 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-14 9:59 [PATCH v3 0/8] misc: Add AMD side band interface(SBI) functionality Akshay Gupta
2024-08-14 9:59 ` [PATCH v3 1/8] hwmon/misc: amd-sbi: Move core sbrmi from hwmon to misc Akshay Gupta
2024-08-14 13:35 ` Guenter Roeck
2024-08-14 9:59 ` [PATCH v3 2/8] misc: amd-sbi: Use regmap subsystem Akshay Gupta
2024-08-14 9:59 ` [PATCH v3 3/8] misc: amd-sbi: Add support for AMD_SBI IOCTL Akshay Gupta
2024-08-14 9:59 ` [PATCH v3 4/8] misc: amd-sbi: Add support for mailbox error codes Akshay Gupta
2024-08-14 9:59 ` [PATCH v3 5/8] misc: amd-sbi: Add support for CPUID protocol Akshay Gupta
2024-08-19 10:27 ` Arnd Bergmann
2024-08-21 14:11 ` Gupta, Akshay
2024-08-14 9:59 ` [PATCH v3 6/8] misc: amd-sbi: Add support for MCA register protocol Akshay Gupta
2024-08-14 9:59 ` [PATCH v3 7/8] misc: amd-sbi: Add supoort for register xfer Akshay Gupta
2024-08-14 9:59 ` [PATCH v3 8/8] misc: amd-sbi: Add document for AMD SB IOCTL description Akshay Gupta
2024-08-14 10:33 ` Greg KH [this message]
2024-08-19 10:15 ` Gupta, Akshay
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