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From: Sohil Mehta <sohil.mehta@intel.com>
To: x86@kernel.org, Dave Hansen <dave.hansen@linux.intel.com>,
	Tony Luck <tony.luck@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Kan Liang <kan.liang@linux.intel.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Borislav Petkov <bp@alien8.de>, "H . Peter Anvin" <hpa@zytor.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>, Andy Lutomirski <luto@kernel.org>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	Fenghua Yu <fenghua.yu@intel.com>,
	Jean Delvare <jdelvare@suse.com>,
	Guenter Roeck <linux@roeck-us.net>,
	Sohil Mehta <sohil.mehta@intel.com>,
	Zhang Rui <rui.zhang@intel.com>,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org,
	linux-hwmon@vger.kernel.org
Subject: [RFC PATCH 03/15] x86/cpu/intel: Fix init_intel() checks for extended family numbers
Date: Fri, 20 Dec 2024 21:36:58 +0000	[thread overview]
Message-ID: <20241220213711.1892696-4-sohil.mehta@intel.com> (raw)
In-Reply-To: <20241220213711.1892696-1-sohil.mehta@intel.com>

X86_FEATURE_REP_GOOD is only set for family 6 processors.  Extend the
check to family numbers beyond 15.

It is uncertain whether the Pentium 4s (family 15) should set the
feature flag as well. Commit 185f3b9da24c ("x86: make intel.c have
64-bit support code") that originally set X86_FEATURE_REP_GOOD also set
the x86_cache_alignment preference for family 15 processors. The
omission of the family 15 seems intentional.

Also, the 32-bit user copy alignment preference is only set for family 6
and 15 processors. Extend the preference to family numbers beyond 15.

Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
---
 arch/x86/kernel/cpu/intel.c | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 8ded9f859a3a..f44b2e618fb3 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -449,23 +449,16 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
 	    (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
 		set_cpu_bug(c, X86_BUG_11AP);
 
-
 #ifdef CONFIG_X86_INTEL_USERCOPY
 	/*
 	 * Set up the preferred alignment for movsl bulk memory moves
+	 * Family 4 - 486: untested
+	 * Family 5 - Pentium: untested
+	 * Family 6 - PII/PIII only like movsl with 8-byte alignment
+	 * Family 15 - P4 is OK down to 8-byte alignment
 	 */
-	switch (c->x86) {
-	case 4:		/* 486: untested */
-		break;
-	case 5:		/* Old Pentia: untested */
-		break;
-	case 6:		/* PII/PIII only like movsl with 8-byte alignment */
-		movsl_mask.mask = 7;
-		break;
-	case 15:	/* P4 is OK down to 8-byte alignment */
+	if (c->x86_vfm >= INTEL_PENTIUM_PRO)
 		movsl_mask.mask = 7;
-		break;
-	}
 #endif
 
 	intel_smp_check(c);
@@ -563,7 +556,7 @@ static void init_intel(struct cpuinfo_x86 *c)
 #ifdef CONFIG_X86_64
 	if (c->x86 == 15)
 		c->x86_cache_alignment = c->x86_clflush_size * 2;
-	if (c->x86 == 6)
+	if (c->x86 == 6 || c->x86 > 15)
 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 #else
 	/*
-- 
2.43.0


  parent reply	other threads:[~2024-12-20 21:39 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-20 21:36 [RFC PATCH 00/15] Prepare for new Intel family models Sohil Mehta
2024-12-20 21:36 ` [RFC PATCH 01/15] x86/apic: Fix 32-bit APIC initialization for extended Intel families Sohil Mehta
2024-12-20 23:13   ` Dave Hansen
2024-12-23 20:40     ` Sohil Mehta
2024-12-20 21:36 ` [RFC PATCH 02/15] x86/apic: Fix smp init delay " Sohil Mehta
2024-12-20 23:20   ` Dave Hansen
2024-12-23 21:55     ` Sohil Mehta
2024-12-20 21:36 ` Sohil Mehta [this message]
2024-12-20 23:27   ` [RFC PATCH 03/15] x86/cpu/intel: Fix init_intel() checks for extended family numbers Dave Hansen
2024-12-23 23:41     ` Sohil Mehta
2024-12-20 21:36 ` [RFC PATCH 04/15] cpufreq: Fix the efficient idle check for Intel extended families Sohil Mehta
2024-12-20 21:37 ` [RFC PATCH 05/15] hwmon: Fix Intel family checks to include extended family numbers Sohil Mehta
2024-12-21 17:27   ` Guenter Roeck
2024-12-23 18:13     ` Sohil Mehta
2024-12-20 21:37 ` [RFC PATCH 06/15] x86/microcode: Update the Intel processor flag scan check Sohil Mehta
2024-12-21  9:11   ` Borislav Petkov
2024-12-23 19:52     ` Sohil Mehta
2024-12-21 15:46   ` Dave Hansen
2024-12-20 21:37 ` [RFC PATCH 07/15] x86/mtrr: Modify a x86_model check to an Intel VFM check Sohil Mehta
2024-12-20 21:37 ` [RFC PATCH 08/15] x86/cpu/intel: Replace early family 6 checks with VFM ones Sohil Mehta
2024-12-21 10:35   ` David Laight
2024-12-21 15:57     ` Dave Hansen
2024-12-21 16:48       ` David Laight
2024-12-21 18:30         ` Dave Hansen
2024-12-23 20:13       ` Sohil Mehta
2024-12-20 21:37 ` [RFC PATCH 09/15] x86/cpu/intel: Replace family 15 " Sohil Mehta
2024-12-20 21:37 ` [RFC PATCH 10/15] x86/cpu/intel: Replace family 5 model " Sohil Mehta
2024-12-20 21:37 ` [RFC PATCH 11/15] x86/pat: Replace Intel " Sohil Mehta
2024-12-20 21:37 ` [RFC PATCH 12/15] x86/acpi/cstate: Improve Intel family model checks Sohil Mehta
2024-12-20 21:37 ` [RFC PATCH 13/15] x86/cpu/intel: Bound the non-architectural constant_tsc " Sohil Mehta
2024-12-20 21:37 ` [RFC PATCH 14/15] perf/x86: Simplify p6_pmu_init() Sohil Mehta
2024-12-20 21:37 ` [RFC PATCH 15/15] perf/x86/p4: Replace Pentium 4 model checks with VFM ones Sohil Mehta
2024-12-21  0:29 ` [RFC PATCH 00/15] Prepare for new Intel family models Andrew Cooper
2024-12-23 19:43   ` Sohil Mehta

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