[PATCH v2 0/8] hwmon: (ina3221) Various improvement and add support for SQ52210

[PATCH v2 0/8] hwmon: (ina3221) Various improvement and add support for SQ52210

[Wenliang Yan]

Revised based on feedback from the previous version:

1.Adjusted the description in dt-bindings: only added a compatible string
for sq52210.

2.Modified the register read/write value conversion function, refined the
calculation logic for each register, and reduced unnecessary function
calls.

3.Restructured the patch content for easier review.

---
v1: https://lore.kernel.org/linux-hwmon/20251111080546.32421-1-wenliang202407@163.com/

Wenliang Yan (8):
  dt-bindings: hwmon: ti,ina3221: Add SQ52210
  hwmon: (ina3221) Add support for SQ52210
  hwmon: (ina3221) Pre-calculate current and power LSB
  hwmon: (ina3221) Support alert configuration
  hwmon: (ina3221) Introduce power attribute and alert characteristics
  hwmon: (ina3221) Support for writing alert limit values and modify
    the 'ina3221_read_value' function.
  hwmon: (ina3221) Support write/read functions for 'power' attribute
  hwmon: (ina3221) Modify write/read functions for 'in' and 'curr'
    attribute

 .../devicetree/bindings/hwmon/ti,ina3221.yaml |   4 +-
 Documentation/hwmon/ina3221.rst               |  24 +
 drivers/hwmon/ina3221.c                       | 520 +++++++++++++++++-
 3 files changed, 533 insertions(+), 15 deletions(-)

-- 
2.17.1

[PATCH v2 1/8] dt-bindings: hwmon: ti,ina3221: Add SQ52210

[Wenliang Yan]

Add a compatible string for sq52210. The sq52210 is forward compatible
with INA3221 and incorporates alert registers to implement four
additional alert functions, all of which require no board-level
configuration.

Signed-off-by: Wenliang Yan <wenliang202407@163.com>
---
 Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml
index 5f10f1207d69..3bdd8dfb7a36 100644
--- a/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml
+++ b/Documentation/devicetree/bindings/hwmon/ti,ina3221.yaml
@@ -12,7 +12,9 @@ maintainers:
 
 properties:
   compatible:
-    const: ti,ina3221
+    enum:
+      - silergy,sq52210
+      - ti,ina3221
 
   reg:
     maxItems: 1
-- 
2.17.1

[PATCH v2 2/8] hwmon: (ina3221) Add support for SQ52210

[Wenliang Yan]

SQ52210 is compatible with INA3221, but also includes current registers,
power registers, and registers related to alerts.

Signed-off-by: Wenliang Yan <wenliang202407@163.com>
---
 drivers/hwmon/ina3221.c | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
index 5ecc68dcf169..47ef4fe694ea 100644
--- a/drivers/hwmon/ina3221.c
+++ b/drivers/hwmon/ina3221.c
@@ -34,6 +34,17 @@
 #define INA3221_SHUNT_SUM		0x0d
 #define INA3221_CRIT_SUM		0x0e
 #define INA3221_MASK_ENABLE		0x0f
+#define SQ52210_ALERT_CONFIG	0x12
+#define SQ52210_CALIBRATION		0x14
+#define SQ52210_CURRENT1		0x15
+#define SQ52210_CURRENT2		0x16
+#define SQ52210_CURRENT3		0x17
+#define SQ52210_POWER1			0x18
+#define SQ52210_POWER2			0x19
+#define SQ52210_POWER3			0x1A
+#define SQ52210_ALERT_LIMIT1	0x1B
+#define SQ52210_ALERT_LIMIT2	0x1C
+#define SQ52210_ALERT_LIMIT3	0x1D
 
 #define INA3221_CONFIG_MODE_MASK	GENMASK(2, 0)
 #define INA3221_CONFIG_MODE_POWERDOWN	0
@@ -108,8 +119,11 @@ struct ina3221_input {
 	bool summation_disable;
 };
 
+enum ina3221_ids { ina3221, sq52210 };
+
 /**
  * struct ina3221_data - device specific information
+ * @chip: Chip type identifier
  * @pm_dev: Device pointer for pm runtime
  * @regmap: Register map of the device
  * @fields: Register fields of the device
@@ -120,6 +134,8 @@ struct ina3221_input {
  * @single_shot: running in single-shot operating mode
  */
 struct ina3221_data {
+	enum ina3221_ids chip;
+
 	struct device *pm_dev;
 	struct regmap *regmap;
 	struct regmap_field *fields[F_MAX_FIELDS];
@@ -734,6 +750,7 @@ static const struct regmap_range ina3221_yes_ranges[] = {
 	regmap_reg_range(INA3221_CONFIG, INA3221_BUS3),
 	regmap_reg_range(INA3221_SHUNT_SUM, INA3221_SHUNT_SUM),
 	regmap_reg_range(INA3221_MASK_ENABLE, INA3221_MASK_ENABLE),
+	regmap_reg_range(SQ52210_ALERT_CONFIG, SQ52210_POWER3),
 };
 
 static const struct regmap_access_table ina3221_volatile_table = {
@@ -818,13 +835,18 @@ static int ina3221_probe(struct i2c_client *client)
 	struct device *dev = &client->dev;
 	struct ina3221_data *ina;
 	struct device *hwmon_dev;
+	enum ina3221_ids chip;
 	char name[32];
 	int i, ret;
 
+	chip = (uintptr_t)i2c_get_match_data(client);
+
 	ina = devm_kzalloc(dev, sizeof(*ina), GFP_KERNEL);
 	if (!ina)
 		return -ENOMEM;
 
+	ina->chip = chip;
+
 	ina->regmap = devm_regmap_init_i2c(client, &ina3221_regmap_config);
 	if (IS_ERR(ina->regmap)) {
 		dev_err(dev, "Unable to allocate register map\n");
@@ -996,13 +1018,21 @@ static DEFINE_RUNTIME_DEV_PM_OPS(ina3221_pm, ina3221_suspend, ina3221_resume,
 				 NULL);
 
 static const struct of_device_id ina3221_of_match_table[] = {
-	{ .compatible = "ti,ina3221", },
+	{
+		.compatible = "silergy,sq52210",
+		.data = (void *)sq52210
+	},
+	{
+		.compatible = "ti,ina3221",
+		.data = (void *)ina3221
+	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ina3221_of_match_table);
 
 static const struct i2c_device_id ina3221_ids[] = {
-	{ "ina3221" },
+	{ "ina3221", ina3221 },
+	{ "sq52210", sq52210 },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(i2c, ina3221_ids);
-- 
2.17.1

[PATCH v2 3/8] hwmon: (ina3221) Pre-calculate current and power LSB

[Wenliang Yan]

The LSB for current and power can be pre-calculated for data read/write
operations. The current LSB is determined by the calibration value and
shunt resistor value, with the calibration value fixed within the driver.
The power LSB can be derived from the current LSB.

Signed-off-by: Wenliang Yan <wenliang202407@163.com>
---
 drivers/hwmon/ina3221.c | 85 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
index 47ef4fe694ea..b5fa984a5a25 100644
--- a/drivers/hwmon/ina3221.c
+++ b/drivers/hwmon/ina3221.c
@@ -67,6 +67,7 @@
 
 #define INA3221_CONFIG_DEFAULT		0x7127
 #define INA3221_RSHUNT_DEFAULT		10000
+#define SQ52210_SHUNT_LSB			40000000	/* pV/LSB */
 
 enum ina3221_fields {
 	/* Configuration */
@@ -121,8 +122,16 @@ struct ina3221_input {
 
 enum ina3221_ids { ina3221, sq52210 };
 
+struct ina3221_config {
+	bool has_current;	/* chip has internal current reg */
+	bool has_power;		/* chip has internal power reg */
+	int calibration_value;	/* calculate current_lsb */
+	int power_lsb_factor;
+};
+
 /**
  * struct ina3221_data - device specific information
+ * @config:	Used to store characteristics of different chips
  * @chip: Chip type identifier
  * @pm_dev: Device pointer for pm runtime
  * @regmap: Register map of the device
@@ -131,9 +140,12 @@ enum ina3221_ids { ina3221, sq52210 };
  * @reg_config: Register value of INA3221_CONFIG
  * @summation_shunt_resistor: equivalent shunt resistor value for summation
  * @summation_channel_control: Value written to SCC field in INA3221_MASK_ENABLE
+ * @current_lsb_uA: The value of one LSB corresponding to the current register
+ * @power_lsb_uW: The value of one LSB corresponding to the power register
  * @single_shot: running in single-shot operating mode
  */
 struct ina3221_data {
+	const struct ina3221_config *config;
 	enum ina3221_ids chip;
 
 	struct device *pm_dev;
@@ -143,10 +155,30 @@ struct ina3221_data {
 	u32 reg_config;
 	int summation_shunt_resistor;
 	u32 summation_channel_control;
+	long current_lsb_uA;
+	long power_lsb_uW;
 
 	bool single_shot;
 };
 
+static const struct ina3221_config ina3221_config[] = {
+	[ina3221] = {
+		.has_current = false,
+		.has_power = false,
+	},
+	[sq52210] = {
+		.has_current = true,
+		.has_power = true,
+		/*
+		 * With this default value configuration,
+		 * the following formula can be obtained:
+		 * Current_LSB = Shunt_LSB / Rshunt
+		 */
+		.calibration_value = 256,
+		.power_lsb_factor = 20,
+	},
+};
+
 static inline bool ina3221_is_enabled(struct ina3221_data *ina, int channel)
 {
 	/* Summation channel checks shunt resistor values */
@@ -697,6 +729,25 @@ static const struct hwmon_chip_info ina3221_chip_info = {
 };
 
 /* Extra attribute groups */
+
+/*
+ * Calculate the value corresponding to one LSB of the current and
+ * power registers.
+ * formula : Current_LSB = Shunt_LSB / Rshunt
+ *           Power_LSB = power_lsb_factor * Current_LSB
+ */
+static int ina3221_set_shunt(struct ina3221_data *ina, unsigned long val)
+{
+	if (!val || val > SQ52210_SHUNT_LSB)
+		return -EINVAL;
+
+	ina->current_lsb_uA = DIV_ROUND_CLOSEST(SQ52210_SHUNT_LSB, val);
+	ina->power_lsb_uW = ina->config->power_lsb_factor *
+			    ina->current_lsb_uA;
+
+	return 0;
+}
+
 static ssize_t ina3221_shunt_show(struct device *dev,
 				  struct device_attribute *attr, char *buf)
 {
@@ -730,6 +781,17 @@ static ssize_t ina3221_shunt_store(struct device *dev,
 	/* Update summation_shunt_resistor for summation channel */
 	ina->summation_shunt_resistor = ina3221_summation_shunt_resistor(ina);
 
+	/*
+	 * The current and power registers can only be used when
+	 * all enabled channels have identical shunt resistors
+	 */
+	if (ina->summation_shunt_resistor) {
+		if (ina->config->has_current) {
+			ret = ina3221_set_shunt(ina, val);
+			if (ret < 0)
+				return ret;
+		}
+	}
 	return count;
 }
 
@@ -846,6 +908,7 @@ static int ina3221_probe(struct i2c_client *client)
 		return -ENOMEM;
 
 	ina->chip = chip;
+	ina->config = &ina3221_config[chip];
 
 	ina->regmap = devm_regmap_init_i2c(client, &ina3221_regmap_config);
 	if (IS_ERR(ina->regmap)) {
@@ -892,6 +955,16 @@ static int ina3221_probe(struct i2c_client *client)
 			ina->summation_channel_control |= BIT(14 - i);
 	}
 
+	/*
+	 * The current and power registers can only be used when
+	 * all enabled channels have identical shunt resistors
+	 */
+	if (ina->summation_shunt_resistor) {
+		ret = ina3221_set_shunt(ina, ina->summation_shunt_resistor);
+		if (ret < 0)
+			return ret;
+	}
+
 	ina->pm_dev = dev;
 	dev_set_drvdata(dev, ina);
 
@@ -1009,6 +1082,18 @@ static int ina3221_resume(struct device *dev)
 			dev_err(dev, "Unable to control summation channel\n");
 			return ret;
 		}
+		/*
+		 * The calibration register can only be enabled when all
+		 * shunt resistor values are identical.
+		 */
+		if (ina->config->has_current) {
+			ret = regmap_write(ina->regmap, SQ52210_CALIBRATION,
+						ina->config->calibration_value);
+			if (ret) {
+				dev_err(dev, "Unable to set calibration value\n");
+				return ret;
+			}
+		}
 	}
 
 	return 0;
-- 
2.17.1

[PATCH v2 4/8] hwmon: (ina3221) Support alert configuration

[Wenliang Yan]

Add alert configuration during chip initialization.

Signed-off-by: Wenliang Yan <wenliang202407@163.com>
---
 drivers/hwmon/ina3221.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
index b5fa984a5a25..8ea75f407055 100644
--- a/drivers/hwmon/ina3221.c
+++ b/drivers/hwmon/ina3221.c
@@ -65,6 +65,8 @@
 
 #define INA3221_MASK_ENABLE_SCC_MASK	GENMASK(14, 12)
 
+#define SQ52210_ALERT_CONFIG_MASK	GENMASK(15, 4)
+
 #define INA3221_CONFIG_DEFAULT		0x7127
 #define INA3221_RSHUNT_DEFAULT		10000
 #define SQ52210_SHUNT_LSB			40000000	/* pV/LSB */
@@ -123,6 +125,7 @@ struct ina3221_input {
 enum ina3221_ids { ina3221, sq52210 };
 
 struct ina3221_config {
+	bool has_alerts;	/* chip supports alerts and limits */
 	bool has_current;	/* chip has internal current reg */
 	bool has_power;		/* chip has internal power reg */
 	int calibration_value;	/* calculate current_lsb */
@@ -140,6 +143,7 @@ struct ina3221_config {
  * @reg_config: Register value of INA3221_CONFIG
  * @summation_shunt_resistor: equivalent shunt resistor value for summation
  * @summation_channel_control: Value written to SCC field in INA3221_MASK_ENABLE
+ * @alert_type_select: Used to store the alert trigger type
  * @current_lsb_uA: The value of one LSB corresponding to the current register
  * @power_lsb_uW: The value of one LSB corresponding to the power register
  * @single_shot: running in single-shot operating mode
@@ -155,6 +159,7 @@ struct ina3221_data {
 	u32 reg_config;
 	int summation_shunt_resistor;
 	u32 summation_channel_control;
+	u32 alert_type_select;
 	long current_lsb_uA;
 	long power_lsb_uW;
 
@@ -163,10 +168,12 @@ struct ina3221_data {
 
 static const struct ina3221_config ina3221_config[] = {
 	[ina3221] = {
+		.has_alerts = false,
 		.has_current = false,
 		.has_power = false,
 	},
 	[sq52210] = {
+		.has_alerts = true,
 		.has_current = true,
 		.has_power = true,
 		/*
@@ -780,7 +787,6 @@ static ssize_t ina3221_shunt_store(struct device *dev,
 
 	/* Update summation_shunt_resistor for summation channel */
 	ina->summation_shunt_resistor = ina3221_summation_shunt_resistor(ina);
-
 	/*
 	 * The current and power registers can only be used when
 	 * all enabled channels have identical shunt resistors
@@ -1096,6 +1102,17 @@ static int ina3221_resume(struct device *dev)
 		}
 	}
 
+	/* Restore alert config register value to hardware */
+	if (ina->config->has_alerts) {
+		ret = regmap_update_bits(ina->regmap, SQ52210_ALERT_CONFIG,
+					 SQ52210_ALERT_CONFIG_MASK,
+					 ina->alert_type_select);
+		if (ret) {
+			dev_err(dev, "Unable to select alert type\n");
+			return ret;
+		}
+	}
+
 	return 0;
 }
 
-- 
2.17.1

[PATCH v2 5/8] hwmon: (ina3221) Introduce power attribute and alert characteristics

[Wenliang Yan]

SQ52210 has built-in current and power sensors as well as multiple
alert functions. Add power attributes and different critical
characteristics in hwmon to report the corresponding data.

Signed-off-by: Wenliang Yan <wenliang202407@163.com>
---
 Documentation/hwmon/ina3221.rst | 24 ++++++++++++++
 drivers/hwmon/ina3221.c         | 57 ++++++++++++++++++++++++++++++---
 2 files changed, 77 insertions(+), 4 deletions(-)

diff --git a/Documentation/hwmon/ina3221.rst b/Documentation/hwmon/ina3221.rst
index 8c12c54d2c24..224c6cf735ed 100644
--- a/Documentation/hwmon/ina3221.rst
+++ b/Documentation/hwmon/ina3221.rst
@@ -13,6 +13,13 @@ Supported chips:
 
 	       https://www.ti.com/
 
+  * Silergy SQ52210
+
+    Prefix: 'SQ52210'
+
+    Addresses: I2C 0x40 - 0x43
+
+
 Author: Andrew F. Davis <afd@ti.com>
 
 Description
@@ -23,6 +30,9 @@ side of up to three D.C. power supplies. The INA3221 monitors both shunt drop
 and supply voltage, with programmable conversion times and averaging, current
 and power are calculated host-side from these.
 
+The SQ52210 is a mostly compatible chip from Silergy. It incorporates internal
+current and power registers, and provides an extra configurable alert function.
+
 Sysfs entries
 -------------
 
@@ -72,3 +82,17 @@ update_interval         Data conversion time in millisecond, following:
                         Note that setting update_interval to 0ms sets both BC
                         and SC to 140 us (minimum conversion time).
 ======================= =======================================================
+
+Additional sysfs entries for sq52210
+-------------------------------------
+
+======================= =======================================================
+in[123]_crit            Critical high bus voltage
+in[123]_crit_alarm      Bus voltage critical high alarm
+in[123]_lcrit           Critical low bus voltage
+in[123]_lcrit_alarm     Bus voltage critical low alarm
+curr[123]_lcrit         Critical low current
+curr[123]_lcrit_alarm   Current critical low alarm
+power[123]_input        Current for channels 1, 2, and 3 respectively
+power[123]_crit         Critical high power
+power[123]_crit_alarm   Power critical high alarm
diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
index 8ea75f407055..1d589d402b52 100644
--- a/drivers/hwmon/ina3221.c
+++ b/drivers/hwmon/ina3221.c
@@ -645,6 +645,8 @@ static umode_t ina3221_is_visible(const void *drvdata,
 {
 	const struct ina3221_data *ina = drvdata;
 	const struct ina3221_input *input = NULL;
+	bool has_alerts = ina->config->has_alerts;
+	bool has_power = ina->config->has_power;
 
 	switch (type) {
 	case hwmon_chip:
@@ -672,6 +674,16 @@ static umode_t ina3221_is_visible(const void *drvdata,
 			return 0444;
 		case hwmon_in_enable:
 			return 0644;
+		case hwmon_in_crit:
+		case hwmon_in_lcrit:
+			if (has_alerts)
+				return 0644;
+			return 0;
+		case hwmon_in_crit_alarm:
+		case hwmon_in_lcrit_alarm:
+			if (has_alerts)
+				return 0444;
+			return 0;
 		default:
 			return 0;
 		}
@@ -684,6 +696,31 @@ static umode_t ina3221_is_visible(const void *drvdata,
 		case hwmon_curr_crit:
 		case hwmon_curr_max:
 			return 0644;
+		case hwmon_curr_lcrit:
+			if (has_alerts)
+				return 0644;
+			return 0;
+		case hwmon_curr_lcrit_alarm:
+			if (has_alerts)
+				return 0444;
+			return 0;
+		default:
+			return 0;
+		}
+	case hwmon_power:
+		switch (attr) {
+		case hwmon_power_input:
+			if (has_power)
+				return 0444;
+			return 0;
+		case hwmon_power_crit_alarm:
+			if (has_alerts)
+				return 0444;
+			return 0;
+		case hwmon_power_crit:
+			if (has_alerts)
+				return 0644;
+			return 0;
 		default:
 			return 0;
 		}
@@ -694,7 +731,14 @@ static umode_t ina3221_is_visible(const void *drvdata,
 
 #define INA3221_HWMON_CURR_CONFIG (HWMON_C_INPUT | \
 				   HWMON_C_CRIT | HWMON_C_CRIT_ALARM | \
-				   HWMON_C_MAX | HWMON_C_MAX_ALARM)
+				   HWMON_C_MAX | HWMON_C_MAX_ALARM | \
+				   HWMON_C_LCRIT | HWMON_C_LCRIT_ALARM)
+#define SQ52210_HWMON_POWER_CONFIG (HWMON_P_INPUT | \
+				   HWMON_P_CRIT | HWMON_P_CRIT_ALARM)
+#define SQ52210_HWMON_BUS_CONFIG (HWMON_I_INPUT | \
+				   HWMON_I_ENABLE | HWMON_I_LABEL | \
+				   HWMON_I_LCRIT_ALARM | HWMON_I_LCRIT |\
+				   HWMON_I_CRIT_ALARM | HWMON_I_CRIT)
 
 static const struct hwmon_channel_info * const ina3221_info[] = {
 	HWMON_CHANNEL_INFO(chip,
@@ -704,9 +748,9 @@ static const struct hwmon_channel_info * const ina3221_info[] = {
 			   /* 0: dummy, skipped in is_visible */
 			   HWMON_I_INPUT,
 			   /* 1-3: input voltage Channels */
-			   HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL,
-			   HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL,
-			   HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL,
+			   SQ52210_HWMON_BUS_CONFIG,
+			   SQ52210_HWMON_BUS_CONFIG,
+			   SQ52210_HWMON_BUS_CONFIG,
 			   /* 4-6: shunt voltage Channels */
 			   HWMON_I_INPUT,
 			   HWMON_I_INPUT,
@@ -720,6 +764,11 @@ static const struct hwmon_channel_info * const ina3221_info[] = {
 			   INA3221_HWMON_CURR_CONFIG,
 			   /* 4: summation of current channels */
 			   HWMON_C_INPUT | HWMON_C_CRIT | HWMON_C_CRIT_ALARM),
+	HWMON_CHANNEL_INFO(power,
+			   /* 1-3: power channels*/
+			   SQ52210_HWMON_POWER_CONFIG,
+			   SQ52210_HWMON_POWER_CONFIG,
+			   SQ52210_HWMON_POWER_CONFIG),
 	NULL
 };
 
-- 
2.17.1

[PATCH v2 6/8] hwmon: (ina3221) Support for writing alert limit values and modify the 'ina3221_read_value' function.

[Wenliang Yan]

SQ52210 adds power, current, and limit registers. The ina3221_read_value
function has been refactored to adapt to the new register data reading
format.

Each channel supports four new alert trigger modes, but only one trigger
mode can be active at any given time. Alert values are stored in the same
register. The sq52210_alert_limit_write function has been added to write
alert threshold values and configure alert source type.

Signed-off-by: Wenliang Yan <wenliang202407@163.com>
---
 drivers/hwmon/ina3221.c | 150 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 147 insertions(+), 3 deletions(-)

diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
index 1d589d402b52..9a25a1b40856 100644
--- a/drivers/hwmon/ina3221.c
+++ b/drivers/hwmon/ina3221.c
@@ -66,6 +66,14 @@
 #define INA3221_MASK_ENABLE_SCC_MASK	GENMASK(14, 12)
 
 #define SQ52210_ALERT_CONFIG_MASK	GENMASK(15, 4)
+#define SQ52210_MASK_ALERT_CHANNEL1 (BIT(15) | BIT(12) | BIT(9) | BIT(6))
+#define SQ52210_MASK_ALERT_CHANNEL2 (BIT(14) | BIT(11) | BIT(8) | BIT(5))
+#define SQ52210_MASK_ALERT_CHANNEL3 (BIT(13) | BIT(10) | BIT(7) | BIT(4))
+
+#define SQ52210_ALERT_ALL_SUL_MASK	(BIT(15) | BIT(14) | BIT(13))
+#define SQ52210_ALERT_ALL_BOL_MASK	(BIT(12) | BIT(11) | BIT(10))
+#define SQ52210_ALERT_ALL_BUL_MASK	(BIT(9) | BIT(8) | BIT(7))
+#define SQ52210_ALERT_ALL_POL_MASK	(BIT(6) | BIT(5) | BIT(4))
 
 #define INA3221_CONFIG_DEFAULT		0x7127
 #define INA3221_RSHUNT_DEFAULT		10000
@@ -272,6 +280,18 @@ static inline int ina3221_wait_for_data(struct ina3221_data *ina)
 					      cvrf, cvrf, wait, wait * 2);
 }
 
+static const u32 alert_groups[] = {
+	SQ52210_MASK_ALERT_CHANNEL1,
+	SQ52210_MASK_ALERT_CHANNEL2,
+	SQ52210_MASK_ALERT_CHANNEL3,
+};
+
+static const u8 limit_regs[] = {
+	SQ52210_ALERT_LIMIT1,
+	SQ52210_ALERT_LIMIT2,
+	SQ52210_ALERT_LIMIT3,
+};
+
 static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
 			      int *val)
 {
@@ -284,13 +304,55 @@ static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
 
 	/*
 	 * Shunt Voltage Sum register has 14-bit value with 1-bit shift
+	 * Current registers have 15-bit value
+	 * Power registers have 16-bit value
+	 * ALERT_LIMIT registers have 16-bit value with 3-bit shift
 	 * Other Shunt Voltage registers have 12 bits with 3-bit shift
 	 */
-	if (reg == INA3221_SHUNT_SUM || reg == INA3221_CRIT_SUM)
+	switch (reg) {
+	case INA3221_SHUNT_SUM:
+	case INA3221_CRIT_SUM:
 		*val = sign_extend32(regval >> 1, 14);
-	else
+		break;
+	case SQ52210_CURRENT1:
+	case SQ52210_CURRENT2:
+	case SQ52210_CURRENT3:
+		*val = sign_extend32(regval, 15);
+		break;
+	case SQ52210_POWER1:
+	case SQ52210_POWER2:
+	case SQ52210_POWER3:
+		*val = regval;
+		break;
+	case INA3221_BUS1:
+	case INA3221_BUS2:
+	case INA3221_BUS3:
+	case INA3221_SHUNT1:
+	case INA3221_SHUNT2:
+	case INA3221_SHUNT3:
+	case INA3221_WARN1:
+	case INA3221_WARN2:
+	case INA3221_WARN3:
+	case INA3221_CRIT1:
+	case INA3221_CRIT2:
+	case INA3221_CRIT3:
 		*val = sign_extend32(regval >> 3, 12);
-
+		break;
+	case SQ52210_ALERT_LIMIT1:
+	case SQ52210_ALERT_LIMIT2:
+	case SQ52210_ALERT_LIMIT3:
+		if (ina->alert_type_select & SQ52210_ALERT_ALL_SUL_MASK)
+			*val = sign_extend32(regval, 15);
+		else if (ina->alert_type_select & (SQ52210_ALERT_ALL_BOL_MASK
+					| SQ52210_ALERT_ALL_BUL_MASK))
+			*val = regval >> 3;
+		else if (ina->alert_type_select & SQ52210_ALERT_ALL_POL_MASK)
+			*val = regval;
+		break;
+	default:
+		*val = 0;
+		return -EOPNOTSUPP;
+	};
 	return 0;
 }
 
@@ -443,6 +505,88 @@ static int ina3221_read_curr(struct device *dev, u32 attr,
 	}
 }
 
+static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, int channel, long val)
+{
+	struct regmap *regmap = ina->regmap;
+	int item = channel % INA3221_NUM_CHANNELS;
+	u8 limit_reg;
+	u32 alert_group, alert_mask = 0;
+	int regval = 0;
+	int ret;
+
+	if (item >= ARRAY_SIZE(alert_groups) || val < 0)
+		return -EINVAL;
+
+	alert_group = alert_groups[item];
+	limit_reg = limit_regs[item];
+
+	/* Clear alerts for this channel group first */
+	ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0);
+	if (ret)
+		return ret;
+
+	/* Determine alert type and calculate register value */
+	switch (attr) {
+	/*
+	 * The alert warning logic is implemented by comparing the limit register values
+	 * with the corresponding alert source register values. Since the current register
+	 * is a 15-bit signed register and the power register is a 16-bit unsigned
+	 * register, but the lower 3 bits of the limit register default to 0, the lower
+	 * 3 bits will be forced to 0 when setting SUL and POL warning values.
+	 * Formula to convert register value:
+	 *     bus_voltage: (regval / 8mV) << 3
+	 *     current: (regval / current_lsb) & 0xfff8
+	 *     power: (regval / current_lsb) & 0xfff8
+	 */
+	case hwmon_curr_lcrit:
+		/* SUL: Shunt Under Limit - BIT(15), BIT(14), BIT(13) */
+		alert_mask = BIT(15 - item);
+		/* Current Register, signed register, result in mA */
+		regval = DIV_ROUND_CLOSEST(val * 1000, ina->current_lsb_uA) & 0xfff8;
+		regval = clamp_val(regval, -32760, 32760);
+		break;
+	case hwmon_in_crit:
+		/* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */
+		alert_mask = BIT(12 - item);
+		/* Bus Register, signed register, result in mV */
+		regval = clamp_val(val, -32760, 32760);
+		break;
+	case hwmon_in_lcrit:
+		/* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */
+		alert_mask = BIT(9 - item);
+		/* Bus Register, signed register, result in mV */
+		regval = clamp_val(val, -32760, 32760);
+		break;
+	case hwmon_power_crit:
+		/* POL: Power Over Limit - BIT(6), BIT(5), BIT(4) */
+		alert_mask = BIT(6 - item);
+		/* Power Register, unsigned register, result in mW */
+		regval = DIV_ROUND_CLOSEST(val * 1000, ina->power_lsb_uW) & 0xfff8;
+		regval = clamp_val(regval, 0, 65528);
+		break;
+	default:
+		/* For unsupported attributes, just clear the configuration */
+		ina->alert_type_select &= ~alert_group;
+		return -EOPNOTSUPP;
+	}
+
+	/* Write limit register value */
+	ret = regmap_write(regmap, limit_reg, regval);
+	if (ret)
+		return ret;
+
+	/* Update alert configuration if limit value is non-zero */
+	if (regval) {
+		ina->alert_type_select = (ina->alert_type_select & ~alert_group) | alert_mask;
+		ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG,
+					alert_group, alert_mask);
+	} else {
+		ina->alert_type_select &= ~alert_group;
+	}
+
+	return ret;
+}
+
 static int ina3221_write_chip(struct device *dev, u32 attr, long val)
 {
 	struct ina3221_data *ina = dev_get_drvdata(dev);
-- 
2.17.1

[PATCH v2 7/8] hwmon: (ina3221) Support write/read functions for 'power' attribute

[Wenliang Yan]

SQ52210 adds power attributes to report power data and implements
corresponding read/write functions for this purpose. This includes
reading power values, reading alert thresholds, reading alert
trigger status, and writing alert thresholds.

Signed-off-by: Wenliang Yan <wenliang202407@163.com>
---
 drivers/hwmon/ina3221.c | 79 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
index 9a25a1b40856..197fc3a468e4 100644
--- a/drivers/hwmon/ina3221.c
+++ b/drivers/hwmon/ina3221.c
@@ -92,6 +92,9 @@ enum ina3221_fields {
 	/* Alert Flags: SF is the summation-alert flag */
 	F_SF, F_CF3, F_CF2, F_CF1,
 
+	/* Alert Flags: AFF is the alert function flag */
+	F_AFF3, F_AFF2, F_AFF1,
+
 	/* sentinel */
 	F_MAX_FIELDS
 };
@@ -107,6 +110,10 @@ static const struct reg_field ina3221_reg_fields[] = {
 	[F_CF3] = REG_FIELD(INA3221_MASK_ENABLE, 7, 7),
 	[F_CF2] = REG_FIELD(INA3221_MASK_ENABLE, 8, 8),
 	[F_CF1] = REG_FIELD(INA3221_MASK_ENABLE, 9, 9),
+
+	[F_AFF3] = REG_FIELD(SQ52210_ALERT_CONFIG, 1, 1),
+	[F_AFF2] = REG_FIELD(SQ52210_ALERT_CONFIG, 2, 2),
+	[F_AFF1] = REG_FIELD(SQ52210_ALERT_CONFIG, 3, 3),
 };
 
 enum ina3221_channels {
@@ -505,6 +512,60 @@ static int ina3221_read_curr(struct device *dev, u32 attr,
 	}
 }
 
+static const u8 ina3221_power_reg[][INA3221_NUM_CHANNELS] = {
+	[hwmon_power_input] = { SQ52210_POWER1, SQ52210_POWER2, SQ52210_POWER3 },
+	[hwmon_power_crit] = { SQ52210_ALERT_LIMIT1, SQ52210_ALERT_LIMIT2,
+						SQ52210_ALERT_LIMIT3 },
+	[hwmon_power_crit_alarm] = { F_AFF1, F_AFF2, F_AFF3 },
+};
+
+static int ina3221_read_power(struct device *dev, u32 attr, int channel, long *val)
+{
+	struct ina3221_data *ina = dev_get_drvdata(dev);
+	u8 reg = ina3221_power_reg[attr][channel];
+	int regval, ret;
+
+	switch (attr) {
+	case hwmon_power_input:
+		if (!ina3221_is_enabled(ina, channel))
+			return -ENODATA;
+
+		/* Write CONFIG register to trigger a single-shot measurement */
+		if (ina->single_shot) {
+			regmap_write(ina->regmap, INA3221_CONFIG,
+				     ina->reg_config);
+
+			ret = ina3221_wait_for_data(ina);
+			if (ret)
+				return ret;
+		}
+
+		fallthrough;
+	case hwmon_power_crit:
+		ret = ina3221_read_value(ina, reg, &regval);
+		if (ret)
+			return ret;
+		/* Return power in mW */
+		*val = DIV_ROUND_CLOSEST(regval * ina->power_lsb_uW, 1000);
+		return 0;
+	case hwmon_power_crit_alarm:
+		/* No actual register read if channel is disabled */
+		if (!ina3221_is_enabled(ina, channel)) {
+			/* Return 0 for alert flags */
+			*val = 0;
+			return 0;
+		}
+
+		ret = regmap_field_read(ina->fields[reg], &regval);
+		if (ret)
+			return ret;
+		*val = regval;
+		return 0;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
 static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, int channel, long val)
 {
 	struct regmap *regmap = ina->regmap;
@@ -723,6 +784,18 @@ static int ina3221_write_enable(struct device *dev, int channel, bool enable)
 	return ret;
 }
 
+static int ina3221_write_power(struct device *dev, u32 attr, int channel, long val)
+{
+	struct ina3221_data *ina = dev_get_drvdata(dev);
+
+	switch (attr) {
+	case hwmon_power_crit:
+		return sq52210_alert_limit_write(ina, attr, channel, val);
+	default:
+		return 0;
+	}
+}
+
 static int ina3221_read(struct device *dev, enum hwmon_sensor_types type,
 			u32 attr, int channel, long *val)
 {
@@ -739,6 +812,9 @@ static int ina3221_read(struct device *dev, enum hwmon_sensor_types type,
 	case hwmon_curr:
 		ret = ina3221_read_curr(dev, attr, channel, val);
 		break;
+	case hwmon_power:
+		ret = ina3221_read_power(dev, attr, channel, val);
+		break;
 	default:
 		ret = -EOPNOTSUPP;
 		break;
@@ -762,6 +838,9 @@ static int ina3221_write(struct device *dev, enum hwmon_sensor_types type,
 	case hwmon_curr:
 		ret = ina3221_write_curr(dev, attr, channel, val);
 		break;
+	case hwmon_power:
+		ret = ina3221_write_power(dev, attr, channel, val);
+		break;
 	default:
 		ret = -EOPNOTSUPP;
 		break;
-- 
2.17.1

[PATCH v2 8/8] hwmon: (ina3221) Modify write/read functions for 'in' and 'curr' attribute

[Wenliang Yan]

Modified the relevant read/write functions for 'in' and 'curr' attributes,
adding support for crit, lcrit, crit_alarm, and lcrit_alarm features.

Signed-off-by: Wenliang Yan <wenliang202407@163.com>
---
 drivers/hwmon/ina3221.c | 96 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 92 insertions(+), 4 deletions(-)

diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
index 197fc3a468e4..2f05ee6c72a9 100644
--- a/drivers/hwmon/ina3221.c
+++ b/drivers/hwmon/ina3221.c
@@ -373,6 +373,12 @@ static const u8 ina3221_in_reg[] = {
 	INA3221_SHUNT_SUM,
 };
 
+static const u8 alert_flag[] = {
+	F_AFF1,
+	F_AFF2,
+	F_AFF3,
+};
+
 static int ina3221_read_chip(struct device *dev, u32 attr, long *val)
 {
 	struct ina3221_data *ina = dev_get_drvdata(dev);
@@ -435,6 +441,38 @@ static int ina3221_read_in(struct device *dev, u32 attr, int channel, long *val)
 	case hwmon_in_enable:
 		*val = ina3221_is_enabled(ina, channel);
 		return 0;
+	case hwmon_in_crit:
+	case hwmon_in_lcrit:
+		if (!ina3221_is_enabled(ina, channel))
+			return -ENODATA;
+
+		if (channel >= INA3221_NUM_CHANNELS)
+			return -EOPNOTSUPP;
+
+		reg = limit_regs[channel];
+		ret = ina3221_read_value(ina, reg, &regval);
+		if (ret)
+			return ret;
+		/*
+		 * Scale of bus voltage (mV): LSB is 8mV
+		 */
+		*val = regval * 8;
+		return 0;
+	case hwmon_in_crit_alarm:
+	case hwmon_in_lcrit_alarm:
+		/* No actual register read if channel is disabled */
+		if (!ina3221_is_enabled(ina, channel)) {
+			/* Return 0 for alert flags */
+			*val = 0;
+			return 0;
+		}
+
+		reg = alert_flag[channel];
+		ret = regmap_field_read(ina->fields[reg], &regval);
+		if (ret)
+			return ret;
+		*val = regval;
+		return 0;
 	default:
 		return -EOPNOTSUPP;
 	}
@@ -494,6 +532,25 @@ static int ina3221_read_curr(struct device *dev, u32 attr,
 		/* Return current in mA */
 		*val = DIV_ROUND_CLOSEST(voltage_nv, resistance_uo);
 		return 0;
+	case hwmon_curr_lcrit:
+		if (!resistance_uo)
+			return -ENODATA;
+
+		if (channel >= INA3221_NUM_CHANNELS)
+			return -EOPNOTSUPP;
+
+		reg = limit_regs[channel];
+		ret = ina3221_read_value(ina, reg, &regval);
+		if (ret)
+			return ret;
+
+		/* Return current in mA */
+		*val = DIV_ROUND_CLOSEST(regval * ina->current_lsb_uA, 1000);
+		return 0;
+	case hwmon_curr_lcrit_alarm:
+		reg = alert_flag[channel];
+
+		fallthrough;
 	case hwmon_curr_crit_alarm:
 	case hwmon_curr_max_alarm:
 		/* No actual register read if channel is disabled */
@@ -690,10 +747,9 @@ static int ina3221_write_chip(struct device *dev, u32 attr, long val)
 	}
 }
 
-static int ina3221_write_curr(struct device *dev, u32 attr,
-			      int channel, long val)
+static int ina3221_write_curr_shunt(struct ina3221_data *ina, u32 attr,
+				int channel, long val)
 {
-	struct ina3221_data *ina = dev_get_drvdata(dev);
 	struct ina3221_input *input = ina->inputs;
 	u8 reg = ina3221_curr_reg[attr][channel];
 	int resistance_uo, current_ma, voltage_uv;
@@ -736,6 +792,22 @@ static int ina3221_write_curr(struct device *dev, u32 attr,
 	return regmap_write(ina->regmap, reg, regval);
 }
 
+static int ina3221_write_curr(struct device *dev, u32 attr,
+			      int channel, long val)
+{
+	struct ina3221_data *ina = dev_get_drvdata(dev);
+
+	switch (attr) {
+	case hwmon_curr_crit:
+	case hwmon_curr_max:
+		return ina3221_write_curr_shunt(ina, attr, channel, val);
+	case hwmon_curr_lcrit:
+		return sq52210_alert_limit_write(ina, attr, channel, val);
+	default:
+		return 0;
+	}
+}
+
 static int ina3221_write_enable(struct device *dev, int channel, bool enable)
 {
 	struct ina3221_data *ina = dev_get_drvdata(dev);
@@ -784,6 +856,22 @@ static int ina3221_write_enable(struct device *dev, int channel, bool enable)
 	return ret;
 }
 
+static int ina3221_write_in(struct device *dev, u32 attr, int channel, long val)
+{
+	struct ina3221_data *ina = dev_get_drvdata(dev);
+
+	switch (attr) {
+	case hwmon_in_lcrit:
+		return sq52210_alert_limit_write(ina, attr, channel, val);
+	case hwmon_in_crit:
+		return sq52210_alert_limit_write(ina, attr, channel, val);
+	case hwmon_in_enable:
+		return ina3221_write_enable(dev, channel, val);
+	default:
+		return 0;
+	}
+}
+
 static int ina3221_write_power(struct device *dev, u32 attr, int channel, long val)
 {
 	struct ina3221_data *ina = dev_get_drvdata(dev);
@@ -833,7 +921,7 @@ static int ina3221_write(struct device *dev, enum hwmon_sensor_types type,
 		break;
 	case hwmon_in:
 		/* 0-align channel ID */
-		ret = ina3221_write_enable(dev, channel - 1, val);
+		ret = ina3221_write_in(dev, attr, channel - 1, val);
 		break;
 	case hwmon_curr:
 		ret = ina3221_write_curr(dev, attr, channel, val);
-- 
2.17.1

Re: [PATCH v2 6/8] hwmon: (ina3221) Support for writing alert limit values and modify the 'ina3221_read_value' function.

[kernel test robot]

Hi Wenliang,

kernel test robot noticed the following build errors:

[auto build test ERROR on groeck-staging/hwmon-next]
[also build test ERROR on robh/for-next linus/master v6.18-rc6 next-20251118]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Wenliang-Yan/dt-bindings-hwmon-ti-ina3221-Add-SQ52210/20251118-205717
base:   https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git hwmon-next
patch link:    https://lore.kernel.org/r/20251118125148.95603-7-wenliang202407%40163.com
patch subject: [PATCH v2 6/8] hwmon: (ina3221) Support for writing alert limit values and modify the 'ina3221_read_value' function.
config: arm-randconfig-002-20251119 (https://download.01.org/0day-ci/archive/20251119/202511191138.FRi6Ldng-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251119/202511191138.FRi6Ldng-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511191138.FRi6Ldng-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/hwmon/ina3221.c:554:7: error: duplicate case value: 'hwmon_curr_lcrit' and 'hwmon_in_lcrit' both equal '4'
           case hwmon_in_lcrit:
                ^
   drivers/hwmon/ina3221.c:541:7: note: previous case defined here
           case hwmon_curr_lcrit:
                ^
   1 error generated.


vim +554 drivers/hwmon/ina3221.c

   507	
   508	static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, int channel, long val)
   509	{
   510		struct regmap *regmap = ina->regmap;
   511		int item = channel % INA3221_NUM_CHANNELS;
   512		u8 limit_reg;
   513		u32 alert_group, alert_mask = 0;
   514		int regval = 0;
   515		int ret;
   516	
   517		if (item >= ARRAY_SIZE(alert_groups) || val < 0)
   518			return -EINVAL;
   519	
   520		alert_group = alert_groups[item];
   521		limit_reg = limit_regs[item];
   522	
   523		/* Clear alerts for this channel group first */
   524		ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0);
   525		if (ret)
   526			return ret;
   527	
   528		/* Determine alert type and calculate register value */
   529		switch (attr) {
   530		/*
   531		 * The alert warning logic is implemented by comparing the limit register values
   532		 * with the corresponding alert source register values. Since the current register
   533		 * is a 15-bit signed register and the power register is a 16-bit unsigned
   534		 * register, but the lower 3 bits of the limit register default to 0, the lower
   535		 * 3 bits will be forced to 0 when setting SUL and POL warning values.
   536		 * Formula to convert register value:
   537		 *     bus_voltage: (regval / 8mV) << 3
   538		 *     current: (regval / current_lsb) & 0xfff8
   539		 *     power: (regval / current_lsb) & 0xfff8
   540		 */
   541		case hwmon_curr_lcrit:
   542			/* SUL: Shunt Under Limit - BIT(15), BIT(14), BIT(13) */
   543			alert_mask = BIT(15 - item);
   544			/* Current Register, signed register, result in mA */
   545			regval = DIV_ROUND_CLOSEST(val * 1000, ina->current_lsb_uA) & 0xfff8;
   546			regval = clamp_val(regval, -32760, 32760);
   547			break;
   548		case hwmon_in_crit:
   549			/* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */
   550			alert_mask = BIT(12 - item);
   551			/* Bus Register, signed register, result in mV */
   552			regval = clamp_val(val, -32760, 32760);
   553			break;
 > 554		case hwmon_in_lcrit:
   555			/* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */
   556			alert_mask = BIT(9 - item);
   557			/* Bus Register, signed register, result in mV */
   558			regval = clamp_val(val, -32760, 32760);
   559			break;
   560		case hwmon_power_crit:
   561			/* POL: Power Over Limit - BIT(6), BIT(5), BIT(4) */
   562			alert_mask = BIT(6 - item);
   563			/* Power Register, unsigned register, result in mW */
   564			regval = DIV_ROUND_CLOSEST(val * 1000, ina->power_lsb_uW) & 0xfff8;
   565			regval = clamp_val(regval, 0, 65528);
   566			break;
   567		default:
   568			/* For unsupported attributes, just clear the configuration */
   569			ina->alert_type_select &= ~alert_group;
   570			return -EOPNOTSUPP;
   571		}
   572	
   573		/* Write limit register value */
   574		ret = regmap_write(regmap, limit_reg, regval);
   575		if (ret)
   576			return ret;
   577	
   578		/* Update alert configuration if limit value is non-zero */
   579		if (regval) {
   580			ina->alert_type_select = (ina->alert_type_select & ~alert_group) | alert_mask;
   581			ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG,
   582						alert_group, alert_mask);
   583		} else {
   584			ina->alert_type_select &= ~alert_group;
   585		}
   586	
   587		return ret;
   588	}
   589	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v2 6/8] hwmon: (ina3221) Support for writing alert limit values and modify the 'ina3221_read_value' function.

[Guenter Roeck]

On 11/18/25 04:51, Wenliang Yan wrote:
> SQ52210 adds power, current, and limit registers. The ina3221_read_value
> function has been refactored to adapt to the new register data reading
> format.
> 
> Each channel supports four new alert trigger modes, but only one trigger
> mode can be active at any given time. Alert values are stored in the same
> register. The sq52210_alert_limit_write function has been added to write
> alert threshold values and configure alert source type.
> 
> Signed-off-by: Wenliang Yan <wenliang202407@163.com>
> ---
>   drivers/hwmon/ina3221.c | 150 +++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 147 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
> index 1d589d402b52..9a25a1b40856 100644
> --- a/drivers/hwmon/ina3221.c
> +++ b/drivers/hwmon/ina3221.c
> @@ -66,6 +66,14 @@
>   #define INA3221_MASK_ENABLE_SCC_MASK	GENMASK(14, 12)
>   
>   #define SQ52210_ALERT_CONFIG_MASK	GENMASK(15, 4)
> +#define SQ52210_MASK_ALERT_CHANNEL1 (BIT(15) | BIT(12) | BIT(9) | BIT(6))
> +#define SQ52210_MASK_ALERT_CHANNEL2 (BIT(14) | BIT(11) | BIT(8) | BIT(5))
> +#define SQ52210_MASK_ALERT_CHANNEL3 (BIT(13) | BIT(10) | BIT(7) | BIT(4))
> +
> +#define SQ52210_ALERT_ALL_SUL_MASK	(BIT(15) | BIT(14) | BIT(13))
> +#define SQ52210_ALERT_ALL_BOL_MASK	(BIT(12) | BIT(11) | BIT(10))
> +#define SQ52210_ALERT_ALL_BUL_MASK	(BIT(9) | BIT(8) | BIT(7))
> +#define SQ52210_ALERT_ALL_POL_MASK	(BIT(6) | BIT(5) | BIT(4))
>   
>   #define INA3221_CONFIG_DEFAULT		0x7127
>   #define INA3221_RSHUNT_DEFAULT		10000
> @@ -272,6 +280,18 @@ static inline int ina3221_wait_for_data(struct ina3221_data *ina)
>   					      cvrf, cvrf, wait, wait * 2);
>   }
>   
> +static const u32 alert_groups[] = {
> +	SQ52210_MASK_ALERT_CHANNEL1,
> +	SQ52210_MASK_ALERT_CHANNEL2,
> +	SQ52210_MASK_ALERT_CHANNEL3,
> +};
> +
> +static const u8 limit_regs[] = {
> +	SQ52210_ALERT_LIMIT1,
> +	SQ52210_ALERT_LIMIT2,
> +	SQ52210_ALERT_LIMIT3,
> +};
> +
>   static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
>   			      int *val)
>   {
> @@ -284,13 +304,55 @@ static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
>   
>   	/*
>   	 * Shunt Voltage Sum register has 14-bit value with 1-bit shift
> +	 * Current registers have 15-bit value
> +	 * Power registers have 16-bit value
> +	 * ALERT_LIMIT registers have 16-bit value with 3-bit shift
>   	 * Other Shunt Voltage registers have 12 bits with 3-bit shift
>   	 */
> -	if (reg == INA3221_SHUNT_SUM || reg == INA3221_CRIT_SUM)
> +	switch (reg) {
> +	case INA3221_SHUNT_SUM:
> +	case INA3221_CRIT_SUM:
>   		*val = sign_extend32(regval >> 1, 14);
> -	else
> +		break;
> +	case SQ52210_CURRENT1:
> +	case SQ52210_CURRENT2:
> +	case SQ52210_CURRENT3:
> +		*val = sign_extend32(regval, 15);
> +		break;
> +	case SQ52210_POWER1:
> +	case SQ52210_POWER2:
> +	case SQ52210_POWER3:
> +		*val = regval;
> +		break;
> +	case INA3221_BUS1:
> +	case INA3221_BUS2:
> +	case INA3221_BUS3:
> +	case INA3221_SHUNT1:
> +	case INA3221_SHUNT2:
> +	case INA3221_SHUNT3:
> +	case INA3221_WARN1:
> +	case INA3221_WARN2:
> +	case INA3221_WARN3:
> +	case INA3221_CRIT1:
> +	case INA3221_CRIT2:
> +	case INA3221_CRIT3:
>   		*val = sign_extend32(regval >> 3, 12);
> -
> +		break;
> +	case SQ52210_ALERT_LIMIT1:
> +	case SQ52210_ALERT_LIMIT2:
> +	case SQ52210_ALERT_LIMIT3:
> +		if (ina->alert_type_select & SQ52210_ALERT_ALL_SUL_MASK)
> +			*val = sign_extend32(regval, 15);
> +		else if (ina->alert_type_select & (SQ52210_ALERT_ALL_BOL_MASK
> +					| SQ52210_ALERT_ALL_BUL_MASK))
> +			*val = regval >> 3;
> +		else if (ina->alert_type_select & SQ52210_ALERT_ALL_POL_MASK)
> +			*val = regval;
> +		break;
> +	default:
> +		*val = 0;
> +		return -EOPNOTSUPP;
> +	};
>   	return 0;
>   }
>   
> @@ -443,6 +505,88 @@ static int ina3221_read_curr(struct device *dev, u32 attr,
>   	}
>   }
>   
> +static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, int channel, long val)
> +{
> +	struct regmap *regmap = ina->regmap;
> +	int item = channel % INA3221_NUM_CHANNELS;
> +	u8 limit_reg;
> +	u32 alert_group, alert_mask = 0;
> +	int regval = 0;
> +	int ret;
> +
> +	if (item >= ARRAY_SIZE(alert_groups) || val < 0)
> +		return -EINVAL;
> +
> +	alert_group = alert_groups[item];
> +	limit_reg = limit_regs[item];
> +
> +	/* Clear alerts for this channel group first */
> +	ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0);
> +	if (ret)
> +		return ret;
> +
> +	/* Determine alert type and calculate register value */
> +	switch (attr) {
> +	/*
> +	 * The alert warning logic is implemented by comparing the limit register values
> +	 * with the corresponding alert source register values. Since the current register
> +	 * is a 15-bit signed register and the power register is a 16-bit unsigned
> +	 * register, but the lower 3 bits of the limit register default to 0, the lower
> +	 * 3 bits will be forced to 0 when setting SUL and POL warning values.
> +	 * Formula to convert register value:
> +	 *     bus_voltage: (regval / 8mV) << 3
> +	 *     current: (regval / current_lsb) & 0xfff8
> +	 *     power: (regval / current_lsb) & 0xfff8
> +	 */
> +	case hwmon_curr_lcrit:
> +		/* SUL: Shunt Under Limit - BIT(15), BIT(14), BIT(13) */
> +		alert_mask = BIT(15 - item);
> +		/* Current Register, signed register, result in mA */
> +		regval = DIV_ROUND_CLOSEST(val * 1000, ina->current_lsb_uA) & 0xfff8;
> +		regval = clamp_val(regval, -32760, 32760);
> +		break;
> +	case hwmon_in_crit:
> +		/* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */
> +		alert_mask = BIT(12 - item);
> +		/* Bus Register, signed register, result in mV */
> +		regval = clamp_val(val, -32760, 32760);
> +		break;
> +	case hwmon_in_lcrit:
> +		/* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */
> +		alert_mask = BIT(9 - item);
> +		/* Bus Register, signed register, result in mV */
> +		regval = clamp_val(val, -32760, 32760);
> +		break;
> +	case hwmon_power_crit:

Didn't I say this before ? The number space for each sensor type overlaps.
Sensor attributes for different types can not be used in the same case statement.

Did you even compile this ? I would be quite surprised if there is a compiler
that would accept this code.

Guenter

Re: [PATCH v2 1/8] dt-bindings: hwmon: ti,ina3221: Add SQ52210

[Krzysztof Kozlowski]

On Tue, Nov 18, 2025 at 07:51:41AM -0500, Wenliang Yan wrote:
> Add a compatible string for sq52210. The sq52210 is forward compatible

forward?

> with INA3221 and incorporates alert registers to implement four

But this suggests opposite.

Your driver changes confirm that even more - it is not forward
compatible. And in other way why wouldn't compatibility be expressed in
the bindings?

Best regards,
Krzysztof

Re: [PATCH v2 1/8] dt-bindings: hwmon: ti,ina3221: Add SQ52210

[Wenliang Yan]

At 2025-11-19 15:22:38, "Krzysztof Kozlowski" <krzk@kernel.org> wrote:
>On Tue, Nov 18, 2025 at 07:51:41AM -0500, Wenliang Yan wrote:
>> Add a compatible string for sq52210. The sq52210 is forward compatible
>
>forward?
>
>> with INA3221 and incorporates alert registers to implement four
>
>But this suggests opposite.
>
>Your driver changes confirm that even more - it is not forward
>compatible. And in other way why wouldn't compatibility be expressed in
>the bindings?
>
>Best regards,
>Krzysztof

Perhaps my use of "forward" was inaccurate. I only meant to express that
at the hardware level, the SQ52210 contains all the registers and
functions of the INA3221, and builds upon them by adding current, power,
and alert registers. However, these additional registers don't require
adding more specific properties in the binding file.
Are you suggesting that I'm missing the description of SQ52210's
characteristics in the documentation?


Thanks,
Wenlaing Yan

Re: [PATCH v2 1/8] dt-bindings: hwmon: ti,ina3221: Add SQ52210

[Krzysztof Kozlowski]

On 19/11/2025 10:06, Wenliang Yan wrote:
> At 2025-11-19 15:22:38, "Krzysztof Kozlowski" <krzk@kernel.org> wrote:
>> On Tue, Nov 18, 2025 at 07:51:41AM -0500, Wenliang Yan wrote:
>>> Add a compatible string for sq52210. The sq52210 is forward compatible
>>
>> forward?
>>
>>> with INA3221 and incorporates alert registers to implement four
>>
>> But this suggests opposite.
>>
>> Your driver changes confirm that even more - it is not forward
>> compatible. And in other way why wouldn't compatibility be expressed in
>> the bindings?
>>
>> Best regards,
>> Krzysztof
> 
> Perhaps my use of "forward" was inaccurate. I only meant to express that
> at the hardware level, the SQ52210 contains all the registers and
> functions of the INA3221, and builds upon them by adding current, power,
> and alert registers. However, these additional registers don't require
> adding more specific properties in the binding file.
> Are you suggesting that I'm missing the description of SQ52210's
> characteristics in the documentation?

This is backwards compatibility and if that's the case - driver can bind
via old compatible and work correctly with previous functionality - why
not expressing it in the bindings as compatible devices? See writing
bindings.

Best regards,
Krzysztof

Re: [PATCH v2 6/8] hwmon: (ina3221) Support for writing alert limit values and modify the 'ina3221_read_value' function.

[Wenliang Yan]

At 2025-11-19 12:20:34, "Guenter Roeck" <linux@roeck-us.net> wrote:
>On 11/18/25 04:51, Wenliang Yan wrote:
>> SQ52210 adds power, current, and limit registers. The ina3221_read_value
>> function has been refactored to adapt to the new register data reading
>> format.
>> 
>> Each channel supports four new alert trigger modes, but only one trigger
>> mode can be active at any given time. Alert values are stored in the same
>> register. The sq52210_alert_limit_write function has been added to write
>> alert threshold values and configure alert source type.
>> 
>> Signed-off-by: Wenliang Yan <wenliang202407@163.com>
>> ---
>>   drivers/hwmon/ina3221.c | 150 +++++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 147 insertions(+), 3 deletions(-)
>> 
>> diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
>> index 1d589d402b52..9a25a1b40856 100644
>> --- a/drivers/hwmon/ina3221.c
>> +++ b/drivers/hwmon/ina3221.c
>> @@ -66,6 +66,14 @@
>>   #define INA3221_MASK_ENABLE_SCC_MASK	GENMASK(14, 12)
>>   
>>   #define SQ52210_ALERT_CONFIG_MASK	GENMASK(15, 4)
>> +#define SQ52210_MASK_ALERT_CHANNEL1 (BIT(15) | BIT(12) | BIT(9) | BIT(6))
>> +#define SQ52210_MASK_ALERT_CHANNEL2 (BIT(14) | BIT(11) | BIT(8) | BIT(5))
>> +#define SQ52210_MASK_ALERT_CHANNEL3 (BIT(13) | BIT(10) | BIT(7) | BIT(4))
>> +
>> +#define SQ52210_ALERT_ALL_SUL_MASK	(BIT(15) | BIT(14) | BIT(13))
>> +#define SQ52210_ALERT_ALL_BOL_MASK	(BIT(12) | BIT(11) | BIT(10))
>> +#define SQ52210_ALERT_ALL_BUL_MASK	(BIT(9) | BIT(8) | BIT(7))
>> +#define SQ52210_ALERT_ALL_POL_MASK	(BIT(6) | BIT(5) | BIT(4))
>>   
>>   #define INA3221_CONFIG_DEFAULT		0x7127
>>   #define INA3221_RSHUNT_DEFAULT		10000
>> @@ -272,6 +280,18 @@ static inline int ina3221_wait_for_data(struct ina3221_data *ina)
>>   					      cvrf, cvrf, wait, wait * 2);
>>   }
>>   
>> +static const u32 alert_groups[] = {
>> +	SQ52210_MASK_ALERT_CHANNEL1,
>> +	SQ52210_MASK_ALERT_CHANNEL2,
>> +	SQ52210_MASK_ALERT_CHANNEL3,
>> +};
>> +
>> +static const u8 limit_regs[] = {
>> +	SQ52210_ALERT_LIMIT1,
>> +	SQ52210_ALERT_LIMIT2,
>> +	SQ52210_ALERT_LIMIT3,
>> +};
>> +
>>   static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
>>   			      int *val)
>>   {
>> @@ -284,13 +304,55 @@ static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
>>   
>>   	/*
>>   	 * Shunt Voltage Sum register has 14-bit value with 1-bit shift
>> +	 * Current registers have 15-bit value
>> +	 * Power registers have 16-bit value
>> +	 * ALERT_LIMIT registers have 16-bit value with 3-bit shift
>>   	 * Other Shunt Voltage registers have 12 bits with 3-bit shift
>>   	 */
>> -	if (reg == INA3221_SHUNT_SUM || reg == INA3221_CRIT_SUM)
>> +	switch (reg) {
>> +	case INA3221_SHUNT_SUM:
>> +	case INA3221_CRIT_SUM:
>>   		*val = sign_extend32(regval >> 1, 14);
>> -	else
>> +		break;
>> +	case SQ52210_CURRENT1:
>> +	case SQ52210_CURRENT2:
>> +	case SQ52210_CURRENT3:
>> +		*val = sign_extend32(regval, 15);
>> +		break;
>> +	case SQ52210_POWER1:
>> +	case SQ52210_POWER2:
>> +	case SQ52210_POWER3:
>> +		*val = regval;
>> +		break;
>> +	case INA3221_BUS1:
>> +	case INA3221_BUS2:
>> +	case INA3221_BUS3:
>> +	case INA3221_SHUNT1:
>> +	case INA3221_SHUNT2:
>> +	case INA3221_SHUNT3:
>> +	case INA3221_WARN1:
>> +	case INA3221_WARN2:
>> +	case INA3221_WARN3:
>> +	case INA3221_CRIT1:
>> +	case INA3221_CRIT2:
>> +	case INA3221_CRIT3:
>>   		*val = sign_extend32(regval >> 3, 12);
>> -
>> +		break;
>> +	case SQ52210_ALERT_LIMIT1:
>> +	case SQ52210_ALERT_LIMIT2:
>> +	case SQ52210_ALERT_LIMIT3:
>> +		if (ina->alert_type_select & SQ52210_ALERT_ALL_SUL_MASK)
>> +			*val = sign_extend32(regval, 15);
>> +		else if (ina->alert_type_select & (SQ52210_ALERT_ALL_BOL_MASK
>> +					| SQ52210_ALERT_ALL_BUL_MASK))
>> +			*val = regval >> 3;
>> +		else if (ina->alert_type_select & SQ52210_ALERT_ALL_POL_MASK)
>> +			*val = regval;
>> +		break;
>> +	default:
>> +		*val = 0;
>> +		return -EOPNOTSUPP;
>> +	};
>>   	return 0;
>>   }
>>   
>> @@ -443,6 +505,88 @@ static int ina3221_read_curr(struct device *dev, u32 attr,
>>   	}
>>   }
>>   
>> +static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, int channel, long val)
>> +{
>> +	struct regmap *regmap = ina->regmap;
>> +	int item = channel % INA3221_NUM_CHANNELS;
>> +	u8 limit_reg;
>> +	u32 alert_group, alert_mask = 0;
>> +	int regval = 0;
>> +	int ret;
>> +
>> +	if (item >= ARRAY_SIZE(alert_groups) || val < 0)
>> +		return -EINVAL;
>> +
>> +	alert_group = alert_groups[item];
>> +	limit_reg = limit_regs[item];
>> +
>> +	/* Clear alerts for this channel group first */
>> +	ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Determine alert type and calculate register value */
>> +	switch (attr) {
>> +	/*
>> +	 * The alert warning logic is implemented by comparing the limit register values
>> +	 * with the corresponding alert source register values. Since the current register
>> +	 * is a 15-bit signed register and the power register is a 16-bit unsigned
>> +	 * register, but the lower 3 bits of the limit register default to 0, the lower
>> +	 * 3 bits will be forced to 0 when setting SUL and POL warning values.
>> +	 * Formula to convert register value:
>> +	 *     bus_voltage: (regval / 8mV) << 3
>> +	 *     current: (regval / current_lsb) & 0xfff8
>> +	 *     power: (regval / current_lsb) & 0xfff8
>> +	 */
>> +	case hwmon_curr_lcrit:
>> +		/* SUL: Shunt Under Limit - BIT(15), BIT(14), BIT(13) */
>> +		alert_mask = BIT(15 - item);
>> +		/* Current Register, signed register, result in mA */
>> +		regval = DIV_ROUND_CLOSEST(val * 1000, ina->current_lsb_uA) & 0xfff8;
>> +		regval = clamp_val(regval, -32760, 32760);
>> +		break;
>> +	case hwmon_in_crit:
>> +		/* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */
>> +		alert_mask = BIT(12 - item);
>> +		/* Bus Register, signed register, result in mV */
>> +		regval = clamp_val(val, -32760, 32760);
>> +		break;
>> +	case hwmon_in_lcrit:
>> +		/* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */
>> +		alert_mask = BIT(9 - item);
>> +		/* Bus Register, signed register, result in mV */
>> +		regval = clamp_val(val, -32760, 32760);
>> +		break;
>> +	case hwmon_power_crit:
>
>Didn't I say this before ? The number space for each sensor type overlaps.
>Sensor attributes for different types can not be used in the same case statement.
>
>Did you even compile this ? I would be quite surprised if there is a compiler
>that would accept this code.
>
>Guenter

This was due to an oversight during the preparation of the patch series:
I inadvertently uploaded an incorrect patch version. Specifically, I submitted
code from an earlier modification phase instead of the final thoroughly tested
version. The updated release introduces new enum variables to address this problem,
and I will promptly prepare and submit a corrected v3 version containing the
proper code.
My sincere apologies for any inconvenience this may have caused.
Thank you for your understanding and patience.


Thanks,
Wenlaing Yan

Re: [PATCH v2 1/8] dt-bindings: hwmon: ti,ina3221: Add SQ52210

[Wenliang Yan]

At 2025-11-19 17:17:18, "Krzysztof Kozlowski" <krzk@kernel.org> wrote:
>On 19/11/2025 10:06, Wenliang Yan wrote:
>> At 2025-11-19 15:22:38, "Krzysztof Kozlowski" <krzk@kernel.org> wrote:
>>> On Tue, Nov 18, 2025 at 07:51:41AM -0500, Wenliang Yan wrote:
>>>> Add a compatible string for sq52210. The sq52210 is forward compatible
>>>
>>> forward?
>>>
>>>> with INA3221 and incorporates alert registers to implement four
>>>
>>> But this suggests opposite.
>>>
>>> Your driver changes confirm that even more - it is not forward
>>> compatible. And in other way why wouldn't compatibility be expressed in
>>> the bindings?
>>>
>>> Best regards,
>>> Krzysztof
>> 
>> Perhaps my use of "forward" was inaccurate. I only meant to express that
>> at the hardware level, the SQ52210 contains all the registers and
>> functions of the INA3221, and builds upon them by adding current, power,
>> and alert registers. However, these additional registers don't require
>> adding more specific properties in the binding file.
>> Are you suggesting that I'm missing the description of SQ52210's
>> characteristics in the documentation?
>
>This is backwards compatibility and if that's the case - driver can bind
>via old compatible and work correctly with previous functionality - why
>not expressing it in the bindings as compatible devices? See writing
>bindings.
>
>Best regards,
>Krzysztof

Okay, I will use oneOf to express the compatibility relationship in the
v3 version.

Thanks,
Wenlaing Yan