From: sashiko-bot@kernel.org
To: "Guenter Roeck" <linux@roeck-us.net>, linux-hwmon@vger.kernel.org
Subject: Re: [PATCH] hwmon: (lm75) Fix setting polarity mask for chips with 16-bit config register
Date: Sat, 31 Oct 2026 03:49:56 +0000 [thread overview]
Message-ID: <sashiko-outbox-191736@kernel.org> (raw)
In-Reply-To: <20261031034755.1079779-1-linux@roeck-us.net>
> When probing a 16-bit compatible temperature sensor configured with the
> "ti,alert-polarity-active-high" device property, lm75_generic_probe()
> writes to a reserved bit instead of the alert polarity bit due to an
> incorrect bit shift in the 16-bit polarity mask.
> On 16-bit sensors, the polarity bit is physically located at bit 2 of the
> MSByte. When accessed via i2c_smbus_read_word_data() or
> i2c_smbus_write_word_data(), the SMBus protocol maps the first received
> byte (the physical MSByte) to the lower 8 bits of the integer
> representation. Consequently, the polarity bit is consistently mapped to
> bit 2, identically to 8-bit sensors. However, the
> LM75_ALERT_POLARITY_HIGH_16_BIT macro applies an 8-bit left shift,
> erroneously targeting bit 10. This causes the driver to silently corrupt a
> reserved bit in the configuration register while leaving the active-high
> alert polarity unconfigured, breaking the polarity feature.
>
> Use BIT(2) as polarity mask in the configuration register for all chips
> to fix the problem.
>
> Reported-by: Sashiko <sashiko-bot@kernel.org>
> Fixes: 1be4001d9b9b ("hwmon: (lm75) Support active-high alert polarity")
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261031034755.1079779-1-linux@roeck-us.net?part=1
prev parent reply other threads:[~2026-10-31 3:49 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-31 3:47 [PATCH] hwmon: (lm75) Fix setting polarity mask for chips with 16-bit config register Guenter Roeck
2026-10-31 3:49 ` sashiko-bot [this message]
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