* [PATCH] hwmon: (lm75) Fix setting polarity mask for chips with 16-bit config register
@ 2026-10-31 3:47 Guenter Roeck
2026-10-31 3:49 ` sashiko-bot
0 siblings, 1 reply; 2+ messages in thread
From: Guenter Roeck @ 2026-10-31 3:47 UTC (permalink / raw)
To: linux-hwmon; +Cc: Guenter Roeck, Sashiko
When probing a 16-bit compatible temperature sensor configured with the
"ti,alert-polarity-active-high" device property, lm75_generic_probe()
writes to a reserved bit instead of the alert polarity bit due to an
incorrect bit shift in the 16-bit polarity mask.
On 16-bit sensors, the polarity bit is physically located at bit 2 of the
MSByte. When accessed via i2c_smbus_read_word_data() or
i2c_smbus_write_word_data(), the SMBus protocol maps the first received
byte (the physical MSByte) to the lower 8 bits of the integer
representation. Consequently, the polarity bit is consistently mapped to
bit 2, identically to 8-bit sensors. However, the
LM75_ALERT_POLARITY_HIGH_16_BIT macro applies an 8-bit left shift,
erroneously targeting bit 10. This causes the driver to silently corrupt a
reserved bit in the configuration register while leaving the active-high
alert polarity unconfigured, breaking the polarity feature.
Use BIT(2) as polarity mask in the configuration register for all chips
to fix the problem.
Reported-by: Sashiko <sashiko-bot@kernel.org>
Fixes: 1be4001d9b9b ("hwmon: (lm75) Support active-high alert polarity")
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
drivers/hwmon/lm75.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c
index 2d2d752aeac9..917ac250a648 100644
--- a/drivers/hwmon/lm75.c
+++ b/drivers/hwmon/lm75.c
@@ -123,8 +123,7 @@ struct lm75_data {
static const u8 lm75_sample_set_masks[] = { 0 << 5, 1 << 5, 2 << 5, 3 << 5 };
-#define LM75_ALERT_POLARITY_HIGH_8_BIT (BIT(2))
-#define LM75_ALERT_POLARITY_HIGH_16_BIT (BIT(2) << 8)
+#define LM75_ALERT_POLARITY_HIGH_BIT BIT(2)
#define LM75_SAMPLE_CLEAR_MASK (3 << 5)
/* The structure below stores the configuration values of the supported devices.
@@ -770,11 +769,7 @@ static int lm75_generic_probe(struct device *dev, const char *name,
data->orig_conf = status;
/* Enforce polarity active-low (default) or active-high (devicetree) */
- if (!data->params->config_reg_16bits)
- pol_mask = LM75_ALERT_POLARITY_HIGH_8_BIT;
- else
- pol_mask = LM75_ALERT_POLARITY_HIGH_16_BIT;
-
+ pol_mask = LM75_ALERT_POLARITY_HIGH_BIT;
clr_mask = data->params->clr_mask | pol_mask;
set_mask = data->params->set_mask & ~pol_mask;
if (device_property_read_bool(dev, "ti,alert-polarity-active-high"))
--
2.45.2
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] hwmon: (lm75) Fix setting polarity mask for chips with 16-bit config register
2026-10-31 3:47 [PATCH] hwmon: (lm75) Fix setting polarity mask for chips with 16-bit config register Guenter Roeck
@ 2026-10-31 3:49 ` sashiko-bot
0 siblings, 0 replies; 2+ messages in thread
From: sashiko-bot @ 2026-10-31 3:49 UTC (permalink / raw)
To: Guenter Roeck, linux-hwmon
> When probing a 16-bit compatible temperature sensor configured with the
> "ti,alert-polarity-active-high" device property, lm75_generic_probe()
> writes to a reserved bit instead of the alert polarity bit due to an
> incorrect bit shift in the 16-bit polarity mask.
> On 16-bit sensors, the polarity bit is physically located at bit 2 of the
> MSByte. When accessed via i2c_smbus_read_word_data() or
> i2c_smbus_write_word_data(), the SMBus protocol maps the first received
> byte (the physical MSByte) to the lower 8 bits of the integer
> representation. Consequently, the polarity bit is consistently mapped to
> bit 2, identically to 8-bit sensors. However, the
> LM75_ALERT_POLARITY_HIGH_16_BIT macro applies an 8-bit left shift,
> erroneously targeting bit 10. This causes the driver to silently corrupt a
> reserved bit in the configuration register while leaving the active-high
> alert polarity unconfigured, breaking the polarity feature.
>
> Use BIT(2) as polarity mask in the configuration register for all chips
> to fix the problem.
>
> Reported-by: Sashiko <sashiko-bot@kernel.org>
> Fixes: 1be4001d9b9b ("hwmon: (lm75) Support active-high alert polarity")
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261031034755.1079779-1-linux@roeck-us.net?part=1
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