From: Wolfram Sang <wsa@the-dreams.de>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
linux-i2c@vger.kernel.org
Subject: Re: [PATCH v2 0/3] i2c: designware-pci: refactor and add Merrifield support
Date: Sun, 19 Jun 2016 20:17:43 +0200 [thread overview]
Message-ID: <20160619181742.GK2933@tetsubishi> (raw)
In-Reply-To: <1466359691.30123.171.camel@linux.intel.com>
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> - * On Intel Merrifield the i2c busses are enumerated [1..7]. So,
> we add
> - * 1 to shift the default range. Besides that the first PCI slot
> - * provides 4 functions, that's why we have to add 0 to the head
> slot
> - * and 4 to the tail one.
> + * On Intel Merrifield the user visible i2c busses are
> enumerated
> + * [1..7]. So, we add 1 to shift the default range. Besides that
> the
> + * first PCI slot provides 4 functions, that's why we have to
> add 0 to
> + * the fisrt slot and 4 to the next one.
> */
> switch (PCI_SLOT(pdev->devfn)) {
> case 8:
>
> Should I send a new patch or you can fold it?
I already pushed out. Also, this patch has line break problems.
So, send an incremental one.
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prev parent reply other threads:[~2016-06-19 19:01 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-15 15:05 [PATCH v2 0/3] i2c: designware-pci: refactor and add Merrifield support Andy Shevchenko
2016-06-15 15:05 ` [PATCH v2 1/3] i2c: designware-pci: Make bus number allocation robust Andy Shevchenko
2016-06-15 15:05 ` [PATCH v2 2/3] i2c: designware-pci: Introduce Merrifield support Andy Shevchenko
2016-06-15 15:05 ` [PATCH v2 3/3] i2c: designware-pci: Sort header block alphabetically Andy Shevchenko
2016-06-16 7:44 ` [PATCH v2 0/3] i2c: designware-pci: refactor and add Merrifield support Jarkko Nikula
2016-06-19 17:42 ` Wolfram Sang
2016-06-19 18:08 ` Andy Shevchenko
2016-06-19 18:17 ` Wolfram Sang [this message]
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