From: Chaitanya Sabnis <chaitanya.msabnis@gmail.com>
To: wsa@kernel.org, thor.thayer@linux.intel.com
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
linux-i2c@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Chaitanya Sabnis <chaitanya.msabnis@gmail.com>
Subject: [PATCH] dt-bindings: i2c: convert altera i2c to dt-schema
Date: Tue, 5 May 2026 11:02:01 +0530 [thread overview]
Message-ID: <20260505053201.5795-1-chaitanya.msabnis@gmail.com> (raw)
Convert the Altera SoftIP I2C Controller bindings from legacy text
format to modern dt-schema (YAML).
The hardware constraints and properties remain identical. The example
node was updated to use a standard 32-bit address space to clear
compilation warnings.
Signed-off-by: Chaitanya Sabnis <chaitanya.msabnis@gmail.com>
---
.../bindings/i2c/altr,softip-i2c-v1.0.yaml | 62 +++++++++++++++++++
.../devicetree/bindings/i2c/i2c-altera.txt | 39 ------------
2 files changed, 62 insertions(+), 39 deletions(-)
create mode 100644 Documentation/devicetree/bindings/i2c/altr,softip-i2c-v1.0.yaml
delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-altera.txt
diff --git a/Documentation/devicetree/bindings/i2c/altr,softip-i2c-v1.0.yaml b/Documentation/devicetree/bindings/i2c/altr,softip-i2c-v1.0.yaml
new file mode 100644
index 000000000000..d04570680c05
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/altr,softip-i2c-v1.0.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/altr,softip-i2c-v1.0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera I2C Controller
+
+maintainers:
+ - Thor Thayer <thor.thayer@linux.intel.com>
+ - Chaitanya Sabnis <chaitanya.msabnis@gmail.com>
+
+description:
+ Altera's synthesizable logic block I2C Controller for use in Altera's FPGAs.
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ const: altr,softip-i2c-v1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ fifo-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Size of the RX and TX FIFOs in bytes.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c@80000 {
+ compatible = "altr,softip-i2c-v1.0";
+ reg = <0x80000 0x40>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 43 4>;
+ clocks = <&clk_0>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fifo-size = <4>;
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-altera.txt b/Documentation/devicetree/bindings/i2c/i2c-altera.txt
deleted file mode 100644
index 767664f448ec..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-altera.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-* Altera I2C Controller
-* This is Altera's synthesizable logic block I2C Controller for use
-* in Altera's FPGAs.
-
-Required properties :
- - compatible : should be "altr,softip-i2c-v1.0"
- - reg : Offset and length of the register set for the device
- - interrupts : <IRQ> where IRQ is the interrupt number.
- - clocks : phandle to input clock.
- - #address-cells = <1>;
- - #size-cells = <0>;
-
-Recommended properties :
- - clock-frequency : desired I2C bus clock frequency in Hz.
-
-Optional properties :
- - fifo-size : Size of the RX and TX FIFOs in bytes.
- - Child nodes conforming to i2c bus binding
-
-Example :
-
- i2c@100080000 {
- compatible = "altr,softip-i2c-v1.0";
- reg = <0x00000001 0x00080000 0x00000040>;
- interrupt-parent = <&intc>;
- interrupts = <0 43 4>;
- clocks = <&clk_0>;
- clock-frequency = <100000>;
- #address-cells = <1>;
- #size-cells = <0>;
- fifo-size = <4>;
-
- eeprom@51 {
- compatible = "atmel,24c32";
- reg = <0x51>;
- pagesize = <32>;
- };
- };
-
--
2.43.0
reply other threads:[~2026-05-05 5:32 UTC|newest]
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