From: Vladimir Zapolskiy <vz@kernel.org>
To: Loic Poulain <loic.poulain@oss.qualcomm.com>,
Robert Foss <rfoss@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Abel Vesa <abelvesa@kernel.org>
Cc: Andi Shyti <andi.shyti@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH 2/3] arm64: dts: qcom: sm8350: Add CCI device tree nodes
Date: Thu, 5 Nov 2026 01:05:28 +0200 [thread overview]
Message-ID: <20261104230529.3040285-3-vz@kernel.org> (raw)
In-Reply-To: <20261104230529.3040285-1-vz@kernel.org>
Add Camera Control Interface (CCI) controller device tree nodes and pin
configurations of the I2C busses to SM8350 SoC dtsi.
Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 147 +++++++++++++++++++++++++++
1 file changed, 147 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a51942c99f8a..41dff3736061 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8350-camcc.h>
#include <dt-bindings/clock/qcom,sm8350-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
@@ -2830,6 +2831,88 @@ videocc: clock-controller@abf0000 {
#power-domain-cells = <1>;
};
+ cci0: cci@ac4f000 {
+ compatible = "qcom,sm8350-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac4f000 0 0x1000>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+
+ pinctrl-0 = <&cci0_0_default &cci0_1_default>;
+ pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac50000 {
+ compatible = "qcom,sm8350-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac50000 0 0x1000>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+
+ pinctrl-0 = <&cci1_0_default &cci1_1_default>;
+ pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sm8350-camcc";
reg = <0 0x0ad00000 0 0x10000>;
@@ -3348,6 +3431,70 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 204>;
wakeup-parent = <&pdc>;
+ cci0_0_default: cci0-0-default-state {
+ /* SDA, SCL */
+ pins = "gpio107", "gpio108";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_0_sleep: cci0-0-sleep-state {
+ /* SDA, SCL */
+ pins = "gpio107", "gpio108";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci0_1_default: cci0-1-default-state {
+ /* SDA, SCL */
+ pins = "gpio109", "gpio110";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_1_sleep: cci0-1-sleep-state {
+ /* SDA, SCL */
+ pins = "gpio109", "gpio110";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_0_default: cci1-0-default-state {
+ /* SDA, SCL */
+ pins = "gpio111", "gpio112";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_0_sleep: cci1-0-sleep-state {
+ /* SDA, SCL */
+ pins = "gpio111", "gpio112";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_1_default: cci1-1-default-state {
+ /* SDA, SCL */
+ pins = "gpio113", "gpio114";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_1_sleep: cci1-1-sleep-state {
+ /* SDA, SCL */
+ pins = "gpio113", "gpio114";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
sdc2_default_state: sdc2-default-state {
clk-pins {
pins = "sdc2_clk";
--
2.51.0
next prev parent reply other threads:[~2026-11-04 23:05 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-04 23:05 [PATCH 0/3] arm64: dts: qcom: sm8350: Add CCI and camera MCLK pins Vladimir Zapolskiy
2026-11-04 23:05 ` [PATCH 1/3] dt-bindings: i2c: qcom-cci: Document SM8350 compatible Vladimir Zapolskiy
2026-11-05 8:38 ` Loic Poulain
2026-11-04 23:05 ` Vladimir Zapolskiy [this message]
2026-11-05 8:37 ` [PATCH 2/3] arm64: dts: qcom: sm8350: Add CCI device tree nodes Loic Poulain
2026-11-04 23:05 ` [PATCH 3/3] arm64: dts: qcom: sm8350: Add camera MCLK pinctrl states Vladimir Zapolskiy
2026-11-05 8:56 ` Konrad Dybcio
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