From: Krzysztof Kozlowski <krzk@kernel.org>
To: Kartik Rajput <kkartik@nvidia.com>,
"thierry.reding@gmail.com" <thierry.reding@gmail.com>,
Jon Hunter <jonathanh@nvidia.com>,
Akhil R <akhilrajeev@nvidia.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"robh@kernel.org" <robh@kernel.org>,
Laxman Dewangan <ldewangan@nvidia.com>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"andi.shyti@kernel.org" <andi.shyti@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"linux-i2c@vger.kernel.org" <linux-i2c@vger.kernel.org>,
"digetx@gmail.com" <digetx@gmail.com>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v2 4/5] i2c: tegra: Add support for SW mutex register
Date: Thu, 30 Jan 2025 18:49:14 +0100 [thread overview]
Message-ID: <4b9777cc-0bb3-44c1-92f8-209c30837f20@kernel.org> (raw)
In-Reply-To: <0daa503e73099085d84d432bb72a5f79db81a9b1.camel@nvidia.com>
On 30/01/2025 17:35, Kartik Rajput wrote:
>>> /**
>>> @@ -372,6 +382,103 @@ static void i2c_readsl(struct tegra_i2c_dev
>>> *i2c_dev, void *data,
>>> readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg),
>>> data, len);
>>> }
>>>
>>> +static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
>>> + u32 reg, u32 mask, u32 delay_us,
>>> + u32 timeout_us)
>>> +{
>>> + void __iomem *addr = i2c_dev->base +
>>> tegra_i2c_reg_addr(i2c_dev, reg);
>>> + u32 val;
>>> +
>>> + if (!i2c_dev->atomic_mode)
>>> + return readl_relaxed_poll_timeout(addr, val, !(val &
>>> mask),
>>> + delay_us,
>>> timeout_us);
>>> +
>>> + return readl_relaxed_poll_timeout_atomic(addr, val, !(val &
>>> mask),
>>> + delay_us,
>>> timeout_us);
>>> +}
>>> +
>>> +static int tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev)
>>> +{
>>> + u32 val, id;
>>> +
>>> + val = i2c_readl(i2c_dev, I2C_SW_MUTEX);
>>> + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
>>> + if (id != 0 && id != I2C_SW_MUTEX_ID)
>>> + return 0;
>>> +
>>> + val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID);
>>> + i2c_writel(i2c_dev, val, I2C_SW_MUTEX);
>>
>> And how do you exactly prevent concurrent, overwriting write? This
>> looks
>> like pure race.
>>
>
> The I2C_SW_MUTEX_GRANT field reflects the id of the current mutex
> owner. The I2C_SW_MUTEX_GRANT field does not change with overwrites to
> the I2C_SW_MUTEX_REQUEST field, unless I2C_SW_MUTEX_REQUEST field is
> cleared.
So second concurrent write to I2C_SW_MUTEX_REQUEST will fail silently,
and you rely on below check which ID succeeded to write?
If that is how it works, then should succeed... except the trouble is
that you use here i2c_readl/writel wrappers (which was already a poor
idea, because it hides the implementation for no real gain) and it turns
out they happen to be relaxed making all your assumptions about ordering
inaccurate. You need to switch to non-relaxed API.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-01-30 17:49 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-30 14:34 [PATCH v2 0/5] Add I2C support for Tegra264 Kartik Rajput
2025-01-30 14:34 ` [PATCH v2 1/5] dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C Kartik Rajput
2025-01-30 16:14 ` Krzysztof Kozlowski
2025-01-30 14:34 ` [PATCH v2 2/5] i2c: tegra: Do not configure DMA if not supported Kartik Rajput
2025-01-30 14:34 ` [PATCH v2 3/5] i2c: tegra: Add HS mode support Kartik Rajput
2025-01-30 14:34 ` [PATCH v2 4/5] i2c: tegra: Add support for SW mutex register Kartik Rajput
2025-01-30 16:12 ` Krzysztof Kozlowski
2025-01-30 16:35 ` Kartik Rajput
2025-01-30 17:49 ` Krzysztof Kozlowski [this message]
2025-01-31 6:46 ` Kartik Rajput
2025-01-30 14:34 ` [PATCH v2 5/5] i2c: tegra: Add Tegra264 support Kartik Rajput
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