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From: Eric Anholt <eric@anholt.net>
To: Annaliese McDermond <nh6z@nh6z.net>
Cc: Stefan Wahren <stefan.wahren@i2se.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	swarren@wwwdotorg.org, wsa@the-dreams.de,
	team@nwdigitalradio.com, linux-rpi-kernel@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org
Subject: Re: [PATCH] i2c: bcm2835: Model Divider in CCF
Date: Mon, 06 May 2019 21:32:29 -0700	[thread overview]
Message-ID: <878svivq8y.fsf@anholt.net> (raw)
In-Reply-To: <C611AB4D-7674-438D-BB95-9F83852043EA@nh6z.net>


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Annaliese McDermond <nh6z@nh6z.net> writes:

>> On May 6, 2019, at 11:14 AM, Eric Anholt <eric@anholt.net> wrote:
>> 
>> Annaliese McDermond <nh6z@nh6z.net> writes:
>> 
>>> Model the I2C bus clock divider as a part of the Core Clock Framework.
>>> Primarily this removes the clk_get_rate() call from each transfer.
>>> This call causes problems for slave drivers that themselves have
>>> internal clock components that are controlled by an I2C interface.
>>> When the slave's internal clock component is prepared, the prepare
>>> lock is obtained, and it makes calls to the I2C subsystem to
>>> command the hardware to activate the clock.  In order to perform
>>> the I2C transfer, this driver sets the divider, which requires
>>> it to get the parent clock rate, which it does with clk_get_rate().
>>> Unfortunately, this function will try to take the clock prepare
>>> lock, which is already held by the slave's internal clock calls
>>> creating a deadlock.
>>> 
>>> Modeling the divider in the CCF natively removes this dependency
>>> and the divider value is only set upon changing the bus clock
>>> frequency or changes in the parent clock that cascade down to this
>>> divisor.  This obviates the need to set the divider with every
>>> transfer and avoids the deadlock described above.  It also should
>>> provide better clock debugging and save a few cycles on each
>>> transfer due to not having to recalcuate the divider value.
>> 
>> Any chance we could reuse clk_register_divider() instead of having our
>> own set/round/recalc rate implementations?
>
> Eric --
>
> I’d love to, but the set_rate implementation includes setting the
> BCM2835_I2C_FEDL_SHIFT and BCM2835_I2C_REDL_SHIFT registers for the 
> rising and falling edge delay on the I2C bus based on what the divider
> value is.

Hmm.  I ran into that in clk-bcm2835.c as well, and the solution was
that bcm2835_register_pll_divider() sets up the divider structure and
then reuses clk_divider_ops.round_rate() and .recalc_rate()

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  reply	other threads:[~2019-05-07  4:32 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-05  3:43 [PATCH] i2c: bcm2835: Model Divider in CCF Annaliese McDermond
2019-05-05 10:36 ` Stefan Wahren
     [not found]   ` <610c7594-85c9-72db-63a6-6e632e9586aa-eS4NqCHxEME@public.gmane.org>
2019-05-05 17:13     ` Florian Fainelli
2019-05-05 17:21       ` Annaliese McDermond
2019-05-06 15:59       ` Nicolas Saenz Julienne
2019-05-05 17:16   ` Annaliese McDermond
2019-05-06 18:14 ` Eric Anholt
2019-05-06 22:56   ` Annaliese McDermond
2019-05-07  4:32     ` Eric Anholt [this message]
2019-05-07 13:10       ` Annaliese McDermond
2019-05-07  6:11 ` Stefan Wahren

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