[PATCH i2c-next 0/2] i2c: mlxcpld: Extend driver functionality and allow to run on ARM64

[PATCH i2c-next 0/2] i2c: mlxcpld: Extend driver functionality and allow to run on ARM64

[Vadim Pasternak]

The patch set contains:
Patch #1 – add dependency on ARM64.
Patch #2 – adds support for 128 bytes transaction data buffer.

Vadim Pasternak (2):
  i2c: mlxcpld: Allow driver to run on ARM64 architecture
  i2c: mlxcpld: Add support for extended transaction length

 drivers/i2c/busses/Kconfig       |  2 +-
 drivers/i2c/busses/i2c-mlxcpld.c | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

-- 
2.20.1

[PATCH i2c-next 1/2] i2c: mlxcpld: Allow driver to run on ARM64 architecture

[Vadim Pasternak]

Extend driver dependency by ARM64 architecture.

Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
Reviewed-by: Michael Shych <michaelsh@nvidia.com>
---
 drivers/i2c/busses/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 9cfe8fc509d7..169607e80331 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1384,7 +1384,7 @@ config I2C_ICY
 
 config I2C_MLXCPLD
 	tristate "Mellanox I2C driver"
-	depends on X86_64 || COMPILE_TEST
+	depends on X86_64 || ARM64 || COMPILE_TEST
 	help
 	  This exposes the Mellanox platform I2C busses to the linux I2C layer
 	  for X86 based systems.
-- 
2.20.1

Re: [PATCH i2c-next 1/2] i2c: mlxcpld: Allow driver to run on ARM64 architecture

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 262 bytes --]

On Tue, Aug 22, 2023 at 06:51:36PM +0000, Vadim Pasternak wrote:
> Extend driver dependency by ARM64 architecture.
> 
> Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
> Reviewed-by: Michael Shych <michaelsh@nvidia.com>

Applied to for-next, thanks!


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[PATCH i2c-next 2/2] i2c: mlxcpld: Add support for extended transaction length

[Vadim Pasternak]

Add support for extended length of read and write transactions.
New FPGA logic allows to increase size of the read and write
transactions length. This feature is verified through capability
register 'CPBLTY_REG'. Two bits 5 and 6 of the register are used for
length capability detection. Value '10' indicates support of extended
transaction length - 128 bytes for read transactions and 132 for write
transactions.

Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
Reviewed-by: Michael Shych <michaelsh@nvidia.com>
---
 drivers/i2c/busses/i2c-mlxcpld.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c
index c42fd4b329e4..6fec64ea67fb 100644
--- a/drivers/i2c/busses/i2c-mlxcpld.c
+++ b/drivers/i2c/busses/i2c-mlxcpld.c
@@ -22,6 +22,7 @@
 #define MLXCPLD_I2C_BUS_NUM		1
 #define MLXCPLD_I2C_DATA_REG_SZ		36
 #define MLXCPLD_I2C_DATA_SZ_BIT		BIT(5)
+#define MLXCPLD_I2C_DATA_EXT2_SZ_BIT	BIT(6)
 #define MLXCPLD_I2C_DATA_SZ_MASK	GENMASK(6, 5)
 #define MLXCPLD_I2C_SMBUS_BLK_BIT	BIT(7)
 #define MLXCPLD_I2C_MAX_ADDR_LEN	4
@@ -466,6 +467,13 @@ static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext = {
 	.max_comb_1st_msg_len = 4,
 };
 
+static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext2 = {
+	.flags = I2C_AQ_COMB_WRITE_THEN_READ,
+	.max_read_len = (MLXCPLD_I2C_DATA_REG_SZ - 4) * 4,
+	.max_write_len = (MLXCPLD_I2C_DATA_REG_SZ - 4) * 4 + MLXCPLD_I2C_MAX_ADDR_LEN,
+	.max_comb_1st_msg_len = 4,
+};
+
 static struct i2c_adapter mlxcpld_i2c_adapter = {
 	.owner          = THIS_MODULE,
 	.name           = "i2c-mlxcpld",
@@ -547,6 +555,8 @@ static int mlxcpld_i2c_probe(struct platform_device *pdev)
 	/* Check support for extended transaction length */
 	if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_SZ_BIT)
 		mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext;
+	else if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_EXT2_SZ_BIT)
+		mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext2;
 	/* Check support for smbus block transaction */
 	if (val & MLXCPLD_I2C_SMBUS_BLK_BIT)
 		priv->smbus_block = true;
-- 
2.20.1

Re: [PATCH i2c-next 2/2] i2c: mlxcpld: Add support for extended transaction length

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 646 bytes --]

On Tue, Aug 22, 2023 at 06:51:37PM +0000, Vadim Pasternak wrote:
> Add support for extended length of read and write transactions.
> New FPGA logic allows to increase size of the read and write
> transactions length. This feature is verified through capability
> register 'CPBLTY_REG'. Two bits 5 and 6 of the register are used for
> length capability detection. Value '10' indicates support of extended
> transaction length - 128 bytes for read transactions and 132 for write
> transactions.
> 
> Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
> Reviewed-by: Michael Shych <michaelsh@nvidia.com>

Applied to for-next, thanks!


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