From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Cc: Jean Delvare <jdelvare@suse.com>,
Andi Shyti <andi.shyti@kernel.org>,
linux-i2c@vger.kernel.org, Sanket.Goswami@amd.com
Subject: Re: [PATCH v3 3/5] i2c: piix4: Add ACPI support for ASF SMBus device
Date: Fri, 6 Sep 2024 17:40:37 +0300 [thread overview]
Message-ID: <ZtsUZfxeE8Tqf1OD@smile.fi.intel.com> (raw)
In-Reply-To: <cdc294e7-a78d-4a3e-a2fd-2122a8ea9660@amd.com>
On Fri, Sep 06, 2024 at 06:50:48PM +0530, Shyam Sundar S K wrote:
> On 9/6/2024 17:54, Andy Shevchenko wrote:
> > On Fri, Sep 06, 2024 at 12:41:59PM +0530, Shyam Sundar S K wrote:
First of all, you haven't replied to some of my comments, I assume that you
agree on them and are going to fix as suggested?
...
> >> The AMD ASF controller is presented to the operating system as an ACPI
> >> device. The piix4 driver can obtain the ASF handle through ACPI to
> >> retrieve information about the ASF controller's attributes, such as the
> >> ASF address space and interrupt number, and to handle ASF interrupts.
> >
> > Can you share an excerpt of DSDT to see how it looks like?
>
> Device (ASFC)
> {
> ...
Can you put the necessary bits for the enumeration (you may replace some IDs if
they are not public yet to something like XX..XX or xx..xx)?
> Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
> {
> Name (ASBB, ResourceTemplate ()
> {
> Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
> {
> 0x00000014,
> }
> IO (Decode16,
> 0x0B20, // Range Minimum
> 0x0B20, // Range Maximum
Typo in value? Shouldn't this be 0x0b3f?
> 0x00, // Alignment
> 0x20, // Length
> )
> Memory32Fixed (ReadWrite,
> 0xFEC00040, // Address Base
> 0x00000100, // Address Length
> )
> })
> Return (ASBB) /* \_SB_.ASFC._CRS.ASBB */
> }
> ...
> }
...
> >> Additionally, include a 'depends on X86' Kconfig entry for
> >> CONFIG_I2C_PIIX4, as the current patch utilizes acpi_dev_get_resources(),
> >> which is compiled only when CONFIG_ACPI is enabled, and CONFIG_ACPI
> >> depends on CONFIG_X86.
> >
> > Yeah, please don't do that. If it requires ACPI, make it clear, there is
> > no x86 compile-time dependency.
>
> You mean to say make the dependencies as:
>
> depends on PCI && HAS_IOPORT && ACPI
>
> instead of:
>
> depends on PCI && HAS_IOPORT && X86
Yes, but see below as well about the stubs
~~~vvv
> > Second issue with this is that now you require entire ACPI machinery for
> > the previous cases where it wasn't needed. Imagine an embedded system with
> > limited amount of memory for which you require +1Mbyte just for nothing.
> >
> > Look how the other do (hint: ifdeffery in the code with stubs).
___^^^
...
> >> + u8 bank, reg, cmd = 0;
> >
> > Move cmd assignment into the respective branch of the conditional below, in
> > that case it will be closer and more symmetrical.
>
> meaning, make the cmd assignment only in the if() case.
Yes.
> Not sure if I understand your remark completely.
if (...) {
cmd = 0;
} else {
cmd = ...
}
...
> >> + if (slave_int & BIT(6)) {
> >> + /* Slave Interrupt */
> >> + outb_p(slave_int | BIT(6), ASFSTA);
> >> + schedule_delayed_work(&adapdata->work_buf, HZ);
> >> + } else {
> >> + /* Master Interrupt */
> >
> > Please, start using inclusive non-offensive terms instead of old 'master/slave'
> > terminology. Nowadays it's a part of the standard AFAIU.
>
> OK. I get it ( tried to retain the names as mentioned in the AMD ASF
> databook).
>
> Which one would you advise (instead of master/slave)?
As per official I2C specification. :-)
> Primary/secondary
> Controller/Worker
> Requester/Responder
See, e.g., a93c2e5fe766 ("i2c: reword i2c_algorithm according to newest specification").
> > Note, I'm talking only about comments and messages, the APIs is another story
> > that should be addressed separately.
> >
> >> + sb800_asf_update_bits(piix4_smba, SB800_ASF_SLV_INTR, SMBHSTSTS, true);
> >> + }
...
> >> + status = acpi_get_handle(NULL, SB800_ASF_ACPI_PATH, &handle);
> >> + if (ACPI_FAILURE(status))
> >> + return -ENODEV;
> >> +
> >> + adev = acpi_fetch_acpi_dev(handle);
> >> + if (!adev)
> >> + return -ENODEV;
> >
> > This approach I don't like. I would like to see DSDT for that
> > as I mentioned above.
>
> I have posted the DSDT. Can you please elaborate your remarks?
Not that parts that affect this...
...
> >> + ret = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
> >> + if (ret < 0) {
> >
> >> + dev_err(&dev->dev, "Error getting ASF ACPI resource: %d\n", ret);
> >> + return ret;
> >
> > return dev_err_probe(...);
>
> I thought dev_err_probe(...); is called only from the .probe
> functions. Is that not the case?
I assume you call this due to use of devm_*(). Either devm_*() should be
replaced to non-devm_*() analogues, or these moved to dev_err_probe().
> In the current proposed change, sb800_asf_add_adap() gets called from
> *_probe().
>
> Or you mean to say, no need for a error print and just do a error return?
No. It's also possible, but this is up to you.
> if (ret < 0)
> return ret;
>
> Likewise for below remarks on dev_err_probe(...);
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2024-09-06 14:40 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-06 7:11 [PATCH v3 0/5] Introduce AMD ASF Controller Support to the i2c-piix4 driver Shyam Sundar S K
2024-09-06 7:11 ` [PATCH v3 1/5] i2c: piix4: Allow more than two algo selection for SMBus Shyam Sundar S K
2024-09-06 7:11 ` [PATCH v3 2/5] i2c: piix4: Add i2c_algorithm operations to support AMD ASF with SMBus Shyam Sundar S K
2024-09-06 7:11 ` [PATCH v3 3/5] i2c: piix4: Add ACPI support for ASF SMBus device Shyam Sundar S K
2024-09-06 12:24 ` Andy Shevchenko
2024-09-06 13:20 ` Shyam Sundar S K
2024-09-06 14:40 ` Andy Shevchenko [this message]
2024-09-06 15:11 ` Shyam Sundar S K
2024-09-06 16:04 ` Andy Shevchenko
2024-09-06 18:51 ` Shyam Sundar S K
2024-09-11 11:58 ` Shyam Sundar S K
2024-09-07 2:49 ` kernel test robot
2024-09-06 7:12 ` [PATCH v3 4/5] i2c: piix4: Adjust the SMBus debug message Shyam Sundar S K
2024-09-06 7:12 ` [PATCH v3 5/5] i2c: piix4: Clear remote IRR bit to get successive interrupt Shyam Sundar S K
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