Re: [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss

[Krzysztof Kozlowski <krzk@kernel.org>]

On 06/01/2026 19:40, Vijay Kumar Tumati wrote:
> 
> On 11/27/2025 12:12 AM, Krzysztof Kozlowski wrote:
>> On Wed, Nov 26, 2025 at 01:38:40AM -0800, Hangxiang Ma wrote:
>>   +
>>> +			cci1_1_default: cci1-1-default-state {
>>> +				sda-pins {
>>> +					pins = "gpio111";
>>> +					function = "cci_i2c_sda";
>>> +					drive-strength = <2>;
>>> +					bias-pull-up;
>>> +				};
>>> +
>>> +				scl-pins {
>>> +					pins = "gpio164";
>>> +					function = "cci_i2c_scl";
>>> +					drive-strength = <2>;
>>> +					bias-pull-up;
>>> +				};
>>> +			};
>>> +
>>> +			cci1_1_sleep: cci1-1-sleep-state {
>>> +				sda-pins {
>>> +					pins = "gpio111";
>>> +					function = "cci_i2c_sda";
>>> +					drive-strength = <2>;
>>> +					bias-pull-down;
>>> +				};
>>> +
>>> +				scl-pins {
>>> +					pins = "gpio164";
>>> +					function = "cci_i2c_scl";
>>> +					drive-strength = <2>;
>>> +					bias-pull-down;
>>> +				};
>>> +			};
>>> +
>>> +			cci2_0_default: cci2-0-default-state {
>>> +				sda-pins {
>>> +					pins = "gpio112";
>>> +					function = "cci_i2c_sda";
>>> +					drive-strength = <2>;
>>> +					bias-pull-up;
>>> +				};
>>> +
>>> +				scl-pins {
>>> +					pins = "gpio153";
>>> +					function = "cci_i2c_scl";
>>> +					drive-strength = <2>;
>>> +					bias-pull-up;
>>> +				};
>>> +			};
>>> +
>>> +			cci2_0_sleep: cci2-0-sleep-state {
>>> +				sda-pins {
>>> +					pins = "gpio112";
>>> +					function = "cci_i2c_sda";
>>> +					drive-strength = <2>;
>>> +					bias-pull-down;
>>> +				};
>>> +
>>> +				scl-pins {
>>> +					pins = "gpio153";
>>> +					function = "cci_i2c_scl";
>>> +					drive-strength = <2>;
>>> +					bias-pull-down;
>>> +				};
>>> +			};
>>> +
>>> +			cci2_1_default: cci2-1-default-state {
>>> +				sda-pins {
>>> +					pins = "gpio119";
>>> +					function = "cci_i2c_sda";
>>> +					drive-strength = <2>;
>>> +					bias-pull-up;
>>> +				};
>>> +
>>> +				scl-pins {
>>> +					pins = "gpio120";
>>> +					function = "cci_i2c_scl";
>>> +					drive-strength = <2>;
>>> +					bias-pull-up;
>>> +				};
>>> +			};
>>> +
>>> +			cci2_1_sleep: cci2-1-sleep-state {
>>> +				sda-pins {
>>> +					pins = "gpio119";
>>> +					function = "cci_i2c_sda";
>>> +					drive-strength = <2>;
>>> +					bias-pull-down;
>>> +				};
>>> +
>>> +				scl-pins {
>>> +					pins = "gpio120";
>>> +					function = "cci_i2c_scl";
>>> +					drive-strength = <2>;
>>> +					bias-pull-down;
>>> +				};
>>> +			};
>>> +		};
>>> +
>>> +		cci0: cci@ac7b000 {
>> Looks completely mis-ordered/sorted. What are the nodes above and below?
> Hi Krzysztof, sorry, not sure how you mean exactly. The ones above are 
> the pinctrl nodes. Each CCI has two masters using two GPIOs each, one 

Why would pinctrl nodes matter anyhow? Please read how DTS syntax works.

> for clk and one for data. The ones below are the actual CCI HW nodes 
> that make use of the pinctrls. I believe this is inline with previous 
> generations. Have I missed something? Thanks.
I wrote what is wrong. Is this maintaining proper sorting? Did you read
DTS coding style?


Best regards,
Krzysztof