[PATCH v2 0/2] Add I2C support for IPQ5424

[PATCH v2 0/2] Add I2C support for IPQ5424

[Manikanta Mylavarapu]

Serial engines 2 and 3 on the IPQ5424 support I2C. The I2C instance
operates on serial engine 2, designated as i2c0, and on serial engine 3,
designated as i2c1. Add both the i2c nodes.

v2: * Remove assigned-clock and add opp table to configure the frequency of se clock.
    * Add opp table support in the GENI I2C driver and reordered variable declarations
      in geni_i2c_probe() using reverse Xmas order.

v1: https://lore.kernel.org/linux-arm-msm/20250711111418.3980520-1-quic_mmanikan@quicinc.com/

Manikanta Mylavarapu (2):
  i2c: qcom-geni: add OPP table support
  arm64: dts: qcom: ipq5424: add i2c nodes

 arch/arm64/boot/dts/qcom/ipq5424.dtsi | 28 +++++++++++++++++++++++++++
 drivers/i2c/busses/i2c-qcom-geni.c    | 27 +++++++++++++++++++++++---
 2 files changed, 52 insertions(+), 3 deletions(-)


base-commit: 33bcf93b9a6b028758105680f8b538a31bc563cf
-- 
2.34.1

[PATCH v2 1/2] i2c: qcom-geni: add OPP table support

[Manikanta Mylavarapu]

Add support for reading and configuring the OPP table in the GENI I2C
driver. This enables setting the frequency based on device tree data,
removing dependency on bootloader configuration.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
---
 drivers/i2c/busses/i2c-qcom-geni.c | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index ff2289b52c84..85b7f25e0c6e 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/pm_opp.h>
 #include <linux/pm_runtime.h>
 #include <linux/soc/qcom/geni-se.h>
 #include <linux/spinlock.h>
@@ -779,11 +780,13 @@ static int setup_gpi_dma(struct geni_i2c_dev *gi2c)
 
 static int geni_i2c_probe(struct platform_device *pdev)
 {
-	struct geni_i2c_dev *gi2c;
+	const struct geni_i2c_desc *desc = NULL;
 	u32 proto, tx_depth, fifo_disable;
-	int ret;
 	struct device *dev = &pdev->dev;
-	const struct geni_i2c_desc *desc = NULL;
+	unsigned long freq = ULONG_MAX;
+	struct geni_i2c_dev *gi2c;
+	struct dev_pm_opp *opp;
+	int ret;
 
 	gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
 	if (!gi2c)
@@ -814,6 +817,24 @@ static int geni_i2c_probe(struct platform_device *pdev)
 		gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ;
 	}
 
+	ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
+	if (ret)
+		return ret;
+
+	/* OPP table is optional */
+	ret = devm_pm_opp_of_add_table(dev);
+	if (!ret) {
+		opp = dev_pm_opp_find_freq_floor(dev, &freq);
+		if (IS_ERR(opp))
+			return dev_err_probe(dev, PTR_ERR(opp), "failed to find the frequency\n");
+		dev_pm_opp_put(opp);
+		ret = dev_pm_opp_set_rate(dev, freq);
+		if (ret)
+			return dev_err_probe(dev, ret, "failed to set the rate=%ld\n", freq);
+	} else if (ret && ret != -ENODEV) {
+		return dev_err_probe(&pdev->dev, ret, "invalid OPP table in device tree\n");
+	}
+
 	if (has_acpi_companion(dev))
 		ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
 
-- 
2.34.1

Re: [PATCH v2 1/2] i2c: qcom-geni: add OPP table support

[Andi Shyti]

Hi Manikanta,

...

> @@ -814,6 +817,24 @@ static int geni_i2c_probe(struct platform_device *pdev)
>  		gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ;
>  	}
>  
> +	ret = devm_pm_opp_set_clkname(&pdev->dev, "se");

/&pdev->dev/dev/

> +	if (ret)
> +		return ret;
> +
> +	/* OPP table is optional */
> +	ret = devm_pm_opp_of_add_table(dev);
> +	if (!ret) {
> +		opp = dev_pm_opp_find_freq_floor(dev, &freq);
> +		if (IS_ERR(opp))
> +			return dev_err_probe(dev, PTR_ERR(opp), "failed to find the frequency\n");
> +		dev_pm_opp_put(opp);
> +		ret = dev_pm_opp_set_rate(dev, freq);
> +		if (ret)
> +			return dev_err_probe(dev, ret, "failed to set the rate=%ld\n", freq);

%lu

Thanks,
Andi

> +	} else if (ret && ret != -ENODEV) {

Re: [PATCH v2 1/2] i2c: qcom-geni: add OPP table support

[Manikanta Mylavarapu]

On 9/5/2025 3:57 AM, Andi Shyti wrote:
>> @@ -814,6 +817,24 @@ static int geni_i2c_probe(struct platform_device *pdev)
>>  		gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ;
>>  	}
>>  
>> +	ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
> 
> /&pdev->dev/dev/
> 

Hi Andi,

Okay, sure. I will update in the next version.

>> +	if (ret)
>> +		return ret;
>> +
>> +	/* OPP table is optional */
>> +	ret = devm_pm_opp_of_add_table(dev);
>> +	if (!ret) {
>> +		opp = dev_pm_opp_find_freq_floor(dev, &freq);
>> +		if (IS_ERR(opp))
>> +			return dev_err_probe(dev, PTR_ERR(opp), "failed to find the frequency\n");
>> +		dev_pm_opp_put(opp);
>> +		ret = dev_pm_opp_set_rate(dev, freq);
>> +		if (ret)
>> +			return dev_err_probe(dev, ret, "failed to set the rate=%ld\n", freq);
> 
> %lu
> 

Okay, sure. I will update in the next version.

Thanks & Regards,
Manikanta.

[PATCH v2 2/2] arm64: dts: qcom: ipq5424: add i2c nodes

[Manikanta Mylavarapu]

Serial engines 2 and 3 on the IPQ5424 support I2C. The I2C instance
operates on serial engine 2, designated as i2c0, and on serial engine 3,
designated as i2c1. Add both the i2c0 and i2c1 nodes.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
---
v2: Remove assigned-clock and add opp table to configure the frequency of se clock

 arch/arm64/boot/dts/qcom/ipq5424.dtsi | 28 +++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 67877fbbdf3a..0d8ea9a8c600 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -173,6 +173,14 @@ memory@80000000 {
 		reg = <0x0 0x80000000 0x0 0x0>;
 	};
 
+	i2c_opp_table_64mhz: opp-table-qup64mhz {
+		compatible = "operating-points-v2";
+
+		opp-64000000 {
+			opp-hz = /bits/ 64 <64000000>;
+		};
+	};
+
 	pmu-a55 {
 		compatible = "arm,cortex-a55-pmu";
 		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -519,6 +527,26 @@ uart1: serial@1a84000 {
 				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
+			i2c0: i2c@1a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x01a88000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+				operating-points-v2 = <&i2c_opp_table_64mhz>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@1a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x01a8c000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_I2C1_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+				operating-points-v2 = <&i2c_opp_table_64mhz>;
+				status = "disabled";
+			};
+
 			spi0: spi@1a90000 {
 				compatible = "qcom,geni-spi";
 				reg = <0 0x01a90000 0 0x4000>;
-- 
2.34.1

Re: [PATCH v2 2/2] arm64: dts: qcom: ipq5424: add i2c nodes

[Konrad Dybcio]

On 9/3/25 10:09 AM, Manikanta Mylavarapu wrote:
> Serial engines 2 and 3 on the IPQ5424 support I2C. The I2C instance
> operates on serial engine 2, designated as i2c0, and on serial engine 3,
> designated as i2c1. Add both the i2c0 and i2c1 nodes.
> 
> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad