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* [PATCH 0/1] Cadence I3C Status Register Bit Mask Error
@ 2023-09-11  8:16 Joshua Yeong
  2023-09-11  8:16 ` [PATCH 1/1] i3c: master: cdns: Fix reading status register Joshua Yeong
  0 siblings, 1 reply; 3+ messages in thread
From: Joshua Yeong @ 2023-09-11  8:16 UTC (permalink / raw)
  To: pgaj; +Cc: alexandre.belloni, linux-i3c, linux-kernel, Joshua Yeong

I3C ibirfifodepth and cmdrfifodepth field should read from status0 instead of
status1. Update I3C slave macro.

Joshua Yeong (1):
  i3c: master: cdns: Fix reading status register

 drivers/i3c/master/i3c-master-cdns.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

--
2.25.1


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^ permalink raw reply	[flat|nested] 3+ messages in thread
* [PATCH 1/1] i3c: master: cdns: Fix reading status register
  2023-09-11  8:16 [PATCH 0/1] Cadence I3C Status Register Bit Mask Error Joshua Yeong
@ 2023-09-11  8:16 ` Joshua Yeong
  2023-09-12 10:57   ` Miquel Raynal
  0 siblings, 1 reply; 3+ messages in thread
From: Joshua Yeong @ 2023-09-11  8:16 UTC (permalink / raw)
  To: pgaj; +Cc: alexandre.belloni, linux-i3c, linux-kernel, Joshua Yeong

IBIR_DEPTH and CMDR_DEPTH should read from status0 instead of status1

Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
---
 drivers/i3c/master/i3c-master-cdns.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c
index 49551db71bc9..8f1fda3c7ac5 100644
--- a/drivers/i3c/master/i3c-master-cdns.c
+++ b/drivers/i3c/master/i3c-master-cdns.c
@@ -191,7 +191,7 @@
 #define SLV_STATUS1_HJ_DIS		BIT(18)
 #define SLV_STATUS1_MR_DIS		BIT(17)
 #define SLV_STATUS1_PROT_ERR		BIT(16)
-#define SLV_STATUS1_DA(x)		(((s) & GENMASK(15, 9)) >> 9)
+#define SLV_STATUS1_DA(s)		(((s) & GENMASK(15, 9)) >> 9)
 #define SLV_STATUS1_HAS_DA		BIT(8)
 #define SLV_STATUS1_DDR_RX_FULL		BIT(7)
 #define SLV_STATUS1_DDR_TX_FULL		BIT(6)
@@ -1623,13 +1623,13 @@ static int cdns_i3c_master_probe(struct platform_device *pdev)
 	/* Device ID0 is reserved to describe this master. */
 	master->maxdevs = CONF_STATUS0_DEVS_NUM(val);
 	master->free_rr_slots = GENMASK(master->maxdevs, 1);
+	master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
+	master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);
 
 	val = readl(master->regs + CONF_STATUS1);
 	master->caps.cmdfifodepth = CONF_STATUS1_CMD_DEPTH(val);
 	master->caps.rxfifodepth = CONF_STATUS1_RX_DEPTH(val);
 	master->caps.txfifodepth = CONF_STATUS1_TX_DEPTH(val);
-	master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
-	master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);
 
 	spin_lock_init(&master->ibi.lock);
 	master->ibi.num_slots = CONF_STATUS1_IBI_HW_RES(val);
-- 
2.25.1


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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] i3c: master: cdns: Fix reading status register
  2023-09-11  8:16 ` [PATCH 1/1] i3c: master: cdns: Fix reading status register Joshua Yeong
@ 2023-09-12 10:57   ` Miquel Raynal
  0 siblings, 0 replies; 3+ messages in thread
From: Miquel Raynal @ 2023-09-12 10:57 UTC (permalink / raw)
  To: Joshua Yeong; +Cc: pgaj, alexandre.belloni, linux-i3c, linux-kernel

Hi Joshua,

joshua.yeong@starfivetech.com wrote on Mon, 11 Sep 2023 16:16:24 +0800:

> IBIR_DEPTH and CMDR_DEPTH should read from status0 instead of status1

				  be

Missing '.' at the end.

Missing Fixes: tag as well as Cc: stable.

> 
> Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
> ---
>  drivers/i3c/master/i3c-master-cdns.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c
> index 49551db71bc9..8f1fda3c7ac5 100644
> --- a/drivers/i3c/master/i3c-master-cdns.c
> +++ b/drivers/i3c/master/i3c-master-cdns.c
> @@ -191,7 +191,7 @@
>  #define SLV_STATUS1_HJ_DIS		BIT(18)
>  #define SLV_STATUS1_MR_DIS		BIT(17)
>  #define SLV_STATUS1_PROT_ERR		BIT(16)
> -#define SLV_STATUS1_DA(x)		(((s) & GENMASK(15, 9)) >> 9)
> +#define SLV_STATUS1_DA(s)		(((s) & GENMASK(15, 9)) >> 9)
>  #define SLV_STATUS1_HAS_DA		BIT(8)
>  #define SLV_STATUS1_DDR_RX_FULL		BIT(7)
>  #define SLV_STATUS1_DDR_TX_FULL		BIT(6)
> @@ -1623,13 +1623,13 @@ static int cdns_i3c_master_probe(struct platform_device *pdev)
>  	/* Device ID0 is reserved to describe this master. */
>  	master->maxdevs = CONF_STATUS0_DEVS_NUM(val);
>  	master->free_rr_slots = GENMASK(master->maxdevs, 1);
> +	master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
> +	master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);
>  
>  	val = readl(master->regs + CONF_STATUS1);
>  	master->caps.cmdfifodepth = CONF_STATUS1_CMD_DEPTH(val);
>  	master->caps.rxfifodepth = CONF_STATUS1_RX_DEPTH(val);
>  	master->caps.txfifodepth = CONF_STATUS1_TX_DEPTH(val);
> -	master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
> -	master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);
>  
>  	spin_lock_init(&master->ibi.lock);
>  	master->ibi.num_slots = CONF_STATUS1_IBI_HW_RES(val);


Thanks,
Miquèl

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^ permalink raw reply	[flat|nested] 3+ messages in thread
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2023-09-11  8:16 [PATCH 0/1] Cadence I3C Status Register Bit Mask Error Joshua Yeong
2023-09-11  8:16 ` [PATCH 1/1] i3c: master: cdns: Fix reading status register Joshua Yeong
2023-09-12 10:57   ` Miquel Raynal

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