[PATCH 1/4] i3c: mipi-i3c-hci: Allow only relevant INTR_STATUS bit updates

[PATCH 1/4] i3c: mipi-i3c-hci: Allow only relevant INTR_STATUS bit updates

[Jarkko Nikula]

Since MIPI I3C HCI specification version v0.8 INTR_STATUS bits 9:0 are
reserved. Version v0.5 has bits 9 and 5:0 in use but not handled by the
current driver code and not needed in DMA transfers.

PIO transfers with v0.5 would require changes to both
core.c: i3c_hci_irq_handler() and pio.c: hci_pio_irq_handler() though.

For these reasons don't enable signal updates from INTR_STATUS bits 9:0.

This change is a no-op for specification versions v0.8 and beyond but
gets rid of "unexpected INTR_STATUS" errors if somebody (read me) wants
to run code on old v0.5 IP version.

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
---
 drivers/i3c/master/mipi-i3c-hci/core.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index a71226d7ca59..e139d7e4d252 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -699,9 +699,10 @@ static int i3c_hci_init(struct i3c_hci *hci)
 	if (ret)
 		return -ENXIO;
 
-	/* Disable all interrupts and allow all signal updates */
+	/* Disable all interrupts */
 	reg_write(INTR_SIGNAL_ENABLE, 0x0);
-	reg_write(INTR_STATUS_ENABLE, 0xffffffff);
+	/* Allow signal updates relevant to IP versions 0.8 and beyond */
+	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
 
 	/* Make sure our data ordering fits the host's */
 	regval = reg_read(HC_CONTROL);
-- 
2.47.2


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[PATCH 2/4] i3c: mipi-i3c-hci: Fix handling status of i3c_hci_irq_handler()

[Jarkko Nikula]

Return IRQ_HANDLED from the i3c_hci_irq_handler() only if some
INTR_STATUS bit was set or if DMA/PIO handler handled it.

Currently it returns IRQ_HANDLED in case INTR_STATUS is zero and IO
handler returns false. Which could be the case if interrupt comes from
other device or is spurious.

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
---
 drivers/i3c/master/mipi-i3c-hci/core.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index e139d7e4d252..e5593b6e897e 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -594,6 +594,7 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
 
 	if (val) {
 		reg_write(INTR_STATUS, val);
+		result = IRQ_HANDLED;
 	}
 
 	if (val & INTR_HC_RESET_CANCEL) {
@@ -605,12 +606,11 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
 		val &= ~INTR_HC_INTERNAL_ERR;
 	}
 
-	hci->io->irq_handler(hci);
+	if (hci->io->irq_handler(hci))
+		result = IRQ_HANDLED;
 
 	if (val)
 		dev_err(&hci->master.dev, "unexpected INTR_STATUS %#x\n", val);
-	else
-		result = IRQ_HANDLED;
 
 	return result;
 }
-- 
2.47.2


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Re: [PATCH 2/4] i3c: mipi-i3c-hci: Fix handling status of i3c_hci_irq_handler()

[Frank Li]

On Fri, Feb 28, 2025 at 04:18:00PM +0200, Jarkko Nikula wrote:
> Return IRQ_HANDLED from the i3c_hci_irq_handler() only if some
> INTR_STATUS bit was set or if DMA/PIO handler handled it.
>
> Currently it returns IRQ_HANDLED in case INTR_STATUS is zero and IO
> handler returns false. Which could be the case if interrupt comes from
> other device or is spurious.
>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
> ---
>  drivers/i3c/master/mipi-i3c-hci/core.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index e139d7e4d252..e5593b6e897e 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -594,6 +594,7 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
>
>  	if (val) {
>  		reg_write(INTR_STATUS, val);
> +		result = IRQ_HANDLED;

Not related this patch.
reg_write(INTR_STATUS, val); should be unconditional since INTR_STATUS is
w1c.

I am strange why need return IRQ_NONE case. I suppose it should always
return IRQ_HANDLED.

Frank
>  	}
>
>  	if (val & INTR_HC_RESET_CANCEL) {
> @@ -605,12 +606,11 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
>  		val &= ~INTR_HC_INTERNAL_ERR;
>  	}
>
> -	hci->io->irq_handler(hci);
> +	if (hci->io->irq_handler(hci))
> +		result = IRQ_HANDLED;
>
>  	if (val)
>  		dev_err(&hci->master.dev, "unexpected INTR_STATUS %#x\n", val);
> -	else
> -		result = IRQ_HANDLED;
>
>  	return result;
>  }
> --
> 2.47.2
>
>
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Re: [PATCH 2/4] i3c: mipi-i3c-hci: Fix handling status of i3c_hci_irq_handler()

[Jarkko Nikula]

Hi

On 2/28/25 6:14 PM, Frank Li wrote:
> On Fri, Feb 28, 2025 at 04:18:00PM +0200, Jarkko Nikula wrote:
>> Return IRQ_HANDLED from the i3c_hci_irq_handler() only if some
>> INTR_STATUS bit was set or if DMA/PIO handler handled it.
>>
>> Currently it returns IRQ_HANDLED in case INTR_STATUS is zero and IO
>> handler returns false. Which could be the case if interrupt comes from
>> other device or is spurious.
>>
>> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
>> ---
>>   drivers/i3c/master/mipi-i3c-hci/core.c | 6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
>> index e139d7e4d252..e5593b6e897e 100644
>> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
>> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
>> @@ -594,6 +594,7 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
>>
>>   	if (val) {
>>   		reg_write(INTR_STATUS, val);
>> +		result = IRQ_HANDLED;
> 
> Not related this patch.
> reg_write(INTR_STATUS, val); should be unconditional since INTR_STATUS is
> w1c.
> 
> I am strange why need return IRQ_NONE case. I suppose it should always
> return IRQ_HANDLED.
> 
This makes driver more ready for shared interrupts and let kernel 
interrupt code be able to disable bad behaving interrupt (misrouted, 
wrong polarity, etc) by returning IRQ_NONE when we know interrupt wasn't 
generated by this device.

Currently driver doesn't support shared interrupts since IRQF_SHARED 
flag is not passed to the devm_request_irq() call in i3c_hci_probe(). I 
didn't change that since I don't have a setup to test.

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[PATCH 3/4] i3c: mipi-i3c-hci: Change name of INTR_STATUS bit 11

[Jarkko Nikula]

INTR_STATUS bit 11 INTR_HC_RESET_CANCEL was probably projected for the
MIPI I3C HCI specification version 2 but was not ever implemented.

This bit is first time specified in the v1.2 as HC_SEQ_CANCEL_STAT
"Host Controller Cancelled Transaction Sequence". Update the definition
and debug print of it accordingly.

While at it, change DBG() print to dev_dbg().

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
---
 drivers/i3c/master/mipi-i3c-hci/core.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index e5593b6e897e..84c372740020 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -78,7 +78,7 @@
 #define INTR_SIGNAL_ENABLE		0x28
 #define INTR_FORCE			0x2c
 #define INTR_HC_CMD_SEQ_UFLOW_STAT	BIT(12)	/* Cmd Sequence Underflow */
-#define INTR_HC_RESET_CANCEL		BIT(11)	/* HC Cancelled Reset */
+#define INTR_HC_SEQ_CANCEL		BIT(11)	/* HC Cancelled Transaction Sequence */
 #define INTR_HC_INTERNAL_ERR		BIT(10)	/* HC Internal Error */
 
 #define DAT_SECTION			0x30	/* Device Address Table */
@@ -597,9 +597,10 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
 		result = IRQ_HANDLED;
 	}
 
-	if (val & INTR_HC_RESET_CANCEL) {
-		DBG("cancelled reset");
-		val &= ~INTR_HC_RESET_CANCEL;
+	if (val & INTR_HC_SEQ_CANCEL) {
+		dev_dbg(&hci->master.dev,
+			"Host Controller Cancelled Transaction Sequence\n");
+		val &= ~INTR_HC_SEQ_CANCEL;
 	}
 	if (val & INTR_HC_INTERNAL_ERR) {
 		dev_err(&hci->master.dev, "Host Controller Internal Error\n");
-- 
2.47.2


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[PATCH 4/4] i3c: mipi-i3c-hci: Move unexpected INTR_STATUS print before IO handler

[Jarkko Nikula]

Move "unexpected INTR_STATUS" error print before calling the IO handler
as it is more consistent that way. Otherwise it may be confusing if
generic interrupt related prints are mixed with IO handler prints.

Since this error print is more indication of missing code rather than
runtime error downgrade it to dev_warn_once().

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
---
 drivers/i3c/master/mipi-i3c-hci/core.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index 84c372740020..5c173249c0ac 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -607,12 +607,13 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
 		val &= ~INTR_HC_INTERNAL_ERR;
 	}
 
+	if (val)
+		dev_warn_once(&hci->master.dev,
+			      "unexpected INTR_STATUS %#x\n", val);
+
 	if (hci->io->irq_handler(hci))
 		result = IRQ_HANDLED;
 
-	if (val)
-		dev_err(&hci->master.dev, "unexpected INTR_STATUS %#x\n", val);
-
 	return result;
 }
 
-- 
2.47.2


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Re: [PATCH 4/4] i3c: mipi-i3c-hci: Move unexpected INTR_STATUS print before IO handler

[Frank Li]

On Fri, Feb 28, 2025 at 04:18:02PM +0200, Jarkko Nikula wrote:
> Move "unexpected INTR_STATUS" error print before calling the IO handler
> as it is more consistent that way. Otherwise it may be confusing if
> generic interrupt related prints are mixed with IO handler prints.
>
> Since this error print is more indication of missing code rather than
> runtime error downgrade it to dev_warn_once().
>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
>  drivers/i3c/master/mipi-i3c-hci/core.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index 84c372740020..5c173249c0ac 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -607,12 +607,13 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
>  		val &= ~INTR_HC_INTERNAL_ERR;
>  	}
>
> +	if (val)
> +		dev_warn_once(&hci->master.dev,
> +			      "unexpected INTR_STATUS %#x\n", val);
> +
>  	if (hci->io->irq_handler(hci))
>  		result = IRQ_HANDLED;
>
> -	if (val)
> -		dev_err(&hci->master.dev, "unexpected INTR_STATUS %#x\n", val);
> -
>  	return result;
>  }
>
> --
> 2.47.2
>
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Re: [PATCH 1/4] i3c: mipi-i3c-hci: Allow only relevant INTR_STATUS bit updates

[Frank Li]

On Fri, Feb 28, 2025 at 04:17:59PM +0200, Jarkko Nikula wrote:
> Since MIPI I3C HCI specification version v0.8 INTR_STATUS bits 9:0 are
> reserved. Version v0.5 has bits 9 and 5:0 in use but not handled by the
> current driver code and not needed in DMA transfers.
>
> PIO transfers with v0.5 would require changes to both
> core.c: i3c_hci_irq_handler() and pio.c: hci_pio_irq_handler() though.

If reasonable, why not change core.c and pio.c?

>
> For these reasons don't enable signal updates from INTR_STATUS bits 9:0.
>
> This change is a no-op for specification versions v0.8 and beyond but
> gets rid of "unexpected INTR_STATUS" errors if somebody (read me) wants
> to run code on old v0.5 IP version.

I think, simple said
"Get rid of "unexpected INTR_STATUS" errors at old v0.5 IP version and
no-op for version above v0.8."

>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
> ---
>  drivers/i3c/master/mipi-i3c-hci/core.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index a71226d7ca59..e139d7e4d252 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -699,9 +699,10 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  	if (ret)
>  		return -ENXIO;
>
> -	/* Disable all interrupts and allow all signal updates */
> +	/* Disable all interrupts */
>  	reg_write(INTR_SIGNAL_ENABLE, 0x0);
> -	reg_write(INTR_STATUS_ENABLE, 0xffffffff);
> +	/* Allow signal updates relevant to IP versions 0.8 and beyond */
> +	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));

Generally, just enable needed IRQ in driver. Define some BITS for
difference type IRQs.

Frank

>
>  	/* Make sure our data ordering fits the host's */
>  	regval = reg_read(HC_CONTROL);
> --
> 2.47.2
>
>
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Re: [PATCH 1/4] i3c: mipi-i3c-hci: Allow only relevant INTR_STATUS bit updates

[Jarkko Nikula]

Hi Frank

Sorry the delay, somehow I missed your comments to this patch :-|

On 2/28/25 6:00 PM, Frank Li wrote:
> On Fri, Feb 28, 2025 at 04:17:59PM +0200, Jarkko Nikula wrote:
>> Since MIPI I3C HCI specification version v0.8 INTR_STATUS bits 9:0 are
>> reserved. Version v0.5 has bits 9 and 5:0 in use but not handled by the
>> current driver code and not needed in DMA transfers.
>>
>> PIO transfers with v0.5 would require changes to both
>> core.c: i3c_hci_irq_handler() and pio.c: hci_pio_irq_handler() though.
> 
> If reasonable, why not change core.c and pio.c?
> 
I had two reasons for that. The v0.5 compatible IP I use in testing 
doesn't support PIO transfers and thus didn't want to add code that is 
not tested.

Then I believe perhaps nobody will release HW with this old IP and thus 
it would be dead code anyway.

>>
>> For these reasons don't enable signal updates from INTR_STATUS bits 9:0.
>>
>> This change is a no-op for specification versions v0.8 and beyond but
>> gets rid of "unexpected INTR_STATUS" errors if somebody (read me) wants
>> to run code on old v0.5 IP version.
> 
> I think, simple said
> "Get rid of "unexpected INTR_STATUS" errors at old v0.5 IP version and
> no-op for version above v0.8."
> 
Makes sense, will change.

>>
>> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
>> ---
>>   drivers/i3c/master/mipi-i3c-hci/core.c | 5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
>> index a71226d7ca59..e139d7e4d252 100644
>> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
>> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
>> @@ -699,9 +699,10 @@ static int i3c_hci_init(struct i3c_hci *hci)
>>   	if (ret)
>>   		return -ENXIO;
>>
>> -	/* Disable all interrupts and allow all signal updates */
>> +	/* Disable all interrupts */
>>   	reg_write(INTR_SIGNAL_ENABLE, 0x0);
>> -	reg_write(INTR_STATUS_ENABLE, 0xffffffff);
>> +	/* Allow signal updates relevant to IP versions 0.8 and beyond */
>> +	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
> 
> Generally, just enable needed IRQ in driver. Define some BITS for
> difference type IRQs.
> 
I was thinking too these need changes too but decided those are better 
to do in another patch(es).

Currently all of these generic interrupt sources are disabled so they 
won't generate interrupt but their status will be printed when handler 
is called due to DMA/PIO interrupt. Known bits 10 INTR_HC_INTERNAL_ERR 
and 11 INTR_HC_SEQ_CANCEL will print their message and unknowns just 
"unexpected INTR_STATUS" with hex of unhandled status bits.

Bits 12:14 can be defined since v1.2 describes them. I'm open for ideas 
does it make more sense to allow signal updates only from known sources 
or keep all bits enabled so that in future IP versions "unexpected 
INTR_STATUS" can be seen from user reports if something odd happens and 
driver is not yet handling that.

Another change is should known generic interrupt sources be enabled so 
handler will be called immediately when that condition occurs.

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Re: [PATCH 1/4] i3c: mipi-i3c-hci: Allow only relevant INTR_STATUS bit updates

[Frank Li]

On Fri, Mar 07, 2025 at 11:14:06AM +0200, Jarkko Nikula wrote:
> Hi Frank
>
> Sorry the delay, somehow I missed your comments to this patch :-|
>
> On 2/28/25 6:00 PM, Frank Li wrote:
> > On Fri, Feb 28, 2025 at 04:17:59PM +0200, Jarkko Nikula wrote:
> > > Since MIPI I3C HCI specification version v0.8 INTR_STATUS bits 9:0 are
> > > reserved. Version v0.5 has bits 9 and 5:0 in use but not handled by the
> > > current driver code and not needed in DMA transfers.
> > >
> > > PIO transfers with v0.5 would require changes to both
> > > core.c: i3c_hci_irq_handler() and pio.c: hci_pio_irq_handler() though.
> >
> > If reasonable, why not change core.c and pio.c?
> >
> I had two reasons for that. The v0.5 compatible IP I use in testing doesn't
> support PIO transfers and thus didn't want to add code that is not tested.
>
> Then I believe perhaps nobody will release HW with this old IP and thus it
> would be dead code anyway.
>
> > >
> > > For these reasons don't enable signal updates from INTR_STATUS bits 9:0.
> > >
> > > This change is a no-op for specification versions v0.8 and beyond but
> > > gets rid of "unexpected INTR_STATUS" errors if somebody (read me) wants
> > > to run code on old v0.5 IP version.
> >
> > I think, simple said
> > "Get rid of "unexpected INTR_STATUS" errors at old v0.5 IP version and
> > no-op for version above v0.8."
> >
> Makes sense, will change.
>
> > >
> > > Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
> > > ---
> > >   drivers/i3c/master/mipi-i3c-hci/core.c | 5 +++--
> > >   1 file changed, 3 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> > > index a71226d7ca59..e139d7e4d252 100644
> > > --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> > > +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> > > @@ -699,9 +699,10 @@ static int i3c_hci_init(struct i3c_hci *hci)
> > >   	if (ret)
> > >   		return -ENXIO;
> > >
> > > -	/* Disable all interrupts and allow all signal updates */
> > > +	/* Disable all interrupts */
> > >   	reg_write(INTR_SIGNAL_ENABLE, 0x0);
> > > -	reg_write(INTR_STATUS_ENABLE, 0xffffffff);
> > > +	/* Allow signal updates relevant to IP versions 0.8 and beyond */
> > > +	reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10));
> >
> > Generally, just enable needed IRQ in driver. Define some BITS for
> > difference type IRQs.
> >
> I was thinking too these need changes too but decided those are better to do
> in another patch(es).
>
> Currently all of these generic interrupt sources are disabled so they won't
> generate interrupt but their status will be printed when handler is called
> due to DMA/PIO interrupt. Known bits 10 INTR_HC_INTERNAL_ERR and 11
> INTR_HC_SEQ_CANCEL will print their message and unknowns just "unexpected
> INTR_STATUS" with hex of unhandled status bits.
>
> Bits 12:14 can be defined since v1.2 describes them. I'm open for ideas does
> it make more sense to allow signal updates only from known sources or keep
> all bits enabled so that in future IP versions "unexpected INTR_STATUS" can
> be seen from user reports if something odd happens and driver is not yet
> handling that.

I think we can defer it until someone really complain it. I am fine for
your current change.

Frank
>
> Another change is should known generic interrupt sources be enabled so
> handler will be called immediately when that condition occurs.
>
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