[PATCH v1 0/2] i3c: master: svc: Fix false SLVSTART issues on NPCM845

[PATCH v1 0/2] i3c: master: svc: Fix false SLVSTART issues on NPCM845

[Stanley Chu]

From: Stanley Chu <yschu@nuvoton.com>

The Nuvoton NPCM845 I3C controller has a hardware quirk
(SVC_I3C_QUIRK_FALSE_SLVSTART) where a spurious SLVSTART interrupt
may be generated. This series addresses two separate issues related to
this quirk:

1. A race condition where a real IBI arrives after MSTATUS is latched
   but before the SLVSTART status is cleared, causing the IRQ handler
   to return early on a stale snapshot and miss the pending IBI. Fixed
   by re-reading MSTATUS after clearing the interrupt status.

2. When a target holds SDA low, the controller reports a Master Request
   (MR). Emitting the required STOP condition in response spuriously
   sets SLVSTART again, re-entering the MR handler in a loop and causing
   an IRQ storm. Fixed by explicitly clearing SLVSTART after the STOP
   in the MR handler.

Stanley Chu (2):
  i3c: master: svc: Fix missed IBI after false SLVSTART on NPCM845
  i3c: master: svc: Prevent IRQ storm from false SLVSTART on NPCM845

 drivers/i3c/master/svc-i3c-master.c | 25 +++++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

-- 
2.34.1


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[PATCH v1 1/2] i3c: master: svc: Fix missed IBI after false SLVSTART on NPCM845

[Stanley Chu]

From: Stanley Chu <yschu@nuvoton.com>

The NPCM845 I3C controller may raise a false SLVSTART interrupt. The
handler first latches MSTATUS and then clears SLVSTART. If a real IBI
request arrives after the handler latches MSTATUS but before it clears
the SLVSTART interrupt status, HW sets the SLVREQ state. However, the
handler still relies on the stale MSTATUS snapshot, returns early, and
misses the real IBI. No further interrupt is generated for this pending
IBI.

Re-read MSTATUS to obtain the latest state and avoid missing a real IBI
due to this race condition.

Fixes: 4dd12e944f07 ("i3c: master: svc: Fix npcm845 invalid slvstart event")
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
 drivers/i3c/master/svc-i3c-master.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
index b84b324e4111..7d88e8fe3742 100644
--- a/drivers/i3c/master/svc-i3c-master.c
+++ b/drivers/i3c/master/svc-i3c-master.c
@@ -672,10 +672,18 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
 	/* Clear the interrupt status */
 	writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
 
-	/* Ignore the false event */
-	if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART) &&
-	    !SVC_I3C_MSTATUS_STATE_SLVREQ(active))
-		return IRQ_HANDLED;
+	if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART)) {
+		/*
+		 * Re-read MSTATUS to obtain the latest state and avoid
+		 * missing an IBI that arrives after MSTATUS is latched
+		 * but before SLVSTART is cleared.
+		 */
+		active = readl(master->regs + SVC_I3C_MSTATUS);
+
+		/* Ignore the false event */
+		if (!SVC_I3C_MSTATUS_STATE_SLVREQ(active))
+			return IRQ_HANDLED;
+	}
 
 	/*
 	 * The SDA line remains low until the request is processed.
-- 
2.34.1


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[PATCH v1 2/2] i3c: master: svc: Prevent IRQ storm from false SLVSTART on NPCM845

[Stanley Chu]

From: Stanley Chu <yschu@nuvoton.com>

On NPCM845, when a target on the I3C bus gets stuck holding SDA low,
the controller reports a false Master Request (MR) in-band interrupt
event. The driver handles this by emitting a STOP condition to restore
the bus.

However, the hardware quirk SVC_I3C_QUIRK_FALSE_SLVSTART indicates that
emitting a STOP condition may spuriously set the SLVSTART interrupt
status bit. In the Master Request case, this creates a feedback loop:
the STOP triggers a new SLVSTART event, the IRQ handler fires again,
the controller still reports an MR type, another STOP is emitted, and
the cycle repeats indefinitely, resulting in an IRQ storm that can lock
up the CPU.

Clear the SLVSTART status bit explicitly after emitting the STOP in the
Master Request IBI handler when the SVC_I3C_QUIRK_FALSE_SLVSTART quirk
is set. This breaks the feedback loop without affecting normal SLVSTART
processing, which is already guarded in the top-level IRQ handler by
checking that MSTATUS is in SLVREQ state.

Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
 drivers/i3c/master/svc-i3c-master.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
index 7d88e8fe3742..c16397013334 100644
--- a/drivers/i3c/master/svc-i3c-master.c
+++ b/drivers/i3c/master/svc-i3c-master.c
@@ -655,6 +655,15 @@ static void svc_i3c_master_ibi_isr(struct svc_i3c_master *master)
 		break;
 	case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST:
 		svc_i3c_master_emit_stop(master);
+
+		/*
+		 * If a target gets stuck holding SDA low, the controller reports a MR.
+		 * On NPCM845, emitting STOP may spuriously set SLVSTART, retriggering
+		 * the interrupt and re-entering MR handling, leading to an IRQ storm.
+		 * Clear SLVSTART after STOP to break the loop.
+		 */
+		if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART))
+			writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
 		break;
 	default:
 		break;
-- 
2.34.1


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Re: [PATCH v1 1/2] i3c: master: svc: Fix missed IBI after false SLVSTART on NPCM845

[Frank Li]

On Mon, Apr 13, 2026 at 08:50:39AM +0800, Stanley Chu wrote:
> From: Stanley Chu <yschu@nuvoton.com>
>
> The NPCM845 I3C controller may raise a false SLVSTART interrupt. The
> handler first latches MSTATUS and then clears SLVSTART. If a real IBI
> request arrives after the handler latches MSTATUS but before it clears
> the SLVSTART interrupt status,

How this happen? If irq handler running, hardware (real IBI) will trigger
irq line before it.

Do you enable other type irq?

Frank

> HW sets the SLVREQ state. However, the
> handler still relies on the stale MSTATUS snapshot, returns early, and
> misses the real IBI. No further interrupt is generated for this pending
> IBI.
>
> Re-read MSTATUS to obtain the latest state and avoid missing a real IBI
> due to this race condition.
>
> Fixes: 4dd12e944f07 ("i3c: master: svc: Fix npcm845 invalid slvstart event")
> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> ---
>  drivers/i3c/master/svc-i3c-master.c | 16 ++++++++++++----
>  1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
> index b84b324e4111..7d88e8fe3742 100644
> --- a/drivers/i3c/master/svc-i3c-master.c
> +++ b/drivers/i3c/master/svc-i3c-master.c
> @@ -672,10 +672,18 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
>  	/* Clear the interrupt status */
>  	writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
>
> -	/* Ignore the false event */
> -	if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART) &&
> -	    !SVC_I3C_MSTATUS_STATE_SLVREQ(active))
> -		return IRQ_HANDLED;
> +	if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART)) {
> +		/*
> +		 * Re-read MSTATUS to obtain the latest state and avoid
> +		 * missing an IBI that arrives after MSTATUS is latched
> +		 * but before SLVSTART is cleared.
> +		 */
> +		active = readl(master->regs + SVC_I3C_MSTATUS);
> +
> +		/* Ignore the false event */
> +		if (!SVC_I3C_MSTATUS_STATE_SLVREQ(active))
> +			return IRQ_HANDLED;
> +	}
>
>  	/*
>  	 * The SDA line remains low until the request is processed.
> --
> 2.34.1
>

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Re: [PATCH v1 1/2] i3c: master: svc: Fix missed IBI after false SLVSTART on NPCM845

[Stanley Chu]

On Mon, Apr 13, 2026 at 9:16 AM Frank Li <Frank.li@nxp.com> wrote:
>
> On Mon, Apr 13, 2026 at 08:50:39AM +0800, Stanley Chu wrote:
> > From: Stanley Chu <yschu@nuvoton.com>
> >
> > The NPCM845 I3C controller may raise a false SLVSTART interrupt. The
> > handler first latches MSTATUS and then clears SLVSTART. If a real IBI
> > request arrives after the handler latches MSTATUS but before it clears
> > the SLVSTART interrupt status,
>
> How this happen? If irq handler running, hardware (real IBI) will trigger
> irq line before it.
>
> Do you enable other type irq?
>
> Frank

Hi Frank,

Only SLVSTART interrupt. Below is the sequence:
- HW raises a false SLVSTART interrupt.
- The IRQ handler latches the MSTATUS register.
- Before the handler clears the SLVSTART status, a real IBI request arrives.
- HW updates the SLVREQ state to indicate a pending IBI.
- The handler continues using the stale MSTATUS snapshot, does not see
  the new SLVREQ state, and returns early.
- The real IBI is missed and no further interrupt is generated.

Thanks.

>
> > HW sets the SLVREQ state. However, the
> > handler still relies on the stale MSTATUS snapshot, returns early, and
> > misses the real IBI. No further interrupt is generated for this pending
> > IBI.
> >
> > Re-read MSTATUS to obtain the latest state and avoid missing a real IBI
> > due to this race condition.
> >
> > Fixes: 4dd12e944f07 ("i3c: master: svc: Fix npcm845 invalid slvstart event")
> > Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> > ---
> >  drivers/i3c/master/svc-i3c-master.c | 16 ++++++++++++----
> >  1 file changed, 12 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
> > index b84b324e4111..7d88e8fe3742 100644
> > --- a/drivers/i3c/master/svc-i3c-master.c
> > +++ b/drivers/i3c/master/svc-i3c-master.c
> > @@ -672,10 +672,18 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
> >       /* Clear the interrupt status */
> >       writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
> >
> > -     /* Ignore the false event */
> > -     if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART) &&
> > -         !SVC_I3C_MSTATUS_STATE_SLVREQ(active))
> > -             return IRQ_HANDLED;
> > +     if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART)) {
> > +             /*
> > +              * Re-read MSTATUS to obtain the latest state and avoid
> > +              * missing an IBI that arrives after MSTATUS is latched
> > +              * but before SLVSTART is cleared.
> > +              */
> > +             active = readl(master->regs + SVC_I3C_MSTATUS);
> > +
> > +             /* Ignore the false event */
> > +             if (!SVC_I3C_MSTATUS_STATE_SLVREQ(active))
> > +                     return IRQ_HANDLED;
> > +     }
> >
> >       /*
> >        * The SDA line remains low until the request is processed.
> > --
> > 2.34.1
> >

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Re: [PATCH v1 1/2] i3c: master: svc: Fix missed IBI after false SLVSTART on NPCM845

[Frank Li]

On Mon, Apr 13, 2026 at 09:40:02AM +0800, Stanley Chu wrote:
> On Mon, Apr 13, 2026 at 9:16 AM Frank Li <Frank.li@nxp.com> wrote:
> >
> > On Mon, Apr 13, 2026 at 08:50:39AM +0800, Stanley Chu wrote:
> > > From: Stanley Chu <yschu@nuvoton.com>
> > >
> > > The NPCM845 I3C controller may raise a false SLVSTART interrupt. The
> > > handler first latches MSTATUS and then clears SLVSTART. If a real IBI
> > > request arrives after the handler latches MSTATUS but before it clears
> > > the SLVSTART interrupt status,
> >
> > How this happen? If irq handler running, hardware (real IBI) will trigger
> > irq line before it.
> >
> > Do you enable other type irq?
> >
> > Frank
>
> Hi Frank,
>
> Only SLVSTART interrupt. Below is the sequence:
> - HW raises a false SLVSTART interrupt.
> - The IRQ handler latches the MSTATUS register.
> - Before the handler clears the SLVSTART status, a real IBI request arrives.
> - HW updates the SLVREQ state to indicate a pending IBI.
> - The handler continues using the stale MSTATUS snapshot, does not see
>   the new SLVREQ state, and returns early.

Because reading register and IBI request arriving are totally async

readl(master->regs + SVC_I3C_MSTATUS),  may return two results
1. before IBI request
2. after IBI request

How do you make sure second readl(master->regs + SVC_I3C_MSTATUS) always
get the result of after IBI request.

Frank

> - The real IBI is missed and no further interrupt is generated.
>
> Thanks.
>
> >
> > > HW sets the SLVREQ state. However, the
> > > handler still relies on the stale MSTATUS snapshot, returns early, and
> > > misses the real IBI. No further interrupt is generated for this pending
> > > IBI.
> > >
> > > Re-read MSTATUS to obtain the latest state and avoid missing a real IBI
> > > due to this race condition.
> > >
> > > Fixes: 4dd12e944f07 ("i3c: master: svc: Fix npcm845 invalid slvstart event")
> > > Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> > > ---
> > >  drivers/i3c/master/svc-i3c-master.c | 16 ++++++++++++----
> > >  1 file changed, 12 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
> > > index b84b324e4111..7d88e8fe3742 100644
> > > --- a/drivers/i3c/master/svc-i3c-master.c
> > > +++ b/drivers/i3c/master/svc-i3c-master.c
> > > @@ -672,10 +672,18 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
> > >       /* Clear the interrupt status */
> > >       writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
> > >
> > > -     /* Ignore the false event */
> > > -     if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART) &&
> > > -         !SVC_I3C_MSTATUS_STATE_SLVREQ(active))
> > > -             return IRQ_HANDLED;
> > > +     if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART)) {
> > > +             /*
> > > +              * Re-read MSTATUS to obtain the latest state and avoid
> > > +              * missing an IBI that arrives after MSTATUS is latched
> > > +              * but before SLVSTART is cleared.
> > > +              */
> > > +             active = readl(master->regs + SVC_I3C_MSTATUS);
> > > +
> > > +             /* Ignore the false event */
> > > +             if (!SVC_I3C_MSTATUS_STATE_SLVREQ(active))
> > > +                     return IRQ_HANDLED;
> > > +     }
> > >
> > >       /*
> > >        * The SDA line remains low until the request is processed.
> > > --
> > > 2.34.1
> > >

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Re: [PATCH v1 1/2] i3c: master: svc: Fix missed IBI after false SLVSTART on NPCM845

[Stanley Chu]

On Mon, Apr 13, 2026 at 11:00 AM Frank Li <Frank.li@nxp.com> wrote:
>
> On Mon, Apr 13, 2026 at 09:40:02AM +0800, Stanley Chu wrote:
> > On Mon, Apr 13, 2026 at 9:16 AM Frank Li <Frank.li@nxp.com> wrote:
> > >
> > > On Mon, Apr 13, 2026 at 08:50:39AM +0800, Stanley Chu wrote:
> > > > From: Stanley Chu <yschu@nuvoton.com>
> > > >
> > > > The NPCM845 I3C controller may raise a false SLVSTART interrupt. The
> > > > handler first latches MSTATUS and then clears SLVSTART. If a real IBI
> > > > request arrives after the handler latches MSTATUS but before it clears
> > > > the SLVSTART interrupt status,
> > >
> > > How this happen? If irq handler running, hardware (real IBI) will trigger
> > > irq line before it.
> > >
> > > Do you enable other type irq?
> > >
> > > Frank
> >
> > Hi Frank,
> >
> > Only SLVSTART interrupt. Below is the sequence:
> > - HW raises a false SLVSTART interrupt.
> > - The IRQ handler latches the MSTATUS register.
> > - Before the handler clears the SLVSTART status, a real IBI request arrives.
> > - HW updates the SLVREQ state to indicate a pending IBI.
> > - The handler continues using the stale MSTATUS snapshot, does not see
> >   the new SLVREQ state, and returns early.
>
> Because reading register and IBI request arriving are totally async
>
> readl(master->regs + SVC_I3C_MSTATUS),  may return two results
> 1. before IBI request
> 2. after IBI request
>
> How do you make sure second readl(master->regs + SVC_I3C_MSTATUS) always
> get the result of after IBI request.
>
> Frank

Hi Frank,
The ordering between the second readl(MSTATUS) and the real IBI arrival is
not critical, as long as the second read is performed after clearing SLVSTART.

There are two cases:
1. IBI arrives before the second read
After SLVSTART is cleared, HW has already updated the SLVREQ state, so the
second MSTATUS read can observe the pending IBI and handle it in the same
IRQ.

2. IBI arrives after the second read
Even though the second MSTATUS read does not reflect the pending IBI, the
IBI will assert SLVSTART again. A new interrupt will be generated
after the current
handler returns, and the pending IBI is handled in the next IRQ.

Thanks.

>
> > - The real IBI is missed and no further interrupt is generated.
> >
> > Thanks.
> >
> > >
> > > > HW sets the SLVREQ state. However, the
> > > > handler still relies on the stale MSTATUS snapshot, returns early, and
> > > > misses the real IBI. No further interrupt is generated for this pending
> > > > IBI.
> > > >
> > > > Re-read MSTATUS to obtain the latest state and avoid missing a real IBI
> > > > due to this race condition.
> > > >
> > > > Fixes: 4dd12e944f07 ("i3c: master: svc: Fix npcm845 invalid slvstart event")
> > > > Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> > > > ---
> > > >  drivers/i3c/master/svc-i3c-master.c | 16 ++++++++++++----
> > > >  1 file changed, 12 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
> > > > index b84b324e4111..7d88e8fe3742 100644
> > > > --- a/drivers/i3c/master/svc-i3c-master.c
> > > > +++ b/drivers/i3c/master/svc-i3c-master.c
> > > > @@ -672,10 +672,18 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
> > > >       /* Clear the interrupt status */
> > > >       writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
> > > >
> > > > -     /* Ignore the false event */
> > > > -     if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART) &&
> > > > -         !SVC_I3C_MSTATUS_STATE_SLVREQ(active))
> > > > -             return IRQ_HANDLED;
> > > > +     if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART)) {
> > > > +             /*
> > > > +              * Re-read MSTATUS to obtain the latest state and avoid
> > > > +              * missing an IBI that arrives after MSTATUS is latched
> > > > +              * but before SLVSTART is cleared.
> > > > +              */
> > > > +             active = readl(master->regs + SVC_I3C_MSTATUS);
> > > > +
> > > > +             /* Ignore the false event */
> > > > +             if (!SVC_I3C_MSTATUS_STATE_SLVREQ(active))
> > > > +                     return IRQ_HANDLED;
> > > > +     }
> > > >
> > > >       /*
> > > >        * The SDA line remains low until the request is processed.
> > > > --
> > > > 2.34.1
> > > >

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Re: [PATCH v1 1/2] i3c: master: svc: Fix missed IBI after false SLVSTART on NPCM845

[Frank Li]

On Mon, Apr 13, 2026 at 11:59:59AM +0800, Stanley Chu wrote:
> On Mon, Apr 13, 2026 at 11:00 AM Frank Li <Frank.li@nxp.com> wrote:
> >
> > On Mon, Apr 13, 2026 at 09:40:02AM +0800, Stanley Chu wrote:
> > > On Mon, Apr 13, 2026 at 9:16 AM Frank Li <Frank.li@nxp.com> wrote:
> > > >
> > > > On Mon, Apr 13, 2026 at 08:50:39AM +0800, Stanley Chu wrote:
> > > > > From: Stanley Chu <yschu@nuvoton.com>
> > > > >
> > > > > The NPCM845 I3C controller may raise a false SLVSTART interrupt. The
> > > > > handler first latches MSTATUS and then clears SLVSTART. If a real IBI
> > > > > request arrives after the handler latches MSTATUS but before it clears
> > > > > the SLVSTART interrupt status,
> > > >
> > > > How this happen? If irq handler running, hardware (real IBI) will trigger
> > > > irq line before it.
> > > >
> > > > Do you enable other type irq?
> > > >
> > > > Frank
> > >
> > > Hi Frank,
> > >
> > > Only SLVSTART interrupt. Below is the sequence:
> > > - HW raises a false SLVSTART interrupt.
> > > - The IRQ handler latches the MSTATUS register.
> > > - Before the handler clears the SLVSTART status, a real IBI request arrives.
> > > - HW updates the SLVREQ state to indicate a pending IBI.
> > > - The handler continues using the stale MSTATUS snapshot, does not see
> > >   the new SLVREQ state, and returns early.
> >
> > Because reading register and IBI request arriving are totally async
> >
> > readl(master->regs + SVC_I3C_MSTATUS),  may return two results
> > 1. before IBI request
> > 2. after IBI request
> >
> > How do you make sure second readl(master->regs + SVC_I3C_MSTATUS) always
> > get the result of after IBI request.
> >
> > Frank
>
> Hi Frank,
> The ordering between the second readl(MSTATUS) and the real IBI arrival is
> not critical, as long as the second read is performed after clearing SLVSTART.
>
> There are two cases:
> 1. IBI arrives before the second read
> After SLVSTART is cleared, HW has already updated the SLVREQ state, so the
> second MSTATUS read can observe the pending IBI and handle it in the same
> IRQ.
>
> 2. IBI arrives after the second read
> Even though the second MSTATUS read does not reflect the pending IBI, the
> IBI will assert SLVSTART again. A new interrupt will be generated
> after the current
> handler returns, and the pending IBI is handled in the next IRQ.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
> Thanks.
>
> >
> > > - The real IBI is missed and no further interrupt is generated.
> > >
> > > Thanks.
> > >
> > > >
> > > > > HW sets the SLVREQ state. However, the
> > > > > handler still relies on the stale MSTATUS snapshot, returns early, and
> > > > > misses the real IBI. No further interrupt is generated for this pending
> > > > > IBI.
> > > > >
> > > > > Re-read MSTATUS to obtain the latest state and avoid missing a real IBI
> > > > > due to this race condition.
> > > > >
> > > > > Fixes: 4dd12e944f07 ("i3c: master: svc: Fix npcm845 invalid slvstart event")
> > > > > Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> > > > > ---
> > > > >  drivers/i3c/master/svc-i3c-master.c | 16 ++++++++++++----
> > > > >  1 file changed, 12 insertions(+), 4 deletions(-)
> > > > >
> > > > > diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
> > > > > index b84b324e4111..7d88e8fe3742 100644
> > > > > --- a/drivers/i3c/master/svc-i3c-master.c
> > > > > +++ b/drivers/i3c/master/svc-i3c-master.c
> > > > > @@ -672,10 +672,18 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
> > > > >       /* Clear the interrupt status */
> > > > >       writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
> > > > >
> > > > > -     /* Ignore the false event */
> > > > > -     if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART) &&
> > > > > -         !SVC_I3C_MSTATUS_STATE_SLVREQ(active))
> > > > > -             return IRQ_HANDLED;
> > > > > +     if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART)) {
> > > > > +             /*
> > > > > +              * Re-read MSTATUS to obtain the latest state and avoid
> > > > > +              * missing an IBI that arrives after MSTATUS is latched
> > > > > +              * but before SLVSTART is cleared.
> > > > > +              */
> > > > > +             active = readl(master->regs + SVC_I3C_MSTATUS);
> > > > > +
> > > > > +             /* Ignore the false event */
> > > > > +             if (!SVC_I3C_MSTATUS_STATE_SLVREQ(active))
> > > > > +                     return IRQ_HANDLED;
> > > > > +     }
> > > > >
> > > > >       /*
> > > > >        * The SDA line remains low until the request is processed.
> > > > > --
> > > > > 2.34.1
> > > > >

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Re: [PATCH v1 2/2] i3c: master: svc: Prevent IRQ storm from false SLVSTART on NPCM845

[Frank Li]

On Mon, Apr 13, 2026 at 08:50:40AM +0800, Stanley Chu wrote:
> From: Stanley Chu <yschu@nuvoton.com>
>
> On NPCM845, when a target on the I3C bus gets stuck holding SDA low,
> the controller reports a false Master Request (MR) in-band interrupt
> event. The driver handles this by emitting a STOP condition to restore
> the bus.
>
> However, the hardware quirk SVC_I3C_QUIRK_FALSE_SLVSTART indicates that
> emitting a STOP condition may spuriously set the SLVSTART interrupt
> status bit. In the Master Request case, this creates a feedback loop:
> the STOP triggers a new SLVSTART event, the IRQ handler fires again,
> the controller still reports an MR type, another STOP is emitted, and
> the cycle repeats indefinitely, resulting in an IRQ storm that can lock
> up the CPU.
>
> Clear the SLVSTART status bit explicitly after emitting the STOP in the
> Master Request IBI handler when the SVC_I3C_QUIRK_FALSE_SLVSTART quirk
> is set. This breaks the feedback loop without affecting normal SLVSTART
> processing, which is already guarded in the top-level IRQ handler by
> checking that MSTATUS is in SLVREQ state.
>
> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/i3c/master/svc-i3c-master.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
> index 7d88e8fe3742..c16397013334 100644
> --- a/drivers/i3c/master/svc-i3c-master.c
> +++ b/drivers/i3c/master/svc-i3c-master.c
> @@ -655,6 +655,15 @@ static void svc_i3c_master_ibi_isr(struct svc_i3c_master *master)
>  		break;
>  	case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST:
>  		svc_i3c_master_emit_stop(master);
> +
> +		/*
> +		 * If a target gets stuck holding SDA low, the controller reports a MR.
> +		 * On NPCM845, emitting STOP may spuriously set SLVSTART, retriggering
> +		 * the interrupt and re-entering MR handling, leading to an IRQ storm.
> +		 * Clear SLVSTART after STOP to break the loop.
> +		 */
> +		if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART))
> +			writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
>  		break;
>  	default:
>  		break;
> --
> 2.34.1
>

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Re: [PATCH v1 0/2] i3c: master: svc: Fix false SLVSTART issues on NPCM845

[Alexandre Belloni]

On Mon, 13 Apr 2026 08:50:38 +0800, Stanley Chu wrote:
> From: Stanley Chu <yschu@nuvoton.com>
> 
> The Nuvoton NPCM845 I3C controller has a hardware quirk
> (SVC_I3C_QUIRK_FALSE_SLVSTART) where a spurious SLVSTART interrupt
> may be generated. This series addresses two separate issues related to
> this quirk:
> 
> [...]

Applied, thanks!

[1/2] i3c: master: svc: Fix missed IBI after false SLVSTART on NPCM845
      https://git.kernel.org/i3c/c/fa1d4fa118f4
[2/2] i3c: master: svc: Prevent IRQ storm from false SLVSTART on NPCM845
      https://git.kernel.org/i3c/c/1effa3adfe53

Best regards,

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Embedded Linux and Kernel engineering
https://bootlin.com

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