cr.gpta register

cr.gpta register

[Matt Chapman]

Can anyone tell me what is the purpose of the cr.gpta (Guest Page Table
Address) register?  It is referred to in the ASDM and elsewhere but not
explicitly documented.

Thanks,
Matt

RE: cr.gpta register

[Jim Hull]

GPTA (CR9) exists solely to support the IA-32 System Environment (see
PAL_ENTER_IA_32_ENV in SDM Volume 2, Chapter 11).  All details concerning the
format and operation of this register are considered Intel Restricted.

From the perspective of an ia64 OS, GPTA should be treated as a Reserved
register - it will be initialized by PAL at reset, and the OS should never touch
it.

 -- Jim
    HP Itanium Processor Architect

> -----Original Message-----
> From: linux-ia64-owner@vger.kernel.org 
> [mailto:linux-ia64-owner@vger.kernel.org] On Behalf Of Matt Chapman
> Sent: Monday, April 26, 2004 5:35 AM
> To: linux-ia64@vger.kernel.org
> Subject: cr.gpta register
> 
> 
> Can anyone tell me what is the purpose of the cr.gpta (Guest 
> Page Table
> Address) register?  It is referred to in the ASDM and 
> elsewhere but not
> explicitly documented.
> 
> Thanks,
> Matt
> 
> -
> To unsubscribe from this list: send the line "unsubscribe 
> linux-ia64" in
> the body of a message to majordomo@vger.kernel.org
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> 

Re: cr.gpta register

[Chris Wedgwood]

On Fri, Apr 30, 2004 at 10:36:32AM -0700, Jim Hull wrote:

> GPTA (CR9) exists solely to support the IA-32 System Environment
> (see PAL_ENTER_IA_32_ENV in SDM Volume 2, Chapter 11).  All details
> concerning the format and operation of this register are considered
> Intel Restricted.

This is the case with some of the MCE stuff means figuring out various
things took way longer than it should have.

I really wish someone would talk Intel into documenting things a bit
more.


  --cw

Re: cr.gpta register

[Matt Chapman]

Amen to that :)  (But thanks for the info Jim, that was sufficient to
answer my question.)

In the meantime I've started to document some of the info I've learned
so far in our Gelato wiki.  This is currently focused on instruction
scheduling, since that's what I was most interested in understanding,
but I'm also interested in collating info on other useful implementation
details [1].

Hopefully other people might find this useful and add to it.

http://www.gelato.unsw.edu.au/IA64wiki/ItaniumInternals

Matt


[1] Something I'd be particularly interested in is details of cache
and TLB replacement algorithms.  (NRU is hardly specific.)


On Fri, Apr 30, 2004 at 04:04:16PM -0700, Chris Wedgwood wrote:
> On Fri, Apr 30, 2004 at 10:36:32AM -0700, Jim Hull wrote:
> 
> > GPTA (CR9) exists solely to support the IA-32 System Environment
> > (see PAL_ENTER_IA_32_ENV in SDM Volume 2, Chapter 11).  All details
> > concerning the format and operation of this register are considered
> > Intel Restricted.
> 
> This is the case with some of the MCE stuff means figuring out various
> things took way longer than it should have.
> 
> I really wish someone would talk Intel into documenting things a bit
> more.
> 
> 
>   --cw
> 
> -
> To unsubscribe from this list: send the line "unsubscribe linux-ia64" in
> the body of a message to majordomo@vger.kernel.org
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