[PATCH] 2.6.1 enable PIOW/DMAR relaxed ordering on ZX1

[PATCH] 2.6.1 enable PIOW/DMAR relaxed ordering on ZX1

[Grant Grundler]

Tony, David,
I lied. Apologies. I thought I had sent this patch before
but was just confused by the change in my local bk tree.
I had the patch sitting there since September. :^(

This enables DMA Reads to bypass PIO Writes for all PCI/PCI-X devices.
On older RHAS (2.1 orig), this improved netperf UDP Stream by ~10%.
Testing on kernel.org 2.4 kernels showed only ~3-5% improvement.
I suspect because of improvements to tg3 driver.

diff is against http://lia64.bkbits.net/linux-ia64-2.6/

thanks,
grant


=== arch/ia64/hp/common/sba_iommu.c 1.33 vs edited ==--- 1.33/arch/ia64/hp/common/sba_iommu.c	Fri Sep 19 08:03:40 2003
+++ edited/arch/ia64/hp/common/sba_iommu.c	Thu Jan 22 13:25:17 2004
@@ -156,6 +156,10 @@
 #define IOC_TCNFG	0x318
 #define IOC_PDIR_BASE	0x320
 
+#define IOC_ROPE0_CFG	0x500
+#define   IOC_ROPE_AO	  0x10	/* Allow "Relaxed Ordering" */
+
+
 /* AGP GART driver looks for this */
 #define ZX1_SBA_IOMMU_COOKIE	0x0000badbadc0ffeeUL
 
@@ -1421,6 +1425,7 @@
 #ifdef FULL_VALID_PDIR
 	unsigned long index;
 #endif
+	unsigned int i;
 
 	/*
 	** Firmware programs the base and size of a "safe IOVA space"
@@ -1475,6 +1480,18 @@
 	** can't reprogram them the way drivers want.
 	*/
 	WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
+
+	/* Clear ROPE(N)_CONFIG AO bit.
+	** Disables "NT Ordering" (~= !"Relaxed Ordering")
+	** Overrides bit 1 in DMA Hint Sets.
+	** Improves netperf UDP_STREAM by ~10% for tg3 on bcm5701.
+	*/
+	for (i=0; i<(8*8); i+=8) {
+		unsigned long rope_config;
+		rope_config = READ_REG(ioc->ioc_hpa + IOC_ROPE0_CFG + i);
+		rope_config &= ~IOC_ROPE_AO;
+		WRITE_REG(rope_config, ioc->ioc_hpa + IOC_ROPE0_CFG + i);
+	}
 
 	/*
 	** Setting the upper bits makes checking for bypass addresses

Re: [PATCH] 2.6.1 enable PIOW/DMAR relaxed ordering on ZX1

[David Mosberger]

>>>>> On Thu, 22 Jan 2004 18:43:02 -0800, Grant Grundler <iod00d@hp.com> said:

  Grant> Tony, David, I lied. Apologies. I thought I had sent this
  Grant> patch before but was just confused by the change in my local
  Grant> bk tree.  I had the patch sitting there since September. :^(

  Grant> This enables DMA Reads to bypass PIO Writes for all PCI/PCI-X
  Grant> devices.  On older RHAS (2.1 orig), this improved netperf UDP
  Grant> Stream by ~10%.  Testing on kernel.org 2.4 kernels showed
  Grant> only ~3-5% improvement.  I suspect because of improvements to
  Grant> tg3 driver.

  Grant> diff is against http://lia64.bkbits.net/linux-ia64-2.6/

I'm not sure Tony's tree is ready for prime-time yet.  Could you
please diff against my tree instead (linux-ia64-2.5)?  I'd have merged
the patch by hand, but the context in the patch you posted doesn't
look like anything that appears in the current sba_iommu.c.

Thanks,

	--david

RE: [PATCH] 2.6.1 enable PIOW/DMAR relaxed ordering on ZX1

[Luck, Tony]

> I'm not sure Tony's tree is ready for prime-time yet.  Could you
> please diff against my tree instead (linux-ia64-2.5)?  I'd have merged
> the patch by hand, but the context in the patch you posted doesn't
> look like anything that appears in the current sba_iommu.c.

In the U.K. (where I'm from originally) people learning to
drive must display a large "L" (for "Learning driver") on
their car to warn other motorists that they may make erratic
moves.

In the bitkeeper world, I'm still learning ... so keep a safe
distance from my tree until I pass my proficiency exam.

-Tony

Re: [PATCH] 2.6.1 enable PIOW/DMAR relaxed ordering on ZX1

[Grant Grundler]

On Fri, Jan 23, 2004 at 10:06:58PM -0800, David Mosberger wrote:
> I'm not sure Tony's tree is ready for prime-time yet.  Could you
> please diff against my tree instead (linux-ia64-2.5)?

yes - sorry. Patch appended.

> I'd have merged
> the patch by hand, but the context in the patch you posted doesn't
> look like anything that appears in the current sba_iommu.c.

hrm...they shouldn't be that different.
OIC.  Some of the DMA hint register support was removed.
If you want to finish that job, remove the definition and references
to hint_mask_pdir and hint_shift_pdir. I'll maintain DMA hints
as a seperate patch (2.4 only so far) until I have data it's useful.

thanks,
grant


=== arch/ia64/hp/common/sba_iommu.c 1.35 vs edited ==--- 1.35/arch/ia64/hp/common/sba_iommu.c	Mon Jan 12 08:02:23 2004
+++ edited/arch/ia64/hp/common/sba_iommu.c	Mon Jan 26 08:47:02 2004
@@ -158,6 +158,10 @@
 #define IOC_TCNFG	0x318
 #define IOC_PDIR_BASE	0x320
 
+#define IOC_ROPE0_CFG	0x500
+#define   IOC_ROPE_AO	  0x10	/* Allow "Relaxed Ordering" */
+
+
 /* AGP GART driver looks for this */
 #define ZX1_SBA_IOMMU_COOKIE	0x0000badbadc0ffeeUL
 
@@ -1361,6 +1365,7 @@
 #ifdef FULL_VALID_PDIR
 	unsigned long index;
 #endif
+	unsigned int i;
 
 	/*
 	** Firmware programs the base and size of a "safe IOVA space"
@@ -1455,6 +1460,18 @@
 	/* Enable IOVA translation */
 	WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
 	READ_REG(ioc->ioc_hpa + IOC_IBASE);
+
+	/* Clear ROPE(N)_CONFIG AO bit.
+	** Disables "NT Ordering" (~= !"Relaxed Ordering")
+	** Overrides bit 1 in DMA Hint Sets.
+	** Improves netperf UDP_STREAM by ~10% for tg3 on bcm5701.
+	*/
+	for (i=0; i<(8*8); i+=8) {
+		unsigned long rope_config;
+		rope_config = READ_REG(ioc->ioc_hpa + IOC_ROPE0_CFG + i);
+		rope_config &= ~IOC_ROPE_AO;
+		WRITE_REG(rope_config, ioc->ioc_hpa + IOC_ROPE0_CFG + i);
+	}
 }
 
 static void __init