Redirectable IRQs

Redirectable IRQs

[Michael.Meduna]

Is there a way to permanently disable interrupts for specific CPUs.  I
am running on a 2.6 kernel and have designated CPU 0 in lowest priority
delivery mode.  I understand how to set lowest priority delivery mode or
fixed delivery mode for a specific IRQ.  What I would like to do is set
CPU 0 in lowest priority delivery mode for all IRQs but then, have the
ability to permanently disable interrupts for specific CPUs.

I realize that I could set CPU 0 to be the only processor to accept all
interrupts, however it would be best to allow Linux to spread the
interrupts
across other processors.  I have a few critical applications each bound to
a
cpuset with its own processor.  Ideally, I would not want these CPUs to
take
interrupts.

For example:  lets say I have a system with 8 host CPUs.  I create a
processor set that will contain a pool of CPUs (0-3).  I create another set
of processor sets (4 of them) that will contain processors 4-7.  All IRQs
are set to CPU 0 in lowest priority delivery mode.  I do not want
processors
4-7 to take an interrupt.  However, I do want interrupts to be spread
across
processors 0-3.  Is there a way to set the XTP register such that
processors
4-7 will never take an interrupt?

Re: Redirectable IRQs

[Grant Grundler]

On Thu, May 12, 2005 at 12:15:41PM -0700, Michael.Meduna@Bull.com wrote:
> Is there a way to permanently disable interrupts for specific CPUs.

Yes - but it may not be exactly what you want.
See /proc/irq/*/smp_affinity.

I'm not sure what /sys/class/pci_bus/*/cpuaffinity does.
It looks like a cpu set mask though.

...
> I have a few critical applications each bound to a cpuset with its
> own processor.  Ideally, I would not want these CPUs to take interrupts.

Simple solution is to bind each IRQ "manually" to a single processor.

> Is there a way to set the XTP register such that processors
> 4-7 will never take an interrupt?

ISTR, HP IA64 platforms do not implement XTP.
Binding IRQs 1:1 with CPUs was seen as a better choice.
MSI-X allows intelligent 1:N if devices really need to load
multiple CPUs.

grant

Re: Redirectable IRQs

[Michael.Meduna]

Grant,

Thank you for the reply.  I forgot to mention that this is an Intel ia64
platform.

Re: Redirectable IRQs

[Erich Focht]

On Thursday 12 May 2005 22:37, Michael.Meduna@bull.com wrote:
> Thank you for the reply.  I forgot to mention that this is an Intel ia64
> platform.

As far as I remember I've been told by Intel that the i870 chipset doesn't
implement the XTP priority based IRQ rerouting. The NEC TX-7 chipset does and
allows priority based routing within a cell (ccNUMA node). Maybe fixed
routing works for you.

Regards,
Erich

Re: Redirectable IRQs

[Grant Grundler]

On Thu, May 12, 2005 at 01:37:46PM -0700, Michael.Meduna@Bull.com wrote:
> Thank you for the reply.
> I forgot to mention that this is an Intel ia64 platform.

Yes, Intel implements XTP - but that doesn't mean you have to use it.
You can bind each IRQ source to a single processor.

grant

Re: Redirectable IRQs

[Grant Grundler]

On Thu, May 12, 2005 at 02:58:15PM -0700, Grant Grundler wrote:
> Yes, Intel implements XTP - but that doesn't mean you have to use it.

Sorry - I'm thinking of the i460 (Merced bus) based platforms.
I don't know about i870 chipset.

thanks,
grant