Re: [patch 1/6] align kenrel rbs on 128 byte

[Russ Anderson <rja@efs.americas.sgi.com>]

Kenneth Chen wrote:
> Keith Owens wrote on Tuesday, January 31, 2006 12:57 AM
> > 
> > The cache lines are not guaranteed to be 128 byte aligned, they
> > were 64 on bigsur.  Change 127 to (L1_CACHE_BYTES - 1).
> 
> That did cross my mind and L1_CACHE_BYTES is such a misleading
> name.  In my head, L1 means the cache level closest to the CPU
> core, but here it appears to represent last level cache line.
> Do we have the numbering scheme reversed?  I have no idea what's
> going on here. 

I agree that L1_CACHE_BYTES is misleading.  Looking at
the usage, most (if not all) references expect the 
last (external/FSB) cache line size, not caches closer
to the core.  As Jes points out SMP_CACHE_BYTES is
more what they mean.

Why not just call it CACHE_BYTES, meaning the last cache
level.  Handling of caches closer to the core most likely
should be through PAL, or, it really needed, use the 
engineering cache level prefix.

-- 
Russ Anderson, OS RAS/Partitioning Project Lead  
SGI - Silicon Graphics Inc          rja@sgi.com