From: Jes Sorensen <jes@sgi.com>
To: linux-ia64@vger.kernel.org
Subject: Re: [patch 1/6] align kenrel rbs on 128 byte
Date: Tue, 31 Jan 2006 11:00:59 +0000 [thread overview]
Message-ID: <yq0zmlcpspg.fsf@jaguar.mkp.net> (raw)
In-Reply-To: <200601310848.k0V8mbg11087@unix-os.sc.intel.com>
>>>>> "Ken" = Chen, Kenneth W <kenneth.w.chen@intel.com> writes:
Ken> Keith Owens wrote on Tuesday, January 31, 2006 12:57 AM
>> The cache lines are not guaranteed to be 128 byte aligned, they
>> were 64 on bigsur. Change 127 to (L1_CACHE_BYTES - 1).
Ken> That did cross my mind and L1_CACHE_BYTES is such a misleading
Ken> name. In my head, L1 means the cache level closest to the CPU
Ken> core, but here it appears to represent last level cache line. Do
Ken> we have the numbering scheme reversed? I have no idea what's
Ken> going on here.
Ken,
Shouldn't this be SMP_CACHE_BYTES if anything?
Cheers,
Jes
next prev parent reply other threads:[~2006-01-31 11:00 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-01-31 8:48 [patch 1/6] align kenrel rbs on 128 byte Chen, Kenneth W
2006-01-31 8:57 ` Keith Owens
2006-01-31 9:42 ` Chen, Kenneth W
2006-01-31 10:15 ` Andreas Schwab
2006-01-31 11:00 ` Jes Sorensen [this message]
2006-01-31 15:26 ` Russ Anderson
2006-01-31 16:25 ` Chen, Kenneth W
2006-01-31 19:58 ` Richard Harke
2006-01-31 19:59 ` Chen, Kenneth W
2006-01-31 20:16 ` Richard Harke
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