Re: [PATCH 2/2]Add Variable Page Size and IA64 Support in Intel IOMMU: IA64 Specific Part

[Fenghua Yu <fenghua.yu@intel.com>]

> > Could you please point me to the doc that explicitly says that architecturally ia64 doesn't need cache flush?
> 
> The following sections in volume 2 of the SDM mention DMA:
> Part 1, Sec 4.4.3, Cacheability and Coherency Attribute:
> Part 2, Sec 2.5.4, DMA:
> 
> It sounds like the expectation is that DMA will be fully coherent
> and no flushes would be required, but there is wiggle room in that
> last paragraph for platforms that don't maintain coherency.

The cache coherency bit in VT-d is for root, context, and page tables which are for DMA management, not DMA data itself. VT-d DMA data should be cache coherent.The Intel IOMMU code doesn't need to deal with non cache coherency in DMA data traffic. But root, context, and page tables could be non cache coherent and this is handled by Intel IOMMU code.

Thanks.

-Fenghua