[patch] ar.fpsr not set on MCA/INIT kernel entry

[patch] ar.fpsr not set on MCA/INIT kernel entry

[Russ Anderson]

[patch] ar.fpsr not set on MCA/INIT kernel entry

When entering the kernel due to an MCA or INIT, ar.fpsr (ar40)
was not getting set to the kernel default value (remaining
at the user value).  The effect depends on the user setting 
of ar.fpsr.  In the test case, the effect was addresses 
printing with strange hex values.  

Setting ar.fpsr in ia64_set_kernel_registers sets it for both
the MCA and INIT paths.  The user value of ar.fpsr is correctly 
saved (in ia64_state_save) and restored (in ia64_state_restore).

Below is an example of output with very strange hex values.
Anyone know the value of hex 'g'?  :-)

-------------------------------------------------------
Entered OS INIT handler. PSPˇf2g19g cpu\x11 monarch=1
Delaying for 5 seconds...
All OS INIT slaves have reached rendezvous
Processes interrupted by INIT - 0 (cpu 14 task 0xdfffg55g7a4c6gA) 0 (cpu 16 task 0xdfffg55g7a4d6gA) 0 (cpu 21 task 0xdfffg25fg3e5egA)


Backtrace of pid 1 (init)

Call Trace:
 [<9ffffffgfg7328A>] schedule+0x19fg/0x1c7g
                                spflffg45fg3ede8Aa bspflffg45fg3ed7gA0
 [<9ffffffgfg733gA0>] schedule_timeout+0xgg/0x17g
                                spflffg45fg3ede8Ad bspflffg45fg3ed7gA0
 [<9ffffffgfg185gAp>] do_select+0x35g/0x83g
                                spflffg45fg3ede8Ad bspflffg45fg3ed7gAd
 [<9ffffffgfg1868A>] sys_select+0x5gg/0x9dg
                                spflffg45fg3ede8A [<9ffffffgfffga8A>] ia64_ret_from_syscall+0x0/0x1g
                                spflffg45fg3ede8A0 bspflffg45fg3ed7gAn
 [<9ffffffffffgegAP>] __kernel_syscall_via_break+0x0/0x1g
                                spflffg45fg3edegA bspflffg45fg3ed7gAn
---------------------------------------------------------------

Signed-off-by: Russ Anderson (rja@sgi.com)


---
 arch/ia64/kernel/mca_asm.S |    2 ++
 1 file changed, 2 insertions(+)

Index: test/arch/ia64/kernel/mca_asm.S
=================================--- test.orig/arch/ia64/kernel/mca_asm.S	2006-09-18 16:10:06.058062990 -0500
+++ test/arch/ia64/kernel/mca_asm.S	2006-09-18 16:10:29.628971888 -0500
@@ -1063,7 +1063,9 @@ ia64_set_kernel_registers:
 	;;
 	mov IA64_KR(CURRENT_STACK)=r16
 	or r21=r20,r21				// construct PA | page properties
+	movl r17=FPSR_DEFAULT
 	;;
+	mov.m ar.fpsr=r17			// set ar.fpsr to kernel default value
 	mov cr.itir=r18
 	mov cr.ifa=r13
 	mov r20=IA64_TR_CURRENT_STACK
-- 
Russ Anderson, OS RAS/Partitioning Project Lead  
SGI - Silicon Graphics Inc          rja@sgi.com
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Re: [patch] ar.fpsr not set on MCA/INIT kernel entry

[Keith Owens]

Russ Anderson (on Mon, 18 Sep 2006 16:18:28 -0500 (CDT)) wrote:
>[patch] ar.fpsr not set on MCA/INIT kernel entry
>Index: test/arch/ia64/kernel/mca_asm.S
>=================================>--- test.orig/arch/ia64/kernel/mca_asm.S	2006-09-18 16:10:06.058062990 -0500
>+++ test/arch/ia64/kernel/mca_asm.S	2006-09-18 16:10:29.628971888 -0500
>@@ -1063,7 +1063,9 @@ ia64_set_kernel_registers:
> 	;;
> 	mov IA64_KR(CURRENT_STACK)=r16
> 	or r21=r20,r21				// construct PA | page properties
>+	movl r17=FPSR_DEFAULT
> 	;;
>+	mov.m ar.fpsr=r17			// set ar.fpsr to kernel default value
> 	mov cr.itir=r18
> 	mov cr.ifa=r13
> 	mov r20=IA64_TR_CURRENT_STACK

Any particular reason to place those instructions in the middle of the
code that wires IA64_TR_CURRENT_STACK?  I tried to keep the tr code as
standard as possible, to make it easier to change in future.  This code
is not performance sensitive, readability counts more than a couple of
unused slots here.

Re: [patch] ar.fpsr not set on MCA/INIT kernel entry

[Russ Anderson]

Keith Owens wrote:
> Russ Anderson (on Mon, 18 Sep 2006 16:18:28 -0500 (CDT)) wrote:
> >[patch] ar.fpsr not set on MCA/INIT kernel entry
> >Index: test/arch/ia64/kernel/mca_asm.S
> >=================================> >--- test.orig/arch/ia64/kernel/mca_asm.S	2006-09-18 16:10:06.058062990 -0500
> >+++ test/arch/ia64/kernel/mca_asm.S	2006-09-18 16:10:29.628971888 -0500
> >@@ -1063,7 +1063,9 @@ ia64_set_kernel_registers:
> > 	;;
> > 	mov IA64_KR(CURRENT_STACK)=r16
> > 	or r21=r20,r21				// construct PA | page properties
> >+	movl r17=FPSR_DEFAULT
> > 	;;
> >+	mov.m ar.fpsr=r17			// set ar.fpsr to kernel default value
> > 	mov cr.itir=r18
> > 	mov cr.ifa=r13
> > 	mov r20=IA64_TR_CURRENT_STACK
> 
> Any particular reason to place those instructions in the middle of the
> code that wires IA64_TR_CURRENT_STACK?  I tried to keep the tr code as
> standard as possible, to make it easier to change in future.  This code
> is not performance sensitive, readability counts more than a couple of
> unused slots here.

Those lines can be shifted up or down.   
Does this look better?

---
 arch/ia64/kernel/mca_asm.S |    4 ++++
 1 file changed, 4 insertions(+)

Index: test/arch/ia64/kernel/mca_asm.S
=================================--- test.orig/arch/ia64/kernel/mca_asm.S	2006-09-18 16:10:06.058062990 -0500
+++ test/arch/ia64/kernel/mca_asm.S	2006-09-18 18:35:41.232092232 -0500
@@ -1067,6 +1067,10 @@ ia64_set_kernel_registers:
 	mov cr.itir=r18
 	mov cr.ifa=r13
 	mov r20=IA64_TR_CURRENT_STACK
+
+	movl r17=FPSR_DEFAULT
+	;;
+	mov.m ar.fpsr=r17			// set ar.fpsr to kernel default value
 	;;
 	itr.d dtr[r20]=r21
 	;;
-- 
Russ Anderson, OS RAS/Partitioning Project Lead  
SGI - Silicon Graphics Inc          rja@sgi.com