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* Re: sched_clock - cont'd
@ 2004-06-04 14:41 Zoltan Menyhart
  2004-06-04 14:52 ` David Mosberger
  2004-06-04 16:51 ` David Mosberger
  0 siblings, 2 replies; 3+ messages in thread
From: Zoltan Menyhart @ 2004-06-04 14:41 UTC (permalink / raw)
  To: linux-ia64

David,

Since I applied your patch, I re-booted my Tiger-4 about 10 times
and I got twice the following Oops:

CPU 3: base freq\x199.453MHz, ITC ratio\x13/2, ITC freq\x1296.444MHz+/--1ppm
Calibrating delay loop... 1943.56 BogoMIPS
Oops: timer tick before it's due (itc—c85f8eed,itm—c87b85d7)
Oops: timer tick before it's due (itc—c8d4a7c7,itm—c8dc1d93)
Oops: timer tick before it's due (itc—c949bc39,itm—c95006db)

... some 100 of similar lines ...

Oops: timer tick before it's due (itc˜59824596,itm˜5985c2ef)
Oops: timer tick before it's due (itc˜59f75936,itm˜59f9ac37)
Oops: timer tick before it's due (itc˜5a6c6c40,itm˜5a6d957f)
CPU 3: synchronized ITC with CPU 0 (last diff -3 cycles, maxerr 494 cycles)

Once it is over, everything seems to be correct. E.g. I can stress
the system by compiling the kernel with "make -j100".
It's a 2.6.5 kernel.
I'm sure the new "sched_clock" code is O.K. I guess this modification
has brought to light a hidden bug in the initial CPU synchronization
or timing set up code.
Have you ever seen a similar problem ?

The 4 CPUs in the box are the same, like CPU #3:
processor  : 3
vendor     : GenuineIntel
arch       : IA-64
family     : Itanium 2
model      : 1
revision   : 5
archrev    : 0
features   : branchlong
cpu number : 0
cpu regs   : 4
cpu MHz    : 1296.444994
itc MHz    : 1296.444994
BogoMIPS   : 1941.96

Thanks,

Zoltán

^ permalink raw reply	[flat|nested] 3+ messages in thread

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2004-06-04 14:41 sched_clock - cont'd Zoltan Menyhart
2004-06-04 14:52 ` David Mosberger
2004-06-04 16:51 ` David Mosberger

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