Re: [Linux-ia64] re-enabling interrupts and interrupt collect

Re: [Linux-ia64] re-enabling interrupts and interrupt collect

[Chuck Fleckenstein]

Since the ssm of psr.i does not require serialization then I believe this
would
be expected.

so as you said the guaranteed method of safely reenabling ic and i would
be:

    ssm psr.ic
    ;;
    srlz.d
    ssm psr.i


Chuck


Jonathan Case Nicklin wrote:

> All,
>
> Recently, i was working on a section of code that disabled/enable
> interrupts
> and interrupt collection like so.
>
>     rsm psr.i | psr.ic
>     ;;
>     ... //body
>     ;;
>     ssm psr.i | psr.ic
>     ;;
>     srlz.d
>     ;;
>
> I found however that this implementation did not work under heavy loads.
>
> It took a while to figure out that a pending interrupt that had occurred
>
> in the body of code, executed while interrupts were turned off, was
> delivered
> after the ssm call as expected. However, it was delivered before the ic
> bit
> serialized. In the code this caused undesirable results. I found that
> the
> proper way to implement the above is to re-enable the ic bit and
> serialize
> before re-enabling the interrupt bit. Has anyone else come across this
> problem and can anybody shed some light on whether this is the expected
> operation.
>
> Sincerely,
> Jonathan Case Nicklin
>
> Mission Critical Linux
> www.missioncriticallinux.com
>
> ps. The manual gives an example of the implementation that works, but
> does
> not provide any explanation of implementation itself (as far as I can
> see ;-P )
>
> _______________________________________________
> Linux-IA64 mailing list
> Linux-IA64@linuxia64.org
> http://lists.linuxia64.org/lists/listinfo/linux-ia64

[Linux-ia64] re-enabling interrupts and interrupt collect

[Jonathan Case Nicklin]

All,

Recently, i was working on a section of code that disabled/enable
interrupts
and interrupt collection like so.

    rsm psr.i | psr.ic
    ;;
    ... //body
    ;;
    ssm psr.i | psr.ic
    ;;
    srlz.d
    ;;

I found however that this implementation did not work under heavy loads.

It took a while to figure out that a pending interrupt that had occurred

in the body of code, executed while interrupts were turned off, was
delivered
after the ssm call as expected. However, it was delivered before the ic
bit
serialized. In the code this caused undesirable results. I found that
the
proper way to implement the above is to re-enable the ic bit and
serialize
before re-enabling the interrupt bit. Has anyone else come across this
problem and can anybody shed some light on whether this is the expected
operation.

Sincerely,
Jonathan Case Nicklin

Mission Critical Linux
www.missioncriticallinux.com

ps. The manual gives an example of the implementation that works, but
does
not provide any explanation of implementation itself (as far as I can
see ;-P )

Re: [Linux-ia64] re-enabling interrupts and interrupt collect

[David Mosberger]

Yes, psr.ic needs to be on before psr.i can be turned on.  That's what
we are doing in ivt.S, for example.  I thought the manual was quite
clear on that topic.

	--david

>>>>> On Wed, 08 Nov 2000 08:28:32 -0500, Jonathan Case Nicklin <nicklin@missioncriticallinux.com> said:

  Jonathan> All, Recently, i was working on a section of code that
  Jonathan> disabled/enable interrupts and interrupt collection like
  Jonathan> so.

  Jonathan>     rsm psr.i | psr.ic ;; ... //body ;; ssm psr.i | psr.ic
  Jonathan> ;; srlz.d ;;

  Jonathan> I found however that this implementation did not work
  Jonathan> under heavy loads.

  Jonathan> It took a while to figure out that a pending interrupt
  Jonathan> that had occurred in the body of code, executed while
  Jonathan> interrupts were turned off, was delivered after the ssm
  Jonathan> call as expected. However, it was delivered before the ic
  Jonathan> bit serialized. In the code this caused undesirable
  Jonathan> results. I found that the proper way to implement the
  Jonathan> above is to re-enable the ic bit and serialize before
  Jonathan> re-enabling the interrupt bit. Has anyone else come across
  Jonathan> this problem and can anybody shed some light on whether
  Jonathan> this is the expected operation.

  Jonathan> Sincerely, Jonathan Case Nicklin

  Jonathan> Mission Critical Linux www.missioncriticallinux.com

  Jonathan> ps. The manual gives an example of the implementation that
  Jonathan> works, but does not provide any explanation of
  Jonathan> implementation itself (as far as I can see ;-P )

RE: [Linux-ia64] re-enabling interrupts and interrupt collect

[Mallick, Asit K]

Setting the PSR.ic or PSR.i is not implicitly serialized and setting both
PSR.ic and PSR.i in a single instruction could create a timing window where
PSR.ic=0 and PSR.i=1. So, software must set the PSR.ic explicitly before
setting the PSR.i.

Asit


> -----Original Message-----
> From: Chuck Fleckenstein [mailto:cfleck@co.intel.com]
> Sent: Wednesday, November 08, 2000 2:07 AM
> To: Jonathan Case Nicklin
> Cc: linux-ia64@ia64linux.org
> Subject: Re: [Linux-ia64] re-enabling interrupts and interrupt collect
> 
> 
> Since the ssm of psr.i does not require serialization then I 
> believe this
> would
> be expected.
> 
> so as you said the guaranteed method of safely reenabling ic 
> and i would
> be:
> 
>     ssm psr.ic
>     ;;
>     srlz.d
>     ssm psr.i
> 
> 
> Chuck
> 
> 
> Jonathan Case Nicklin wrote:
> 
> > All,
> >
> > Recently, i was working on a section of code that disabled/enable
> > interrupts
> > and interrupt collection like so.
> >
> >     rsm psr.i | psr.ic
> >     ;;
> >     ... //body
> >     ;;
> >     ssm psr.i | psr.ic
> >     ;;
> >     srlz.d
> >     ;;
> >
> > I found however that this implementation did not work under 
> heavy loads.
> >
> > It took a while to figure out that a pending interrupt that 
> had occurred
> >
> > in the body of code, executed while interrupts were turned off, was
> > delivered
> > after the ssm call as expected. However, it was delivered 
> before the ic
> > bit
> > serialized. In the code this caused undesirable results. I 
> found that
> > the
> > proper way to implement the above is to re-enable the ic bit and
> > serialize
> > before re-enabling the interrupt bit. Has anyone else come 
> across this
> > problem and can anybody shed some light on whether this is 
> the expected
> > operation.
> >
> > Sincerely,
> > Jonathan Case Nicklin
> >
> > Mission Critical Linux
> > www.missioncriticallinux.com
> >
> > ps. The manual gives an example of the implementation that 
> works, but
> > does
> > not provide any explanation of implementation itself (as 
> far as I can
> > see ;-P )
> >
> > _______________________________________________
> > Linux-IA64 mailing list
> > Linux-IA64@linuxia64.org
> > http://lists.linuxia64.org/lists/listinfo/linux-ia64
> 
> 
> _______________________________________________
> Linux-IA64 mailing list
> Linux-IA64@linuxia64.org
> http://lists.linuxia64.org/lists/listinfo/linux-ia64
>