[Linux-ia64] IA64 software pipelining

[Linux-ia64] IA64 software pipelining

[dai yiyang]

Hi all,

   I am trying to test the software pipelining with the following code ,
----------------------------------
int swp(int m,int *a,int *b){
        int i;
#pragma swp
        for (i=0; i<m ; i++)
        {
                    b[i]=a[i]+1;

         }
        return i;
}
------------------------------------
I expect , for better performence , the code should be compiled somewhat 
like this:
------------------------
      mov ar.lc=r32
      mov ar.ec=4
      mov pr.rot=0x1000
loop:
(p16) ld8 r35=[r9],8
(p18) add r37=r36,r0,1
(p19) st8 [r6]=r38,8
      br.ctop loop;;
-------------------------
but it seems the Intel compiler7.1 can not produce software pipelining for 
this code like what I expected .
with -opt_report_file option , I got such tip:
-----------------------------

Swp report for loop at line 6 in swp in file swp.c

         Modulo scheduling failed. Most likely, this was
         caused by loop-carried memory dependences.

         Following are the loop-carried memory dependence edges:
         Store  at line     6 --> Load   at line     6

-----------------------------
any advice ?

Regards,
Yiyang



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Re: [Linux-ia64] IA64 software pipelining

[Hans Boehm]

The compiler has no way to tell whether a a and b point into the same
array, in which case it might not be correct to pipeline the loop.

Try using

int swp(int m,int * restrict a,int * restrict b)

instead.

Hans

On Sun, 20 Apr 2003, dai yiyang wrote:

> 
> Hi all,
> 
>    I am trying to test the software pipelining with the following code ,
> ----------------------------------
> int swp(int m,int *a,int *b){
>         int i;
> #pragma swp
>         for (i=0; i<m ; i++)
>         {
>                     b[i]=a[i]+1;
> 
>          }
>         return i;
> }
> ------------------------------------
> I expect , for better performence , the code should be compiled somewhat 
> like this:
> ------------------------
>       mov ar.lc=r32
>       mov ar.ec=4
>       mov pr.rot=0x1000
> loop:
> (p16) ld8 r35=[r9],8
> (p18) add r37=r36,r0,1
> (p19) st8 [r6]=r38,8
>       br.ctop loop;;
> -------------------------
> but it seems the Intel compiler7.1 can not produce software pipelining for 
> this code like what I expected .
> with -opt_report_file option , I got such tip:
> -----------------------------
> 
> Swp report for loop at line 6 in swp in file swp.c
> 
>          Modulo scheduling failed. Most likely, this was
>          caused by loop-carried memory dependences.
> 
>          Following are the loop-carried memory dependence edges:
>          Store  at line     6 --> Load   at line     6
> 
> -----------------------------
> any advice ?
> 
> Regards,
> Yiyang
> 
> 
> 
> _________________________________________________________________
> 与联机的朋友进行交流，请使用 MSN Messenger:  http://messenger.msn.com/cn  
> 
> 
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> Linux-IA64 mailing list
> Linux-IA64@linuxia64.org
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> 

-- 
Hans Boehm
(hboehm@hpl.hp.com)