pal/power_info for real?

pal/power_info for real?

[Duraid Madina]

Hi all,

	/proc/pal/cpu0/power_info on my system reads:

Power level 0:
         entry_latency       : 9000 cycles
         exit_latency        : 8700 cycles
         power consumption   : 52000 mW
         Cache+TLB coherency : Yes
Power level 1: not implemented
Power level 2:
         entry_latency       : 14000 cycles
         exit_latency        : 8700 cycles
         power consumption   : 52000 mW
         Cache+TLB coherency : Yes
Power level 3: not implemented
Power level 4: not implemented
Power level 5: not implemented
Power level 6: not implemented
Power level 7: not implemented


	Is this correct? Two power levels, with different entry latencies, but 
the same power consumption?

	Bracing myself for a particularly warm summer,

	Duraid

Re: pal/power_info for real?

[Alex Williamson]

On Tue, 2003-11-25 at 02:09, Duraid Madina wrote:
> 	Is this correct? Two power levels, with different entry latencies, but 
> the same power consumption?

  Yep, power level 0 is light_halt and 2 is halt2.  I can't really
comment on the power consumption, but presumably they're shutting down
different portions of the chip.  I see the same thing on my boxes.  Note
that these are all halt state power consumptions, not full running power
consumption.

	Alex

-- 
Alex Williamson                             HP Linux & Open Source Lab