Re: Acard ATP8620 2SATA / 1 IDE driver - AHCI.C Nov082007

Re: Acard ATP8620 2SATA / 1 IDE driver - AHCI.C Nov082007

[Jeff Garzik]

On Thu, Nov 08, 2007 at 07:34:22PM +0800, jameshsu wrote:
> From: LaurenceWu

> We didn't study about ata/ahci.c, but it should be based on AHCI1.0 or 1.1
> spec. That is, NO P.M. FIS base switching, but supports both non-NCQ and NCQ
> protocols.
> 
> For NCQ or nonNCQ, 8620 is very AHCI-like, although not fully compatible,
> programmer can easily modify standard ahci.c
> for 8620. The main differences between 8620 and AHCI are :
> 
> 1. PRD table format changed, (please compare AHCI 1.x section 4.2.3.3 and
> 8620 datasheet section 7.3), 'I' bit in 8620 is defined as 'EOT' and NO
> PRDTL value are available in the
>     Command List Structure.
> 
> 2. For NCQ transfer, PxIS bit 3(SDBS) is changed. ATP8620 add the Reg_144h
> to accumulate 32 Sactive bits in each SDB FIS.
>     The Reg_144h is RWC and all its 32 bits are 'ORed'  to form the PxIS
> bit3 and interrupt, if PxIE bit 3 enabled.
> 
> Yes.  Modifying the ata/ahci.c is OK to support atp8620.

This is good information, thanks.

After studying the datasheet I also noted a couple differences:

1) Port Multiplier support appears different from standard AHCI.

2) This chip includes target mode support.  Very nice, well done!
I hope that standard AHCI eventually supports this nice feature!

	Jeff

Re: Acard ATP8620 2SATA / 1 IDE driver - AHCI.C Nov082007

[Mark Lord]

Jeff Garzik wrote:
>..
> 2) This chip includes target mode support.  Very nice, well done!
> I hope that standard AHCI eventually supports this nice feature!
..

Speaking of which.  Do we have a strategy as to how to implement/support
the target side of target mode on controllers which can do it?

The Marvell chips also have a target mode feature, and I'd like to add
support for it soon-ish, but it's now clear how you would like it plumbed
into libata.

It's almost like a separate driver/subsystem, except that would be very silly.

???

Re: Acard ATP8620 2SATA / 1 IDE driver - AHCI.C Nov082007

[Jeff Garzik]

On Thu, Nov 08, 2007 at 02:52:26PM -0500, Mark Lord wrote:
> Jeff Garzik wrote:
> >..
> >2) This chip includes target mode support.  Very nice, well done!
> >I hope that standard AHCI eventually supports this nice feature!
> ..
> 
> Speaking of which.  Do we have a strategy as to how to implement/support
> the target side of target mode on controllers which can do it?
> 
> The Marvell chips also have a target mode feature, and I'd like to add
> support for it soon-ish, but it's now clear how you would like it plumbed
> into libata.
> 
> It's almost like a separate driver/subsystem, except that would be very 
> silly.

I'm letting the SCSI folks do the heavy lifting, implementing SCSI
target mode -- an effort already quite well along.

We should be able to piggyback off of that work.

	Jeff

Re: Acard ATP8620 2SATA / 1 IDE driver - AHCI.C Nov082007

[Mark Lord]

Jeff Garzik wrote:
> On Thu, Nov 08, 2007 at 02:52:26PM -0500, Mark Lord wrote:
>> Jeff Garzik wrote:
>>> ..
>>> 2) This chip includes target mode support.  Very nice, well done!
>>> I hope that standard AHCI eventually supports this nice feature!
>> ..
>>
>> Speaking of which.  Do we have a strategy as to how to implement/support
>> the target side of target mode on controllers which can do it?
>>
>> The Marvell chips also have a target mode feature, and I'd like to add
>> support for it soon-ish, but it's now clear how you would like it plumbed
>> into libata.
>>
>> It's almost like a separate driver/subsystem, except that would be very 
>> silly.
> 
> I'm letting the SCSI folks do the heavy lifting, implementing SCSI
> target mode -- an effort already quite well along.
> 
> We should be able to piggyback off of that work.
..

MMmm..  I wonder what the most common use case is for target mode?

Everybody I've dealt with thus far uses it as a high-speed local comms interface,
which would suggest that it might be done as a network interface (ethernet emulation).

But that would confusingly go across driver subsystems,
despite that this is how it actually is used.

Re: Acard ATP8620 2SATA / 1 IDE driver - AHCI.C Nov082007

[Jeff Garzik]

On Thu, Nov 08, 2007 at 03:19:52PM -0500, Mark Lord wrote:
> Jeff Garzik wrote:
> >On Thu, Nov 08, 2007 at 02:52:26PM -0500, Mark Lord wrote:
> >>Jeff Garzik wrote:
> >>>..
> >>>2) This chip includes target mode support.  Very nice, well done!
> >>>I hope that standard AHCI eventually supports this nice feature!
> >>..
> >>
> >>Speaking of which.  Do we have a strategy as to how to implement/support
> >>the target side of target mode on controllers which can do it?
> >>
> >>The Marvell chips also have a target mode feature, and I'd like to add
> >>support for it soon-ish, but it's now clear how you would like it plumbed
> >>into libata.
> >>
> >>It's almost like a separate driver/subsystem, except that would be very 
> >>silly.
> >
> >I'm letting the SCSI folks do the heavy lifting, implementing SCSI
> >target mode -- an effort already quite well along.
> >
> >We should be able to piggyback off of that work.
> ..
> 
> MMmm..  I wonder what the most common use case is for target mode?
> 
> Everybody I've dealt with thus far uses it as a high-speed local comms 
> interface,
> which would suggest that it might be done as a network interface (ethernet 
> emulation).
> 
> But that would confusingly go across driver subsystems,
> despite that this is how it actually is used.

The low-level driver itself will just be a dumb DMA send/receive engine,
with submit/completion APIs highly similar to the existing ones.  Then
you can easily provide a network interface interface (not a typo) on top
of that.

The biggest use case I've seen is in the embedded space, where you
really are creating a SCSI (or ATA) target, that appears to the
initiator/client to be a real SCSI-or-ATA device.

There are certainly other uses:  networking, creating a cheap SATA bus
analyzer, creating a cheap SATA bridge, ...

My main goal is to ensure that the low-level driver is as simple as
possible, which permits upper layers to actually figure out what
purposes it shall use.

Modern SATA is just a DMA engine with PHY control anyway (just like
networking), so we really just need to be sure to abstract away
initiator-mode (aka host mode) specifics in drivers that support target
mode.

	Jeff

Re: Acard ATP8620 2SATA / 1 IDE driver - AHCI.C Nov082007

[jameshsu]

Jeff,

First, appreciate for taking few minutes to answer my short question:

1) How is the status of ACARD Linux SATA driver after spec studying??.
Any progress and any qustion/help needed from Acard, esp., AHCI support??
If you have draft open source(driver) now, do you mind to share with us!
Please advise! Thanks!

Best regards & happy holiday season!

James
----- Original Message -----
From: Jeff Garzik
To: jameshsu
Cc: Jason Wu ; LaurenceWu ; Andrew Morton ; IDE/ATA development list ;
tytso@us.ibm.com ; Matti Aarnio ; James Bottomley ; Daniel Weng
Sent: Friday, November 09, 2007 12:22 AM
Subject: Re: Acard ATP8620 2SATA / 1 IDE driver - AHCI.C Nov082007


On Thu, Nov 08, 2007 at 07:34:22PM +0800, jameshsu wrote:
> From: LaurenceWu

> We didn't study about ata/ahci.c, but it should be based on AHCI1.0 or 1.1
> spec. That is, NO P.M. FIS base switching, but supports both non-NCQ and
NCQ
> protocols.
>
> For NCQ or nonNCQ, 8620 is very AHCI-like, although not fully compatible,
> programmer can easily modify standard ahci.c
> for 8620. The main differences between 8620 and AHCI are :
>
> 1. PRD table format changed, (please compare AHCI 1.x section 4.2.3.3 and
> 8620 datasheet section 7.3), 'I' bit in 8620 is defined as 'EOT' and NO
> PRDTL value are available in the
>     Command List Structure.
>
> 2. For NCQ transfer, PxIS bit 3(SDBS) is changed. ATP8620 add the Reg_144h
> to accumulate 32 Sactive bits in each SDB FIS.
>     The Reg_144h is RWC and all its 32 bits are 'ORed'  to form the PxIS
> bit3 and interrupt, if PxIE bit 3 enabled.
>
> Yes.  Modifying the ata/ahci.c is OK to support atp8620.

This is good information, thanks.

After studying the datasheet I also noted a couple differences:

1) Port Multiplier support appears different from standard AHCI.

2) This chip includes target mode support.  Very nice, well done!
I hope that standard AHCI eventually supports this nice feature!

Jeff

Re: Acard ATP8620 2SATA / 1 IDE driver - AHCI.C Nov082007

[jameshsu]

Jeff,

Do you know who has SATA sample driver w/ AHCI support for reference (esp., 
for Acard SATA chip)??
If possible, please advise in your earlier convenience ! Appreciate for your 
help!
James
----- Original Message ----- 
From: jameshsu
To: Jeff Garzik
Cc: James Bottomley ; Matti Aarnio ; tytso@us.ibm.com ; IDE/ATA development 
list ; Andrew Morton
Sent: Tuesday, November 27, 2007 6:18 PM
Subject: Re: Acard ATP8620 2SATA / 1 IDE driver - AHCI.C Nov082007


Jeff,

First, appreciate for taking few minutes to answer my short question:

1) How is the status of ACARD Linux SATA driver after spec studying??.
Any progress and any qustion/help needed from Acard, esp., AHCI support??
If you have draft open source(driver) now, do you mind to share with us!
Please advise! Thanks!

Best regards & happy holiday season!

James
----- Original Message -----
From: Jeff Garzik
To: jameshsu
Cc: Jason Wu ; LaurenceWu ; Andrew Morton ; IDE/ATA development list ;
tytso@us.ibm.com ; Matti Aarnio ; James Bottomley ; Daniel Weng
Sent: Friday, November 09, 2007 12:22 AM
Subject: Re: Acard ATP8620 2SATA / 1 IDE driver - AHCI.C Nov082007


On Thu, Nov 08, 2007 at 07:34:22PM +0800, jameshsu wrote:
> From: LaurenceWu

> We didn't study about ata/ahci.c, but it should be based on AHCI1.0 or 1.1
> spec. That is, NO P.M. FIS base switching, but supports both non-NCQ and
NCQ
> protocols.
>
> For NCQ or nonNCQ, 8620 is very AHCI-like, although not fully compatible,
> programmer can easily modify standard ahci.c
> for 8620. The main differences between 8620 and AHCI are :
>
> 1. PRD table format changed, (please compare AHCI 1.x section 4.2.3.3 and
> 8620 datasheet section 7.3), 'I' bit in 8620 is defined as 'EOT' and NO
> PRDTL value are available in the
>     Command List Structure.
>
> 2. For NCQ transfer, PxIS bit 3(SDBS) is changed. ATP8620 add the Reg_144h
> to accumulate 32 Sactive bits in each SDB FIS.
>     The Reg_144h is RWC and all its 32 bits are 'ORed'  to form the PxIS
> bit3 and interrupt, if PxIE bit 3 enabled.
>
> Yes.  Modifying the ata/ahci.c is OK to support atp8620.

This is good information, thanks.

After studying the datasheet I also noted a couple differences:

1) Port Multiplier support appears different from standard AHCI.

2) This chip includes target mode support.  Very nice, well done!
I hope that standard AHCI eventually supports this nice feature!

Jeff