[PATCH v5 0/3] ahci: enable ahci sata support on imx6q

[PATCH v5 0/3] ahci: enable ahci sata support on imx6q

[Richard Zhu]

V5: add imx6q specific ahci sata support
  - Fix the wrong referrence usage of the private data.
  - Use the private data to contain the poninter of the PHY
  signals adjustment window(gpr)
  - Tested on imx6q sd board.
  - 

v4: http://www.spinics.net/lists/linux-ide/msg45699.html
  Thanks for the review comments provided by Sascha, and Alexander.
  - Use the private data and keep a pointer to the PHY clock.
  - Don't use the global platform device variable, because that
  it would make the driver broken for mutiple instances.
  - Don't do the "writel" with assignment.
  - Other minor changes, such as print the error code when printing
  error message, use a u32 type to store readl results, and so on.

v3: http://www.spinics.net/lists/linux-ide/msg45688.html
  - Keep arch/arm and ahci_platform driver clean.
  - Add the sata_imx standalone driver contained all the
  specific setup
  - Add the release function, support the loadable module
  driver.
  - Tested on imx6q sd board.

v2: http://www.spinics.net/lists/linux-ide/msg45666.html 
 - Setup standalone imx ahci sata driver, because of
 the misalignments of the bits definition of the HBA register.
 - Replace the node by the label in the board dts.
 - 

v1: http://www.spinics.net/lists/linux-ide/msg45581.html
 - add imx6q specific ahci sata support to arch/arm/mach-imx/mach-imx6q.c

These patches is based on imx/dt branch of
"http://git.linaro.org/git-ro/people/shawnguo/linux-2.6.git"

[v5 1/3] ARM: dtsi: enable ahci sata on imx6q platforms
[v5 2/3] ARM: imx6q: update the sata bits definitions of gpr13
[v5 3/3] sata: imx: add ahci sata support on imx platforms

arch/arm/boot/dts/imx6q-sabreauto.dts       |    4 +
arch/arm/boot/dts/imx6q-sabrelite.dts       |    4 +
arch/arm/boot/dts/imx6q-sabresd.dts         |    4 +
arch/arm/boot/dts/imx6q.dtsi                |    9 +
drivers/ata/Kconfig                         |    9 +
drivers/ata/Makefile                        |    1 +
drivers/ata/sata_imx.c                      |  233 +++++++++++++++++++++++++++
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h |  121 ++++++++++-----
8 files changed, 348 insertions(+), 37 deletions(-)

[v5 1/3] ARM: dtsi: enable ahci sata on imx6q platforms

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

Only imx6q has the ahci sata controller, enable
it on imx6q platforms.

Signed-off-by: Richard Zhu <r65037@freescale.com>
---
 arch/arm/boot/dts/imx6q-sabreauto.dts |    4 ++++
 arch/arm/boot/dts/imx6q-sabrelite.dts |    4 ++++
 arch/arm/boot/dts/imx6q-sabresd.dts   |    4 ++++
 arch/arm/boot/dts/imx6q.dtsi          |    9 +++++++++
 4 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 09a7580..5cd5209 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -20,6 +20,10 @@
 	compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
 };
 
+&ahci {
+	status = "okay";
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 6a00066..6bf6fec 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -65,6 +65,10 @@
 	};
 };
 
+&ahci {
+	status = "okay";
+};
+
 &ecspi1 {
 	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio3 19 0>;
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 0038228..d0579b8 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -20,6 +20,10 @@
 	compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
 };
 
+&ahci {
+	status = "okay";
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e7dd2c4..40db926 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -424,6 +424,15 @@
 			};
 		};
 
+		ahci: ahci@02200000 {
+			compatible = "fsl,imx6q-ahci";
+			reg = <0x02200000 0x4000>;
+			interrupts = <0 39 0x04>;
+			clocks = <&clks 154>, <&clks 187>;
+			clock-names = "sata", "sata_ref";
+			status = "disabled";
+		};
+
 		ipu2: ipu@02800000 {
 			#crtc-cells = <1>;
 			compatible = "fsl,imx6q-ipu";
-- 
1.7.5.4

[v5 2/3] ARM: imx6q: update the sata bits definitions of gpr13

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

Replace the SATA_PHY_# by the more readable definitons.

Signed-off-by: Richard Zhu <r65037@freescale.com>
---
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h |  121 ++++++++++++++++++--------
 1 files changed, 84 insertions(+), 37 deletions(-)

diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index dab34a1..e235251 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -279,41 +279,88 @@
 #define IMX6Q_GPR13_CAN2_STOP_REQ		BIT(29)
 #define IMX6Q_GPR13_CAN1_STOP_REQ		BIT(28)
 #define IMX6Q_GPR13_ENET_STOP_REQ		BIT(27)
-#define IMX6Q_GPR13_SATA_PHY_8_MASK		(0x7 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB		(0x0 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB		(0x1 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB		(0x2 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB		(0x3 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB		(0x4 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB		(0x5 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB		(0x6 << 24)
-#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB		(0x7 << 24)
-#define IMX6Q_GPR13_SATA_PHY_7_MASK		(0x1f << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1I		(0x10 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1M		(0x10 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA1X		(0x1a << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2I		(0x12 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2M		(0x12 << 19)
-#define IMX6Q_GPR13_SATA_PHY_7_SATA2X		(0x1a << 19)
-#define IMX6Q_GPR13_SATA_PHY_6_MASK		(0x7 << 16)
-#define IMX6Q_GPR13_SATA_SPEED_MASK		BIT(15)
-#define IMX6Q_GPR13_SATA_SPEED_1P5G		0x0
-#define IMX6Q_GPR13_SATA_SPEED_3P0G		BIT(15)
-#define IMX6Q_GPR13_SATA_PHY_5			BIT(14)
-#define IMX6Q_GPR13_SATA_PHY_4_MASK		(0x7 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_16_16		(0x0 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_14_16		(0x1 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_12_16		(0x2 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_10_16		(0x3 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_9_16		(0x4 << 11)
-#define IMX6Q_GPR13_SATA_PHY_4_8_16		(0x5 << 11)
-#define IMX6Q_GPR13_SATA_PHY_3_MASK		(0xf << 7)
-#define IMX6Q_GPR13_SATA_PHY_3_OFF		0x7
-#define IMX6Q_GPR13_SATA_PHY_2_MASK		(0x1f << 2)
-#define IMX6Q_GPR13_SATA_PHY_2_OFF		0x2
-#define IMX6Q_GPR13_SATA_PHY_1_MASK		(0x3 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_FAST		(0x0 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_MED		(0x1 << 0)
-#define IMX6Q_GPR13_SATA_PHY_1_SLOW		(0x2 << 0)
-
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK		(0x7 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB	(0x0 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB	(0x1 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB	(0x2 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB	(0x3 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB	(0x4 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB	(0x5 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB	(0x6 << 24)
+#define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB	(0x7 << 24)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK	(0x1f << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I	(0x10 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M	(0x10 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X	(0x1a << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I	(0x12 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M	(0x12 << 19)
+#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X	(0x1a << 19)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK	(0x7 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F	(0x0 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F	(0x1 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F	(0x2 << 16)
+#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F	(0x3 << 16)
+#define IMX6Q_GPR13_SATA_SPD_MODE_MASK		BIT(15)
+#define IMX6Q_GPR13_SATA_SPD_MODE_1P5G		0x0
+#define IMX6Q_GPR13_SATA_SPD_MODE_3P0G		BIT(15)
+#define IMX6Q_GPR13_SATA_MPLL_SS_EN		BIT(14)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_MASK		(0x7 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_16_16		(0x0 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_14_16		(0x1 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_12_16		(0x2 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_10_16		(0x3 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_9_16		(0x4 << 11)
+#define IMX6Q_GPR13_SATA_TX_ATTEN_8_16		(0x5 << 11)
+#define IMX6Q_GPR13_SATA_TX_BOOST_MASK		(0xf << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB	(0x0 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB	(0x1 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB	(0x2 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB	(0x3 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB	(0x4 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB	(0x5 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB	(0x6 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB	(0x7 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB	(0x8 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB	(0x9 << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB	(0xa << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB	(0xb << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB	(0xc << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB	(0xd << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB	(0xe << 7)
+#define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB	(0xf << 7)
+#define IMX6Q_GPR13_SATA_TX_LVL_MASK		(0x1f << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_937_V		(0x00 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_947_V		(0x01 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_957_V		(0x02 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_966_V		(0x03 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_976_V		(0x04 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_986_V		(0x05 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_0_996_V		(0x06 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_005_V		(0x07 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_015_V		(0x08 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_025_V		(0x09 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_035_V		(0x0a << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_045_V		(0x0b << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_054_V		(0x0c << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_064_V		(0x0d << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_074_V		(0x0e << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_084_V		(0x0f << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_094_V		(0x10 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_104_V		(0x11 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_113_V		(0x12 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_123_V		(0x13 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_133_V		(0x14 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_143_V		(0x15 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_152_V		(0x16 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_162_V		(0x17 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_172_V		(0x18 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_182_V		(0x19 << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_191_V		(0x1a << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_201_V		(0x1b << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_211_V		(0x1c << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_221_V		(0x1d << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_230_V		(0x1e << 2)
+#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V		(0x1f << 2)
+#define IMX6Q_GPR13_SATA_MPLL_CLK_EN		BIT(1)
+#define IMX6Q_GPR13_SATA_TX_EDGE_RATE		BIT(0)
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
-- 
1.7.5.4

[v5 3/3] sata: imx: add ahci sata support on imx platforms

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

imx6q contains one Synopsys AHCI SATA controller,
But it can't shares ahci_platform driver with other
controllers.
Because there are some misalignments of the generic
AHCI controller.
The bits definitions of the HBA registers, the Vendor
Specific registers, the AHCI PHY clock and the AHCI
signals adjustment window(GPR13 Reg).
 - CAP_SSS(bit20) of the HOST_CAP is writable, default
 value is '0', should be configured to be '1'
 - bit0 (only one AHCI SATA port on imx6q) of the
 HOST_PORTS_IMPL should be set to be '1'.(default 0)
 - One Vendor Specific register HOST_TIMER1MS(offset:0xe0)
 should be configured regarding to the frequency of AHB
 bus clock.
 - Configurations of the AHCI PHY clock, and the signal
 parameters of the GPR13

Setup its own ahci sata driver, contained the imx6q specific
initialized codes, re-use the generic ahci_platform drier, and
keep the generic ahci_platform driver clean as much as possible.

Signed-off-by: Richard Zhu <r65037@freescale.com>
---
 drivers/ata/Kconfig    |    9 ++
 drivers/ata/Makefile   |    1 +
 drivers/ata/sata_imx.c |  233 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 243 insertions(+), 0 deletions(-)
 create mode 100644 drivers/ata/sata_imx.c

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index a5a3ebc..275dc2c 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -97,6 +97,15 @@ config SATA_AHCI_PLATFORM
 
 	  If unsure, say N.
 
+config SATA_IMX
+	tristate "Freescale i.MX AHCI SATA support"
+	depends on SATA_AHCI_PLATFORM
+	help
+	  This option enables support for the Freescale i.MX SoC's
+	  onboard AHCI SATA.
+
+	  If unsure, say N.
+
 config SATA_FSL
 	tristate "Freescale 3.0Gbps SATA support"
 	depends on FSL_SOC
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index c04d0fd..04b1c6c 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SATA_INIC162X)	+= sata_inic162x.o
 obj-$(CONFIG_SATA_SIL24)	+= sata_sil24.o
 obj-$(CONFIG_SATA_DWC)		+= sata_dwc_460ex.o
 obj-$(CONFIG_SATA_HIGHBANK)	+= sata_highbank.o libahci.o
+obj-$(CONFIG_SATA_IMX)		+= sata_imx.o
 
 # SFF w/ custom DMA
 obj-$(CONFIG_PDC_ADMA)		+= pdc_adma.o
diff --git a/drivers/ata/sata_imx.c b/drivers/ata/sata_imx.c
new file mode 100644
index 0000000..de6330e
--- /dev/null
+++ b/drivers/ata/sata_imx.c
@@ -0,0 +1,233 @@
+/*
+ * Freescale IMX AHCI SATA platform driver
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/ahci_platform.h>
+#include <linux/of_device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include "ahci.h"
+
+enum {
+	HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
+};
+
+struct imx_ahci_priv {
+	struct platform_device *imx_ahci_pdev;
+	struct clk *sata_ref_clk;
+	struct regmap *gpr;
+};
+
+/* imx6q ahci module initialization. */
+static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
+{
+	int ret = 0;
+	unsigned int rc;
+	struct clk *ahb_clk;
+	struct device *p_dev = dev->parent;
+	struct imx_ahci_priv *imxpriv =  dev_get_drvdata(p_dev);
+
+	imxpriv->gpr =
+		syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+	if (IS_ERR(imxpriv->gpr)) {
+		dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
+		return PTR_ERR(imxpriv->gpr);
+	}
+
+	imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
+	if (IS_ERR(imxpriv->sata_ref_clk)) {
+		dev_err(dev, "can't get sata_ref clock.\n");
+		return PTR_ERR(imxpriv->sata_ref_clk);
+	}
+
+	ret = clk_prepare_enable(imxpriv->sata_ref_clk);
+	if (ret < 0) {
+		dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * set PHY Paremeters, two steps to configure the GPR13,
+	 * one write for rest of parameters, mask of first write
+	 * is 0x07fffffd, and the other one write for setting
+	 * the mpll_clk_en.
+	 */
+	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
+			| IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
+			| IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
+			| IMX6Q_GPR13_SATA_SPD_MODE_MASK
+			| IMX6Q_GPR13_SATA_MPLL_SS_EN
+			| IMX6Q_GPR13_SATA_TX_ATTEN_MASK
+			| IMX6Q_GPR13_SATA_TX_BOOST_MASK
+			| IMX6Q_GPR13_SATA_TX_LVL_MASK
+			| IMX6Q_GPR13_SATA_TX_EDGE_RATE
+			, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
+			| IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
+			| IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
+			| IMX6Q_GPR13_SATA_SPD_MODE_3P0G
+			| IMX6Q_GPR13_SATA_MPLL_SS_EN
+			| IMX6Q_GPR13_SATA_TX_ATTEN_9_16
+			| IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
+			| IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
+	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
+			IMX6Q_GPR13_SATA_MPLL_CLK_EN);
+	usleep_range(100, 200);
+
+	/*
+	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
+	 * and IP vendor specific register HOST_TIMER1MS.
+	 *
+	 * Configure CAP_SSS (support stagered spin up).
+	 * Implement the port0.
+	 * Get the ahb clock rate, and configure the TIMER1MS register.
+	 */
+	rc = readl(mmio + HOST_CAP);
+	if (!(rc & HOST_CAP_SSS)) {
+		rc |= HOST_CAP_SSS;
+		writel(rc, mmio + HOST_CAP);
+	}
+	rc = readl(mmio + HOST_PORTS_IMPL);
+	if (!(rc & 0x1)) {
+		rc |= 0x1;
+		writel(rc, mmio + HOST_PORTS_IMPL);
+	}
+
+	ahb_clk = devm_clk_get(dev, "ahb");
+	if (IS_ERR(ahb_clk)) {
+		dev_err(dev, "no ahb clock.\n");
+		clk_disable_unprepare(imxpriv->sata_ref_clk);
+		devm_clk_put(dev, imxpriv->sata_ref_clk);
+		return PTR_ERR(ahb_clk);
+	}
+	rc = clk_get_rate(ahb_clk) / 1000;
+	writel(rc, mmio + HOST_TIMER1MS);
+	devm_clk_put(dev, ahb_clk);
+
+	return 0;
+}
+
+static void imx6q_sata_exit(struct device *dev)
+{
+	struct device *p_dev = dev->parent;
+	struct imx_ahci_priv *imxpriv =  dev_get_drvdata(p_dev);
+
+	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
+			!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
+	clk_disable_unprepare(imxpriv->sata_ref_clk);
+}
+
+static struct ahci_platform_data imx6q_sata_pdata = {
+	.init = imx6q_sata_init,
+	.exit = imx6q_sata_exit,
+};
+static const struct of_device_id imx_ahci_of_match[] = {
+	{ .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
+	{},
+};
+MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
+
+static void imx_ahci_platform_release(struct device *dev)
+{
+	return;
+}
+
+static int imx_ahci_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *mem, *irq, res[2];
+	const struct of_device_id *of_id;
+	const struct ahci_platform_data *pdata = NULL;
+	struct imx_ahci_priv *imxpriv;
+	int ret;
+
+	struct device *imx_dev;
+	struct platform_device *imx_ahci_pdev;
+
+	imx_ahci_pdev = platform_device_alloc("ahci", -1);
+	if (!imx_ahci_pdev)
+		return -ENODEV;
+
+	imx_dev = &imx_ahci_pdev->dev;
+	imx_dev->release = imx_ahci_platform_release;
+	imx_dev->parent = dev;
+
+	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
+	if (!imxpriv) {
+		dev_err(dev, "can't alloc ahci_host_priv\n");
+		return -ENOMEM;
+	}
+
+	imxpriv->imx_ahci_pdev = imx_ahci_pdev;
+	platform_set_drvdata(pdev, imxpriv);
+
+	of_id = of_match_device(imx_ahci_of_match, dev);
+	if (of_id)
+		pdata = of_id->data;
+	else
+		return -EINVAL;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!mem || !irq) {
+		dev_err(dev, "no mmio/irq resource\n");
+		return -EINVAL;
+	}
+
+	res[0] = *mem;
+	res[1] = *irq;
+
+	imx_dev->coherent_dma_mask = DMA_BIT_MASK(32);
+	imx_dev->dma_mask = &imx_dev->coherent_dma_mask;
+	imx_dev->of_node = dev->of_node;
+
+	platform_device_add_resources(imx_ahci_pdev, res, 2);
+	platform_device_add_data(imx_ahci_pdev, pdata, sizeof(*pdata));
+
+	ret = platform_device_add(imx_ahci_pdev);
+
+	return ret;
+}
+
+static int imx_ahci_remove(struct platform_device *pdev)
+{
+	struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
+	struct platform_device *imx_ahci_pdev = imxpriv->imx_ahci_pdev;
+
+	platform_device_unregister(imx_ahci_pdev);
+	return 0;
+}
+
+static struct platform_driver imx_ahci_driver = {
+	.probe = imx_ahci_probe,
+	.remove = imx_ahci_remove,
+	.driver = {
+		.name = "sata-imx",
+		.owner = THIS_MODULE,
+		.of_match_table = imx_ahci_of_match,
+	},
+};
+module_platform_driver(imx_ahci_driver);
+
+MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
+MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("sata:imx");
-- 
1.7.5.4

Re: [v5 3/3] sata: imx: add ahci sata support on imx platforms

[Shawn Guo]

On Thu, Jul 11, 2013 at 05:10:31PM +0800, Richard Zhu wrote:
> From: Richard Zhu <r65037@freescale.com>
> 
> imx6q contains one Synopsys AHCI SATA controller,
> But it can't shares ahci_platform driver with other
> controllers.
> Because there are some misalignments of the generic
> AHCI controller.
> The bits definitions of the HBA registers, the Vendor
> Specific registers, the AHCI PHY clock and the AHCI
> signals adjustment window(GPR13 Reg).
>  - CAP_SSS(bit20) of the HOST_CAP is writable, default
>  value is '0', should be configured to be '1'
>  - bit0 (only one AHCI SATA port on imx6q) of the
>  HOST_PORTS_IMPL should be set to be '1'.(default 0)
>  - One Vendor Specific register HOST_TIMER1MS(offset:0xe0)
>  should be configured regarding to the frequency of AHB
>  bus clock.
>  - Configurations of the AHCI PHY clock, and the signal
>  parameters of the GPR13
> 
> Setup its own ahci sata driver, contained the imx6q specific
> initialized codes, re-use the generic ahci_platform drier, and

s/drier/driver

> keep the generic ahci_platform driver clean as much as possible.
> 
> Signed-off-by: Richard Zhu <r65037@freescale.com>
> ---
>  drivers/ata/Kconfig    |    9 ++
>  drivers/ata/Makefile   |    1 +
>  drivers/ata/sata_imx.c |  233 ++++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 243 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/ata/sata_imx.c
> 
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index a5a3ebc..275dc2c 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -97,6 +97,15 @@ config SATA_AHCI_PLATFORM
>  
>  	  If unsure, say N.
>  
> +config SATA_IMX
> +	tristate "Freescale i.MX AHCI SATA support"
> +	depends on SATA_AHCI_PLATFORM
> +	help
> +	  This option enables support for the Freescale i.MX SoC's
> +	  onboard AHCI SATA.
> +
> +	  If unsure, say N.
> +
>  config SATA_FSL
>  	tristate "Freescale 3.0Gbps SATA support"
>  	depends on FSL_SOC
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> index c04d0fd..04b1c6c 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_SATA_INIC162X)	+= sata_inic162x.o
>  obj-$(CONFIG_SATA_SIL24)	+= sata_sil24.o
>  obj-$(CONFIG_SATA_DWC)		+= sata_dwc_460ex.o
>  obj-$(CONFIG_SATA_HIGHBANK)	+= sata_highbank.o libahci.o
> +obj-$(CONFIG_SATA_IMX)		+= sata_imx.o
>  
>  # SFF w/ custom DMA
>  obj-$(CONFIG_PDC_ADMA)		+= pdc_adma.o
> diff --git a/drivers/ata/sata_imx.c b/drivers/ata/sata_imx.c
> new file mode 100644
> index 0000000..de6330e
> --- /dev/null
> +++ b/drivers/ata/sata_imx.c
> @@ -0,0 +1,233 @@
> +/*
> + * Freescale IMX AHCI SATA platform driver
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/ahci_platform.h>
> +#include <linux/of_device.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
> +#include "ahci.h"
> +
> +enum {
> +	HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
> +};
> +
> +struct imx_ahci_priv {
> +	struct platform_device *imx_ahci_pdev;
> +	struct clk *sata_ref_clk;
> +	struct regmap *gpr;
> +};
> +
> +/* imx6q ahci module initialization. */
> +static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
> +{
> +	int ret = 0;
> +	unsigned int rc;

The variable name is confusing. "rc" generally means return code.

> +	struct clk *ahb_clk;
> +	struct device *p_dev = dev->parent;
> +	struct imx_ahci_priv *imxpriv =  dev_get_drvdata(p_dev);

I would go dev_get_drvdata(dev->parent), since dev->parent is even more
readable than p_dev.

> +
> +	imxpriv->gpr =
> +		syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> +	if (IS_ERR(imxpriv->gpr)) {
> +		dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
> +		return PTR_ERR(imxpriv->gpr);
> +	}

Move it into imx_ahci_probe().

> +
> +	imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
> +	if (IS_ERR(imxpriv->sata_ref_clk)) {
> +		dev_err(dev, "can't get sata_ref clock.\n");
> +		return PTR_ERR(imxpriv->sata_ref_clk);
> +	}

Ditto

> +
> +	ret = clk_prepare_enable(imxpriv->sata_ref_clk);
> +	if (ret < 0) {
> +		dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
> +		return ret;
> +	}
> +
> +	/*
> +	 * set PHY Paremeters, two steps to configure the GPR13,
> +	 * one write for rest of parameters, mask of first write
> +	 * is 0x07fffffd, and the other one write for setting
> +	 * the mpll_clk_en.
> +	 */
> +	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
> +			| IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
> +			| IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
> +			| IMX6Q_GPR13_SATA_SPD_MODE_MASK
> +			| IMX6Q_GPR13_SATA_MPLL_SS_EN
> +			| IMX6Q_GPR13_SATA_TX_ATTEN_MASK
> +			| IMX6Q_GPR13_SATA_TX_BOOST_MASK
> +			| IMX6Q_GPR13_SATA_TX_LVL_MASK
> +			| IMX6Q_GPR13_SATA_TX_EDGE_RATE
> +			, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
> +			| IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
> +			| IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
> +			| IMX6Q_GPR13_SATA_SPD_MODE_3P0G
> +			| IMX6Q_GPR13_SATA_MPLL_SS_EN
> +			| IMX6Q_GPR13_SATA_TX_ATTEN_9_16
> +			| IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
> +			| IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
> +	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
> +			IMX6Q_GPR13_SATA_MPLL_CLK_EN);
> +	usleep_range(100, 200);
> +
> +	/*
> +	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
> +	 * and IP vendor specific register HOST_TIMER1MS.
> +	 *
> +	 * Configure CAP_SSS (support stagered spin up).
> +	 * Implement the port0.
> +	 * Get the ahb clock rate, and configure the TIMER1MS register.
> +	 */
> +	rc = readl(mmio + HOST_CAP);
> +	if (!(rc & HOST_CAP_SSS)) {
> +		rc |= HOST_CAP_SSS;
> +		writel(rc, mmio + HOST_CAP);
> +	}
> +	rc = readl(mmio + HOST_PORTS_IMPL);
> +	if (!(rc & 0x1)) {
> +		rc |= 0x1;
> +		writel(rc, mmio + HOST_PORTS_IMPL);
> +	}
> +
> +	ahb_clk = devm_clk_get(dev, "ahb");

If you need to get ahb clock, please specify it in your DTS node.  Right
now, you only have the following two clocks in the DTS.

	clocks = <&clks 154>, <&clks 187>;
	clock-names = "sata", "sata_ref";

You code happens to work because of the following call in clk-imx6q.c.

	clk_register_clkdev(clk[ahb], "ahb", NULL);

But you shouldn't reply on that.  With all users moved to looking up
clocks from device tree, we would remove it from clock driver.

Also, please have a clk pointer in imx_ahci_priv and call devm_clk_get()
in imx_ahci_probe().

> +	if (IS_ERR(ahb_clk)) {
> +		dev_err(dev, "no ahb clock.\n");
> +		clk_disable_unprepare(imxpriv->sata_ref_clk);
> +		devm_clk_put(dev, imxpriv->sata_ref_clk);
> +		return PTR_ERR(ahb_clk);
> +	}
> +	rc = clk_get_rate(ahb_clk) / 1000;
> +	writel(rc, mmio + HOST_TIMER1MS);
> +	devm_clk_put(dev, ahb_clk);
> +
> +	return 0;
> +}
> +
> +static void imx6q_sata_exit(struct device *dev)
> +{
> +	struct device *p_dev = dev->parent;
> +	struct imx_ahci_priv *imxpriv =  dev_get_drvdata(p_dev);

dev_get_drvdata(dev->parent);

> +
> +	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
> +			!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
> +	clk_disable_unprepare(imxpriv->sata_ref_clk);
> +}
> +
> +static struct ahci_platform_data imx6q_sata_pdata = {
> +	.init = imx6q_sata_init,
> +	.exit = imx6q_sata_exit,
> +};

Put a blank line here.

> +static const struct of_device_id imx_ahci_of_match[] = {
> +	{ .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
> +
> +static void imx_ahci_platform_release(struct device *dev)
> +{
> +	return;
> +}

Is this empty function mandatory?

> +
> +static int imx_ahci_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct resource *mem, *irq, res[2];
> +	const struct of_device_id *of_id;
> +	const struct ahci_platform_data *pdata = NULL;
> +	struct imx_ahci_priv *imxpriv;
> +	int ret;
> +
I would drop this blank line and move the following two line above
"int ret;".

> +	struct device *imx_dev;
> +	struct platform_device *imx_ahci_pdev;

These two variable names are confusing.  I would name them ahci_dev and
ahci_pdev, as they are all about generic "ahci" rather than imx specific
one.

> +
> +	imx_ahci_pdev = platform_device_alloc("ahci", -1);
> +	if (!imx_ahci_pdev)
> +		return -ENODEV;
> +
> +	imx_dev = &imx_ahci_pdev->dev;
> +	imx_dev->release = imx_ahci_platform_release;
> +	imx_dev->parent = dev;
> +
> +	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
> +	if (!imxpriv) {
> +		dev_err(dev, "can't alloc ahci_host_priv\n");
> +		return -ENOMEM;
> +	}
> +
> +	imxpriv->imx_ahci_pdev = imx_ahci_pdev;

So imx_ahci_pdev in imx_ahci_priv is also confusing.

> +	platform_set_drvdata(pdev, imxpriv);
> +
> +	of_id = of_match_device(imx_ahci_of_match, dev);
> +	if (of_id)
> +		pdata = of_id->data;
> +	else
> +		return -EINVAL;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
> +	if (!mem || !irq) {
> +		dev_err(dev, "no mmio/irq resource\n");
> +		return -EINVAL;
> +	}
> +
> +	res[0] = *mem;
> +	res[1] = *irq;
> +
> +	imx_dev->coherent_dma_mask = DMA_BIT_MASK(32);
> +	imx_dev->dma_mask = &imx_dev->coherent_dma_mask;
> +	imx_dev->of_node = dev->of_node;
> +
> +	platform_device_add_resources(imx_ahci_pdev, res, 2);
> +	platform_device_add_data(imx_ahci_pdev, pdata, sizeof(*pdata));
> +
> +	ret = platform_device_add(imx_ahci_pdev);
> +
> +	return ret;

Can just be return platform_device_add(imx_ahci_pdev);

Shawn

> +}
> +
> +static int imx_ahci_remove(struct platform_device *pdev)
> +{
> +	struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
> +	struct platform_device *imx_ahci_pdev = imxpriv->imx_ahci_pdev;
> +
> +	platform_device_unregister(imx_ahci_pdev);
> +	return 0;
> +}
> +
> +static struct platform_driver imx_ahci_driver = {
> +	.probe = imx_ahci_probe,
> +	.remove = imx_ahci_remove,
> +	.driver = {
> +		.name = "sata-imx",
> +		.owner = THIS_MODULE,
> +		.of_match_table = imx_ahci_of_match,
> +	},
> +};
> +module_platform_driver(imx_ahci_driver);
> +
> +MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
> +MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("sata:imx");
> -- 
> 1.7.5.4
> 

RE: [v5 3/3] sata: imx: add ahci sata support on imx platforms

[Zhu Richard-R65037]

Hi Shawn:
Thanks for your comments.

Best Regards
Richard Zhu


-----Original Message-----
From: Shawn Guo [mailto:shawn.guo@linaro.org] 
Sent: Friday, July 12, 2013 3:02 PM
To: Richard Zhu
Cc: linux-arm-kernel@lists.infradead.org; jgarzik@pobox.com; tj@kernel.org; rob.herring@calxeda.com; s.hauer@pengutronix.de; linux-ide@vger.kernel.org; Zhu Richard-R65037
Subject: Re: [v5 3/3] sata: imx: add ahci sata support on imx platforms

On Thu, Jul 11, 2013 at 05:10:31PM +0800, Richard Zhu wrote:
> From: Richard Zhu <r65037@freescale.com>
> 
> imx6q contains one Synopsys AHCI SATA controller, But it can't shares 
> ahci_platform driver with other controllers.
> Because there are some misalignments of the generic AHCI controller.
> The bits definitions of the HBA registers, the Vendor Specific 
> registers, the AHCI PHY clock and the AHCI signals adjustment 
> window(GPR13 Reg).
>  - CAP_SSS(bit20) of the HOST_CAP is writable, default  value is '0', 
> should be configured to be '1'
>  - bit0 (only one AHCI SATA port on imx6q) of the  HOST_PORTS_IMPL 
> should be set to be '1'.(default 0)
>  - One Vendor Specific register HOST_TIMER1MS(offset:0xe0)  should be 
> configured regarding to the frequency of AHB  bus clock.
>  - Configurations of the AHCI PHY clock, and the signal  parameters of 
> the GPR13
> 
> Setup its own ahci sata driver, contained the imx6q specific 
> initialized codes, re-use the generic ahci_platform drier, and

s/drier/driver
[Richard] One typo error, would be changed.

> keep the generic ahci_platform driver clean as much as possible.
> 
> Signed-off-by: Richard Zhu <r65037@freescale.com>
> ---
>  drivers/ata/Kconfig    |    9 ++
>  drivers/ata/Makefile   |    1 +
>  drivers/ata/sata_imx.c |  233 
> ++++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 243 insertions(+), 0 deletions(-)  create mode 
> 100644 drivers/ata/sata_imx.c
> 
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 
> a5a3ebc..275dc2c 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -97,6 +97,15 @@ config SATA_AHCI_PLATFORM
>  
>  	  If unsure, say N.
>  
> +config SATA_IMX
> +	tristate "Freescale i.MX AHCI SATA support"
> +	depends on SATA_AHCI_PLATFORM
> +	help
> +	  This option enables support for the Freescale i.MX SoC's
> +	  onboard AHCI SATA.
> +
> +	  If unsure, say N.
> +
>  config SATA_FSL
>  	tristate "Freescale 3.0Gbps SATA support"
>  	depends on FSL_SOC
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 
> c04d0fd..04b1c6c 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_SATA_INIC162X)	+= sata_inic162x.o
>  obj-$(CONFIG_SATA_SIL24)	+= sata_sil24.o
>  obj-$(CONFIG_SATA_DWC)		+= sata_dwc_460ex.o
>  obj-$(CONFIG_SATA_HIGHBANK)	+= sata_highbank.o libahci.o
> +obj-$(CONFIG_SATA_IMX)		+= sata_imx.o
>  
>  # SFF w/ custom DMA
>  obj-$(CONFIG_PDC_ADMA)		+= pdc_adma.o
> diff --git a/drivers/ata/sata_imx.c b/drivers/ata/sata_imx.c new file 
> mode 100644 index 0000000..de6330e
> --- /dev/null
> +++ b/drivers/ata/sata_imx.c
> @@ -0,0 +1,233 @@
> +/*
> + * Freescale IMX AHCI SATA platform driver
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * based on the AHCI SATA platform driver by Jeff Garzik and Anton 
> +Vorontsov
> + *
> + * This program is free software; you can redistribute it and/or 
> +modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but 
> +WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
> +or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 
> +License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License 
> +along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/ahci_platform.h>
> +#include <linux/of_device.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
> +#include "ahci.h"
> +
> +enum {
> +	HOST_TIMER1MS = 0xe0, /* Timer 1-ms */ };
> +
> +struct imx_ahci_priv {
> +	struct platform_device *imx_ahci_pdev;
> +	struct clk *sata_ref_clk;
> +	struct regmap *gpr;
> +};
> +
> +/* imx6q ahci module initialization. */ static int 
> +imx6q_sata_init(struct device *dev, void __iomem *mmio) {
> +	int ret = 0;
> +	unsigned int rc;

The variable name is confusing. "rc" generally means return code.
[Richard] Accepted. Would be changed.
> +	struct clk *ahb_clk;
> +	struct device *p_dev = dev->parent;
> +	struct imx_ahci_priv *imxpriv =  dev_get_drvdata(p_dev);

I would go dev_get_drvdata(dev->parent), since dev->parent is even more readable than p_dev.
[Richard] Accepted.

> +
> +	imxpriv->gpr =
> +		syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> +	if (IS_ERR(imxpriv->gpr)) {
> +		dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
> +		return PTR_ERR(imxpriv->gpr);
> +	}

Move it into imx_ahci_probe().
[Richard] The codes "> +		syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); " is imx6q specific.
I think it's better to place these codes in the imx6q_sata_init(). Otherwise, the probe maybe broken here, when imx53
sata use sata_imx driver in future.

> +
> +	imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
> +	if (IS_ERR(imxpriv->sata_ref_clk)) {
> +		dev_err(dev, "can't get sata_ref clock.\n");
> +		return PTR_ERR(imxpriv->sata_ref_clk);
> +	}

Ditto
[Richard] Accepted.

> +
> +	ret = clk_prepare_enable(imxpriv->sata_ref_clk);
> +	if (ret < 0) {
> +		dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
> +		return ret;
> +	}
> +
> +	/*
> +	 * set PHY Paremeters, two steps to configure the GPR13,
> +	 * one write for rest of parameters, mask of first write
> +	 * is 0x07fffffd, and the other one write for setting
> +	 * the mpll_clk_en.
> +	 */
> +	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
> +			| IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
> +			| IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
> +			| IMX6Q_GPR13_SATA_SPD_MODE_MASK
> +			| IMX6Q_GPR13_SATA_MPLL_SS_EN
> +			| IMX6Q_GPR13_SATA_TX_ATTEN_MASK
> +			| IMX6Q_GPR13_SATA_TX_BOOST_MASK
> +			| IMX6Q_GPR13_SATA_TX_LVL_MASK
> +			| IMX6Q_GPR13_SATA_TX_EDGE_RATE
> +			, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
> +			| IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
> +			| IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
> +			| IMX6Q_GPR13_SATA_SPD_MODE_3P0G
> +			| IMX6Q_GPR13_SATA_MPLL_SS_EN
> +			| IMX6Q_GPR13_SATA_TX_ATTEN_9_16
> +			| IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
> +			| IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
> +	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
> +			IMX6Q_GPR13_SATA_MPLL_CLK_EN);
> +	usleep_range(100, 200);
> +
> +	/*
> +	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
> +	 * and IP vendor specific register HOST_TIMER1MS.
> +	 *
> +	 * Configure CAP_SSS (support stagered spin up).
> +	 * Implement the port0.
> +	 * Get the ahb clock rate, and configure the TIMER1MS register.
> +	 */
> +	rc = readl(mmio + HOST_CAP);
> +	if (!(rc & HOST_CAP_SSS)) {
> +		rc |= HOST_CAP_SSS;
> +		writel(rc, mmio + HOST_CAP);
> +	}
> +	rc = readl(mmio + HOST_PORTS_IMPL);
> +	if (!(rc & 0x1)) {
> +		rc |= 0x1;
> +		writel(rc, mmio + HOST_PORTS_IMPL);
> +	}
> +
> +	ahb_clk = devm_clk_get(dev, "ahb");

If you need to get ahb clock, please specify it in your DTS node.  Right now, you only have the following two clocks in the DTS.

	clocks = <&clks 154>, <&clks 187>;
	clock-names = "sata", "sata_ref";

You code happens to work because of the following call in clk-imx6q.c.

	clk_register_clkdev(clk[ahb], "ahb", NULL);

But you shouldn't reply on that.  With all users moved to looking up clocks from device tree, we would remove it from clock driver.

Also, please have a clk pointer in imx_ahci_priv and call devm_clk_get() in imx_ahci_probe().
[Richard] Accepted. Would add "ahb" to sata related dts changes.

> +	if (IS_ERR(ahb_clk)) {
> +		dev_err(dev, "no ahb clock.\n");
> +		clk_disable_unprepare(imxpriv->sata_ref_clk);
> +		devm_clk_put(dev, imxpriv->sata_ref_clk);
> +		return PTR_ERR(ahb_clk);
> +	}
> +	rc = clk_get_rate(ahb_clk) / 1000;
> +	writel(rc, mmio + HOST_TIMER1MS);
> +	devm_clk_put(dev, ahb_clk);
> +
> +	return 0;
> +}
> +
> +static void imx6q_sata_exit(struct device *dev) {
> +	struct device *p_dev = dev->parent;
> +	struct imx_ahci_priv *imxpriv =  dev_get_drvdata(p_dev);

dev_get_drvdata(dev->parent);
[Richard] Accepted.

> +
> +	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
> +			!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
> +	clk_disable_unprepare(imxpriv->sata_ref_clk);
> +}
> +
> +static struct ahci_platform_data imx6q_sata_pdata = {
> +	.init = imx6q_sata_init,
> +	.exit = imx6q_sata_exit,
> +};

Put a blank line here.

> +static const struct of_device_id imx_ahci_of_match[] = {
> +	{ .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
> +
> +static void imx_ahci_platform_release(struct device *dev) {
> +	return;
> +}

Is this empty function mandatory?
[Richard] Introduce in the previous patch-set, It can be removed in the current version.

> +
> +static int imx_ahci_probe(struct platform_device *pdev) {
> +	struct device *dev = &pdev->dev;
> +	struct resource *mem, *irq, res[2];
> +	const struct of_device_id *of_id;
> +	const struct ahci_platform_data *pdata = NULL;
> +	struct imx_ahci_priv *imxpriv;
> +	int ret;
> +
I would drop this blank line and move the following two line above "int ret;".
[Richard] Accepted. 

> +	struct device *imx_dev;
> +	struct platform_device *imx_ahci_pdev;

These two variable names are confusing.  I would name them ahci_dev and ahci_pdev, as they are all about generic "ahci" rather than imx specific one.
[Richard] Accepted.

> +
> +	imx_ahci_pdev = platform_device_alloc("ahci", -1);
> +	if (!imx_ahci_pdev)
> +		return -ENODEV;
> +
> +	imx_dev = &imx_ahci_pdev->dev;
> +	imx_dev->release = imx_ahci_platform_release;
> +	imx_dev->parent = dev;
> +
> +	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
> +	if (!imxpriv) {
> +		dev_err(dev, "can't alloc ahci_host_priv\n");
> +		return -ENOMEM;
> +	}
> +
> +	imxpriv->imx_ahci_pdev = imx_ahci_pdev;

So imx_ahci_pdev in imx_ahci_priv is also confusing.
[Richard] imx_ahci_pdev would be replaced by ahci_pdev.

> +	platform_set_drvdata(pdev, imxpriv);
> +
> +	of_id = of_match_device(imx_ahci_of_match, dev);
> +	if (of_id)
> +		pdata = of_id->data;
> +	else
> +		return -EINVAL;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
> +	if (!mem || !irq) {
> +		dev_err(dev, "no mmio/irq resource\n");
> +		return -EINVAL;
> +	}
> +
> +	res[0] = *mem;
> +	res[1] = *irq;
> +
> +	imx_dev->coherent_dma_mask = DMA_BIT_MASK(32);
> +	imx_dev->dma_mask = &imx_dev->coherent_dma_mask;
> +	imx_dev->of_node = dev->of_node;
> +
> +	platform_device_add_resources(imx_ahci_pdev, res, 2);
> +	platform_device_add_data(imx_ahci_pdev, pdata, sizeof(*pdata));
> +
> +	ret = platform_device_add(imx_ahci_pdev);
> +
> +	return ret;

Can just be return platform_device_add(imx_ahci_pdev);
[Richard] Accepted.

Shawn

> +}
> +
> +static int imx_ahci_remove(struct platform_device *pdev) {
> +	struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
> +	struct platform_device *imx_ahci_pdev = imxpriv->imx_ahci_pdev;
> +
> +	platform_device_unregister(imx_ahci_pdev);
> +	return 0;
> +}
> +
> +static struct platform_driver imx_ahci_driver = {
> +	.probe = imx_ahci_probe,
> +	.remove = imx_ahci_remove,
> +	.driver = {
> +		.name = "sata-imx",
> +		.owner = THIS_MODULE,
> +		.of_match_table = imx_ahci_of_match,
> +	},
> +};
> +module_platform_driver(imx_ahci_driver);
> +
> +MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver"); 
> +MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>"); 
> +MODULE_LICENSE("GPL"); MODULE_ALIAS("sata:imx");
> --
> 1.7.5.4
>