[PATCH 0/2] Fix for storage corruption w/ AMD IOMMU on 64-bit DMA

[PATCH 0/2] Fix for storage corruption w/ AMD IOMMU on 64-bit DMA

[Mario Limonciello]

An issue has been reported by a number of people that corruption
was occurring on storage for desktop systems.  It's notably reported
on SATA, but the same issue also appears on NVME.

At a glance it looks like an IOMMU issue as turning off the IOMMU helps
the issue, but it's actually a problem that occurs specifically with any
IOVA addressed >58 bits.

This is because the BIOS on these systems is enabling a feature of the
root port called 'enhanced atomics' which repurposes those upper 5 bits
of address space.  That feature should only be enabled by the BIOS when
the partner device supports it, but it's instead needlessly enabled on a
number of root ports.

As some of these systems probably won't receive BIOS updates and there is
active reports of data corruption root caused to this add a quirk to
disable it on affected models, and also remove the quirk that was
introduced to work around this issue in drivers/ata.

Mario Limonciello (2):
  x86/PCI: Disable enhanced atomics on some AMD PCIe ports
  Revert "ata: ahci: force 32-bit DMA for JMicron JMB582/JMB585"

 arch/x86/pci/fixup.c | 93 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/ata/ahci.c   | 18 ---------
 2 files changed, 93 insertions(+), 18 deletions(-)

-- 
2.43.0

[PATCH 1/2] x86/PCI: Disable enhanced atomics on some AMD PCIe ports

[Mario Limonciello]

There have been multiple reports of data corruption that can occur
with 64-bit DMA when the IOMMU is enabled. This occurs due to some
BIOSes enabling enhanced atomic operations on PCIe ports.

When enhanced atomic operations are enabled on PCIe ports for some
models, data corruption occurs when the 32-bit IOVA space is exhausted.
The problem is reported on storage devices, but can affect any device
that uses 64 bit DMA.

Disable enhanced atomics using SMN for NBIO 7.7 and 7.11 based models.

Cc: david.laight.linux@gmail.com
Cc: John Smith <imjohnsmith4000@gmail.com>
Cc: Lennert Buytenhek <kernel@wantstofly.org>
Cc: Niklas Cassel <cassel@kernel.org>
Cc: Roland Waltersson <roland.waltersson@netinsight.net>
Reported-by: Mikael Etienne <mikael1022bzh@gmail.com>
Closes: https://lore.kernel.org/all/178789300872.392066.15963676631650361573@gmail.com/
Reported-by: Arthur Husband <artmoty@gmail.com>
Closes: https://lore.kernel.org/linux-ide/20260406222335.379935-1-artmoty@gmail.com/
Reported-by: Alvin Lim <alvinwylim@gmail.com>
Closes: https://lore.kernel.org/linux-ide/20260621100844.1224301-1-alvinwylim@gmail.com/
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
 arch/x86/pci/fixup.c | 93 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index b301c6c8df753..0857fd9365ec2 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -886,6 +886,99 @@ static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev)
 	}
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0);
+
+/*
+ * Enhanced atomic operations can cause corruption with 64-bit IOVA
+ * on these devices.
+ */
+#define RX_ENH_ATOMIC_EN		BIT(8)
+
+static const u32 nbio_7_7_pcie_smn_addrs[] = {
+	0x111401d0,
+	0x111411d0,
+	0x111421d0,
+	0x111431d0,
+	0x111441d0,
+	0x112401d0,
+	0x112411d0,
+	0x112421d0,
+	0x112431d0,
+	0x112441d0,
+	0x112451d0,
+	0x113401d0,
+	0x114401d0,
+};
+
+static const u32 nbio_7_11_pcie_smn_addrs[] = {
+	0x112401d0,
+	0x112411d0,
+	0x112421d0,
+	0x112431d0,
+	0x112441d0,
+	0x112451d0,
+	0x113401d0,
+	0x113411d0,
+	0x113421d0,
+	0x113431d0,
+	0x113441d0,
+	0x113451d0,
+};
+
+static void quirk_amd_nbio_enhanced_atomic(struct pci_dev *host_bridge,
+					   const u32 *smn_addrs,
+					   size_t nr_smn_addrs)
+{
+	bool changed = false;
+	size_t i;
+	u32 data;
+	int ret;
+
+	for (i = 0; i < nr_smn_addrs; i++) {
+		ret = amd_smn_read(0, smn_addrs[i], &data);
+		if (ret)
+			continue;
+		if (!(data & RX_ENH_ATOMIC_EN))
+			continue;
+		data = data & ~RX_ENH_ATOMIC_EN;
+		ret = amd_smn_write(0, smn_addrs[i], data);
+		if (ret)
+			continue;
+		if (changed)
+			continue;
+		ret = amd_smn_read(0, smn_addrs[i], &data);
+		if (ret)
+			continue;
+		if (data & RX_ENH_ATOMIC_EN)
+			continue;
+		changed = true;
+	}
+
+	if (changed)
+		pci_info(host_bridge, "enhanced atomics disabled\n");
+}
+
+static void quirk_amd_nbio_7_7_disable_enhanced_atomic(struct pci_dev *dev)
+{
+	quirk_amd_nbio_enhanced_atomic(dev, nbio_7_7_pcie_smn_addrs,
+				       ARRAY_SIZE(nbio_7_7_pcie_smn_addrs));
+}
+
+static void quirk_amd_nbio_7_11_disable_enhanced_atomic(struct pci_dev *dev)
+{
+	quirk_amd_nbio_enhanced_atomic(dev, nbio_7_11_pcie_smn_addrs,
+				       ARRAY_SIZE(nbio_7_11_pcie_smn_addrs));
+}
+
+/* Phoenix, Hawk Point (NBIO 7.7) */
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x14E8,
+			quirk_amd_nbio_7_7_disable_enhanced_atomic);
+
+/* Strix, Krackan, Strix Halo (NBIO 7.11) */
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1507,
+			quirk_amd_nbio_7_11_disable_enhanced_atomic);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1122,
+			quirk_amd_nbio_7_11_disable_enhanced_atomic);
+
 #endif
 
 /*
-- 
2.43.0

Re: [PATCH 1/2] x86/PCI: Disable enhanced atomics on some AMD PCIe ports

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Critical] Hardware state loss across suspend/resume causing data corruption
--

commit 6c1c185449d3f44e1db8d42c0f5b1f2a64c2eeb8
Author: Mario Limonciello <mario.limonciello@amd.com>

x86/PCI: Disable enhanced atomics on some AMD PCIe ports

This commit disables enhanced atomic operations on PCIe ports for AMD
NBIO 7.7 and 7.11 based models to prevent data corruption with 64-bit DMA.
The issue occurs when the 32-bit IOVA space is exhausted on certain BIOSes.

Closes: https://lore.kernel.org/all/178789300872.392066.15963676631650361573@gmail.com/
Closes: https://lore.kernel.org/linux-ide/20260406222335.379935-1-artmoty@gmail.com/
Closes: https://lore.kernel.org/linux-ide/20260621100844.1224301-1-alvinwylim@gmail.com/

> diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
> index b301c6c8df753..0857fd9365ec2 100644
> --- a/arch/x86/pci/fixup.c
> +++ b/arch/x86/pci/fixup.c

[ ... ]

> +/* Phoenix, Hawk Point (NBIO 7.7) */
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x14E8,
> +			quirk_amd_nbio_7_7_disable_enhanced_atomic);
> +
> +/* Strix, Krackan, Strix Halo (NBIO 7.11) */
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1507,
> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1122,
> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);

[Severity: Critical]
Is this fixup lost across suspend and resume cycles?

Because the quirk is only registered for the final boot phase using
DECLARE_PCI_FIXUP_FINAL, the PCI core will not re-apply it during system
wake (which relies on DECLARE_PCI_FIXUP_RESUME).

If the system suspends to S3 or s2idle, the NBIO power domain is gated and
SMN registers lose their state. When the system resumes, the firmware
re-initializes these SMN registers to their default state (which has
enhanced atomics enabled). 

Because the kernel does not re-apply the quirk on resume, any subsequent
64-bit DMA traffic after waking from sleep could trigger the data
corruption this code is intended to prevent. 

Should these quirks also be registered with DECLARE_PCI_FIXUP_RESUME?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260908170035.160166-1-mario.limonciello@amd.com?part=1

Re: [PATCH 1/2] x86/PCI: Disable enhanced atomics on some AMD PCIe ports

[Mario Limonciello]

On 9/8/26 12:14, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Critical] Hardware state loss across suspend/resume causing data corruption
> --
> 
> commit 6c1c185449d3f44e1db8d42c0f5b1f2a64c2eeb8
> Author: Mario Limonciello <mario.limonciello@amd.com>
> 
> x86/PCI: Disable enhanced atomics on some AMD PCIe ports
> 
> This commit disables enhanced atomic operations on PCIe ports for AMD
> NBIO 7.7 and 7.11 based models to prevent data corruption with 64-bit DMA.
> The issue occurs when the 32-bit IOVA space is exhausted on certain BIOSes.
> 
> Closes: https://lore.kernel.org/all/178789300872.392066.15963676631650361573@gmail.com/
> Closes: https://lore.kernel.org/linux-ide/20260406222335.379935-1-artmoty@gmail.com/
> Closes: https://lore.kernel.org/linux-ide/20260621100844.1224301-1-alvinwylim@gmail.com/
> 
>> diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
>> index b301c6c8df753..0857fd9365ec2 100644
>> --- a/arch/x86/pci/fixup.c
>> +++ b/arch/x86/pci/fixup.c
> 
> [ ... ]
> 
>> +/* Phoenix, Hawk Point (NBIO 7.7) */
>> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x14E8,
>> +			quirk_amd_nbio_7_7_disable_enhanced_atomic);
>> +
>> +/* Strix, Krackan, Strix Halo (NBIO 7.11) */
>> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1507,
>> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);
>> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1122,
>> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);
> 
> [Severity: Critical]
> Is this fixup lost across suspend and resume cycles?
> 
> Because the quirk is only registered for the final boot phase using
> DECLARE_PCI_FIXUP_FINAL, the PCI core will not re-apply it during system
> wake (which relies on DECLARE_PCI_FIXUP_RESUME).
> 
> If the system suspends to S3 or s2idle, the NBIO power domain is gated and
> SMN registers lose their state. When the system resumes, the firmware
> re-initializes these SMN registers to their default state (which has
> enhanced atomics enabled).
> 
> Because the kernel does not re-apply the quirk on resume, any subsequent
> 64-bit DMA traffic after waking from sleep could trigger the data
> corruption this code is intended to prevent.
> 
> Should these quirks also be registered with DECLARE_PCI_FIXUP_RESUME?
> 

This looks like valid feedback.  I checked and these registers don't 
surive suspend/resume.  I'll modify it for a v2.

Re: [PATCH 1/2] x86/PCI: Disable enhanced atomics on some AMD PCIe ports

[Bjorn Helgaas]

On Tue, Sep 08, 2026 at 12:00:34PM -0500, Mario Limonciello wrote:
> There have been multiple reports of data corruption that can occur
> with 64-bit DMA when the IOMMU is enabled. This occurs due to some
> BIOSes enabling enhanced atomic operations on PCIe ports.
> 
> When enhanced atomic operations are enabled on PCIe ports for some
> models, data corruption occurs when the 32-bit IOVA space is exhausted.
> The problem is reported on storage devices, but can affect any device
> that uses 64 bit DMA.

I assume this means there's an erratum where NBIO doesn't handle
64-bit DMA correctly when some AMD-specific "enhanced atomics" are
enabled?

Nothing to do with the atomic operations defined by the PCI specs?

> Disable enhanced atomics using SMN for NBIO 7.7 and 7.11 based models.
> 
> Cc: david.laight.linux@gmail.com
> Cc: John Smith <imjohnsmith4000@gmail.com>
> Cc: Lennert Buytenhek <kernel@wantstofly.org>
> Cc: Niklas Cassel <cassel@kernel.org>
> Cc: Roland Waltersson <roland.waltersson@netinsight.net>
> Reported-by: Mikael Etienne <mikael1022bzh@gmail.com>
> Closes: https://lore.kernel.org/all/178789300872.392066.15963676631650361573@gmail.com/
> Reported-by: Arthur Husband <artmoty@gmail.com>
> Closes: https://lore.kernel.org/linux-ide/20260406222335.379935-1-artmoty@gmail.com/
> Reported-by: Alvin Lim <alvinwylim@gmail.com>
> Closes: https://lore.kernel.org/linux-ide/20260621100844.1224301-1-alvinwylim@gmail.com/
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
>  arch/x86/pci/fixup.c | 93 ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 93 insertions(+)
> 
> diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
> index b301c6c8df753..0857fd9365ec2 100644
> --- a/arch/x86/pci/fixup.c
> +++ b/arch/x86/pci/fixup.c
> @@ -886,6 +886,99 @@ static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev)
>  	}
>  }
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0);
> +
> +/*
> + * Enhanced atomic operations can cause corruption with 64-bit IOVA
> + * on these devices.
> + */
> +#define RX_ENH_ATOMIC_EN		BIT(8)
> +
> +static const u32 nbio_7_7_pcie_smn_addrs[] = {
> +	0x111401d0,
> +	0x111411d0,
> +	0x111421d0,
> +	0x111431d0,
> +	0x111441d0,
> +	0x112401d0,
> +	0x112411d0,
> +	0x112421d0,
> +	0x112431d0,
> +	0x112441d0,
> +	0x112451d0,
> +	0x113401d0,
> +	0x114401d0,
> +};
> +
> +static const u32 nbio_7_11_pcie_smn_addrs[] = {
> +	0x112401d0,
> +	0x112411d0,
> +	0x112421d0,
> +	0x112431d0,
> +	0x112441d0,
> +	0x112451d0,
> +	0x113401d0,
> +	0x113411d0,
> +	0x113421d0,
> +	0x113431d0,
> +	0x113441d0,
> +	0x113451d0,
> +};
> +
> +static void quirk_amd_nbio_enhanced_atomic(struct pci_dev *host_bridge,
> +					   const u32 *smn_addrs,
> +					   size_t nr_smn_addrs)
> +{
> +	bool changed = false;
> +	size_t i;
> +	u32 data;
> +	int ret;
> +
> +	for (i = 0; i < nr_smn_addrs; i++) {
> +		ret = amd_smn_read(0, smn_addrs[i], &data);
> +		if (ret)
> +			continue;
> +		if (!(data & RX_ENH_ATOMIC_EN))
> +			continue;
> +		data = data & ~RX_ENH_ATOMIC_EN;
> +		ret = amd_smn_write(0, smn_addrs[i], data);
> +		if (ret)
> +			continue;
> +		if (changed)
> +			continue;
> +		ret = amd_smn_read(0, smn_addrs[i], &data);
> +		if (ret)
> +			continue;
> +		if (data & RX_ENH_ATOMIC_EN)
> +			continue;
> +		changed = true;
> +	}
> +
> +	if (changed)
> +		pci_info(host_bridge, "enhanced atomics disabled\n");
> +}
> +
> +static void quirk_amd_nbio_7_7_disable_enhanced_atomic(struct pci_dev *dev)
> +{
> +	quirk_amd_nbio_enhanced_atomic(dev, nbio_7_7_pcie_smn_addrs,
> +				       ARRAY_SIZE(nbio_7_7_pcie_smn_addrs));
> +}
> +
> +static void quirk_amd_nbio_7_11_disable_enhanced_atomic(struct pci_dev *dev)
> +{
> +	quirk_amd_nbio_enhanced_atomic(dev, nbio_7_11_pcie_smn_addrs,
> +				       ARRAY_SIZE(nbio_7_11_pcie_smn_addrs));
> +}
> +
> +/* Phoenix, Hawk Point (NBIO 7.7) */
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x14E8,
> +			quirk_amd_nbio_7_7_disable_enhanced_atomic);
> +
> +/* Strix, Krackan, Strix Halo (NBIO 7.11) */
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1507,
> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1122,
> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);
> +
>  #endif
>  
>  /*
> -- 
> 2.43.0
> 

Re: [PATCH 1/2] x86/PCI: Disable enhanced atomics on some AMD PCIe ports

[Mario Limonciello]

On 9/8/26 14:18, Bjorn Helgaas wrote:
> On Tue, Sep 08, 2026 at 12:00:34PM -0500, Mario Limonciello wrote:
>> There have been multiple reports of data corruption that can occur
>> with 64-bit DMA when the IOMMU is enabled. This occurs due to some
>> BIOSes enabling enhanced atomic operations on PCIe ports.
>>
>> When enhanced atomic operations are enabled on PCIe ports for some
>> models, data corruption occurs when the 32-bit IOVA space is exhausted.
>> The problem is reported on storage devices, but can affect any device
>> that uses 64 bit DMA.
> 
> I assume this means there's an erratum where NBIO doesn't handle
> 64-bit DMA correctly when some AMD-specific "enhanced atomics" are
> enabled?
> 
> Nothing to do with the atomic operations defined by the PCI specs?

Correct; nothing to do with atomic operations in PCI spec.

Note: I did post a v2 as Sashiko found a (valid) problem that this 
policy fixup needs to be applied during resume as well.

> 
>> Disable enhanced atomics using SMN for NBIO 7.7 and 7.11 based models.
>>
>> Cc: david.laight.linux@gmail.com
>> Cc: John Smith <imjohnsmith4000@gmail.com>
>> Cc: Lennert Buytenhek <kernel@wantstofly.org>
>> Cc: Niklas Cassel <cassel@kernel.org>
>> Cc: Roland Waltersson <roland.waltersson@netinsight.net>
>> Reported-by: Mikael Etienne <mikael1022bzh@gmail.com>
>> Closes: https://lore.kernel.org/all/178789300872.392066.15963676631650361573@gmail.com/
>> Reported-by: Arthur Husband <artmoty@gmail.com>
>> Closes: https://lore.kernel.org/linux-ide/20260406222335.379935-1-artmoty@gmail.com/
>> Reported-by: Alvin Lim <alvinwylim@gmail.com>
>> Closes: https://lore.kernel.org/linux-ide/20260621100844.1224301-1-alvinwylim@gmail.com/
>> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
>> ---
>>   arch/x86/pci/fixup.c | 93 ++++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 93 insertions(+)
>>
>> diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
>> index b301c6c8df753..0857fd9365ec2 100644
>> --- a/arch/x86/pci/fixup.c
>> +++ b/arch/x86/pci/fixup.c
>> @@ -886,6 +886,99 @@ static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev)
>>   	}
>>   }
>>   DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0);
>> +
>> +/*
>> + * Enhanced atomic operations can cause corruption with 64-bit IOVA
>> + * on these devices.
>> + */
>> +#define RX_ENH_ATOMIC_EN		BIT(8)
>> +
>> +static const u32 nbio_7_7_pcie_smn_addrs[] = {
>> +	0x111401d0,
>> +	0x111411d0,
>> +	0x111421d0,
>> +	0x111431d0,
>> +	0x111441d0,
>> +	0x112401d0,
>> +	0x112411d0,
>> +	0x112421d0,
>> +	0x112431d0,
>> +	0x112441d0,
>> +	0x112451d0,
>> +	0x113401d0,
>> +	0x114401d0,
>> +};
>> +
>> +static const u32 nbio_7_11_pcie_smn_addrs[] = {
>> +	0x112401d0,
>> +	0x112411d0,
>> +	0x112421d0,
>> +	0x112431d0,
>> +	0x112441d0,
>> +	0x112451d0,
>> +	0x113401d0,
>> +	0x113411d0,
>> +	0x113421d0,
>> +	0x113431d0,
>> +	0x113441d0,
>> +	0x113451d0,
>> +};
>> +
>> +static void quirk_amd_nbio_enhanced_atomic(struct pci_dev *host_bridge,
>> +					   const u32 *smn_addrs,
>> +					   size_t nr_smn_addrs)
>> +{
>> +	bool changed = false;
>> +	size_t i;
>> +	u32 data;
>> +	int ret;
>> +
>> +	for (i = 0; i < nr_smn_addrs; i++) {
>> +		ret = amd_smn_read(0, smn_addrs[i], &data);
>> +		if (ret)
>> +			continue;
>> +		if (!(data & RX_ENH_ATOMIC_EN))
>> +			continue;
>> +		data = data & ~RX_ENH_ATOMIC_EN;
>> +		ret = amd_smn_write(0, smn_addrs[i], data);
>> +		if (ret)
>> +			continue;
>> +		if (changed)
>> +			continue;
>> +		ret = amd_smn_read(0, smn_addrs[i], &data);
>> +		if (ret)
>> +			continue;
>> +		if (data & RX_ENH_ATOMIC_EN)
>> +			continue;
>> +		changed = true;
>> +	}
>> +
>> +	if (changed)
>> +		pci_info(host_bridge, "enhanced atomics disabled\n");
>> +}
>> +
>> +static void quirk_amd_nbio_7_7_disable_enhanced_atomic(struct pci_dev *dev)
>> +{
>> +	quirk_amd_nbio_enhanced_atomic(dev, nbio_7_7_pcie_smn_addrs,
>> +				       ARRAY_SIZE(nbio_7_7_pcie_smn_addrs));
>> +}
>> +
>> +static void quirk_amd_nbio_7_11_disable_enhanced_atomic(struct pci_dev *dev)
>> +{
>> +	quirk_amd_nbio_enhanced_atomic(dev, nbio_7_11_pcie_smn_addrs,
>> +				       ARRAY_SIZE(nbio_7_11_pcie_smn_addrs));
>> +}
>> +
>> +/* Phoenix, Hawk Point (NBIO 7.7) */
>> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x14E8,
>> +			quirk_amd_nbio_7_7_disable_enhanced_atomic);
>> +
>> +/* Strix, Krackan, Strix Halo (NBIO 7.11) */
>> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1507,
>> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);
>> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1122,
>> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);
>> +
>>   #endif
>>   
>>   /*
>> -- 
>> 2.43.0
>>

[PATCH 2/2] Revert "ata: ahci: force 32-bit DMA for JMicron JMB582/JMB585"

[Mario Limonciello]

This reverts commit 105c42566a550e2d05fc14f763216a8765ee5d0e.

The issue is actually a problem with BIOS configuaration of PCIe
root ports, enabling a feature that causes problems with 64-bit
DMA.  It is fixed by adjusting the kernel adjusting the
configuration of those root ports.

Cc: Arthur Husband <artmoty@gmail.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
 drivers/ata/ahci.c | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 9b8c0935001cb..bffe50a109b88 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -68,7 +68,6 @@ enum board_ids {
 	/* board IDs for specific chipsets in alphabetical order */
 	board_ahci_al,
 	board_ahci_avn,
-	board_ahci_jmb585,
 	board_ahci_mcp65,
 	board_ahci_mcp77,
 	board_ahci_mcp89,
@@ -213,15 +212,6 @@ static const struct ata_port_info ahci_port_info[] = {
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_avn_ops,
 	},
-	/* JMicron JMB582/585: 64-bit DMA is broken, force 32-bit */
-	[board_ahci_jmb585] = {
-		AHCI_HFLAGS	(AHCI_HFLAG_IGN_IRQ_IF_ERR |
-				 AHCI_HFLAG_32BIT_ONLY),
-		.flags		= AHCI_FLAG_COMMON,
-		.pio_mask	= ATA_PIO4,
-		.udma_mask	= ATA_UDMA6,
-		.port_ops	= &ahci_ops,
-	},
 	[board_ahci_mcp65] = {
 		AHCI_HFLAGS	(AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
 				 AHCI_HFLAG_YES_NCQ),
@@ -954,14 +944,6 @@ static const struct pci_device_id ahci_pci_tbl[] = {
 		/* Elkhart Lake AHCI */
 		PCI_VDEVICE(INTEL, 0x4b63),
 		.driver_data = board_ahci_pcs_quirk,
-	}, {
-		/* JMicron JMB582/585: force 32-bit DMA (broken 64-bit implementation) */
-		PCI_VDEVICE(JMICRON, 0x0582),
-		.driver_data = board_ahci_jmb585,
-
-	}, {
-		PCI_VDEVICE(JMICRON, 0x0585),
-		.driver_data = board_ahci_jmb585,
 	}, {
 		/* JMicron 360/1/3/5/6, match class to avoid IDE function */
 		PCI_DEVICE(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID),
-- 
2.43.0

Re: [PATCH 2/2] Revert "ata: ahci: force 32-bit DMA for JMicron JMB582/JMB585"

[sashiko-bot]

> This reverts commit 105c42566a550e2d05fc14f763216a8765ee5d0e.
> 
> The issue is actually a problem with BIOS configuaration of PCIe
> root ports, enabling a feature that causes problems with 64-bit
> DMA.  It is fixed by adjusting the kernel adjusting the
> configuration of those root ports.
> 
> Cc: Arthur Husband <artmoty@gmail.com>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260908170035.160166-1-mario.limonciello@amd.com?part=2