[PATCH v2 00/53] MIPS: SGI-IP27: add support for the IP35 (Bedrock hub) machines

[PATCH v2 00/53] MIPS: SGI-IP27: add support for the IP35 (Bedrock hub) machines

[Imre Kaloz]

This series adds support for the SGI machines built around the Bedrock
hub (IP35), such as Fuel and Tezro, to the IP27 platform code.

Patches 1-5 fix the config space accessors and slot setup of the
Bridge, XBridge and PIC driver: device numbers past the last slot,
slots the PROM leaves unconfigured, the type 1 IOC3 write, posted
config writes and slots whose devio window the PROM maps elsewhere.

Patches 6-22 teach the IP27 code the Bedrock hub: detection, the node
address layout and register windows, the node id, CPU slots, memory
banks, both PIs and the kernel load address.

Patches 23-32 add the crossbar, bridge and I/O parts of these machines:
PXBow, XBridge, PIC and IOC4.

Patches 33-44 add the L1 system controller and what it provides, the
Origin 300 IO8 serial interrupts, the Odyssey graphics widget, the
KLCONFIG console and a topology package id per CPU.

Patches 45-47 add a libata driver for the IOC4 ATA/ATAPI controller,
which carries the DVD-ROM of Tezro and Origin 350 I-bricks. It drives
PIO4 and multiword DMA mode 2.

Patch 48 updates ip27_defconfig to the onboard hardware of these
machines, dropping add-in card drivers and enabling USB and PS/2
input. Patch 49 enables the IOC4 ATA driver in it.

Patches 50-53 add a driver for the Fuel and Tezro front-panel LEDs,
which the L1 sets, as white:status and red:fault. The red LED blinks
on panic, and a Tezro shows the OS state on its L1 display.

The series applies on top of "[PATCH v2] MIPS: SGI-IP27: print the NMI
dump on an nbcon console", which the NMI dump needs to reach the 8250
console.

Tested on SGI Fuel and Tezro, the Fuel with an LSI 53C1030 and an NVMe
drive behind a PCI-X-to-PCIe bridge in slots the PROM leaves
unconfigured, on a 4GB Tezro with an LSI SAS1064 on a PCI-X bus, and
for patch 5 also on an Octane. Patches 50-53 were tested on a Tezro
only, and patch 48 was only built.

On IP27 (Hub) machines:
- patch 22 moves the kernel up by 144KB, and the 144KB below it stays
  reserved and unused;
- with patch 26 SWIOTLB takes 64MB of node 0 on a multi-node Origin,
  and ZONE_DMA32 spans the first 2GB;
- the XBridge and PIC DMA address forms (patch 26) and the w1 change
  (patch 39) do nothing on a Hub with classic Bridges;
- patches 1-5 change the config space handling of its Bridges as well.

Given I have no IP27 boxes, none of this was booted on one.
ip27_defconfig builds at every patch, ip30_defconfig at every patch
that changes code it builds.

An XBridge or PIC on a Bedrock hub takes its board setup from the
first board part number the L1 reports that the setup table knows
(patch 35), so on a machine with several bricks every such bridge gets
that one board's setup.

Patch 42 registers the Odyssey graphics widget as the "sgi-odyssey"
platform device used by the Odyssey DRM driver, a separate series, and
passes it the master widget id as the "sgi,master-widget" property.

checkpatch reports "spaces required around that ':'" in patches 14 and
21 for the GAS numeric local labels 1: and 2: in assembler macros.

Changes in v2:
- New patches 1-5 (Bridge config space and slot fixes), 37 (Origin
  300 IO8 serial interrupts), 45-47 and 49 (IOC4 ATA/ATAPI), 48
  (ip27_defconfig update) and 50-53 (front-panel LEDs).
- Patch 15 (was 10): slot 0 takes master_nasid as its node, not 0.
- Patch 24 (was 19): also enables the SGI 1-wire master and the DS250x
  slave the Bridge probe waits for.
- Patch 25 (was 20): comment and message name the IOC3 on the 32-bit
  window behind an XBridge or PIC.
- Patch 26 (was 21), retitled (Christoph Hellwig): an XBridge or PIC
  device with a 64-bit DMA mask uses the 64-bit direct form with bit 55
  set, other devices the 32-bit window with SWIOTLB and ZONE_DMA32; a
  PIC bus in PCI-X mode uses the direct form only; the IOC3 and IOC4
  always use the window, with byte swapping off; an IOC3 or IOC4 MFD
  cell maps through its PCI parent.
- Patch 29 (was 24): the PIC slot count goes through bridge_nslots()
  from patch 1.
- Patch 30 (was 25): probe fails without a platform device id.
- Patch 31 (was 26): probe fails on a PCI id without variant data;
  const mfd_cell array; MAINTAINERS covers sgi-ioc3-serial.h; the IOC4
  register layout includes the ATA/ATAPI block; the IOC4 firmware
  revision is printed, and the serial ports need revision 62 or later;
  the PCI id is PCI_DEVICE_ID_SGI_IOC4, which patch 26 adds.
- Patch 36 (was 31): const mfd_cell array.
- Patch 38 (was 32): the random fallback address is set with
  eth_hw_addr_random().
- Patch 42 (was 36): passes the "sgi,master-widget" property.
- Patch 43 (was 37): the PROM's console baud rate is printed unsigned,
  so 38400 does not come out negative.
- mfd subjects capitalised; rebased onto v7.3-rc7 and the NMI v2 patch.
- v1: https://lore.kernel.org/all/cover.1790857966.git.kaloz@kernel.org/

Imre Kaloz (53):
  MIPS: PCI: xtalk-bridge: refuse device numbers past the last slot
  MIPS: PCI: xtalk-bridge: assign slots the PROM leaves unconfigured
  MIPS: PCI: xtalk-bridge: write a type 1 IOC3 through the type 1 window
  MIPS: PCI: xtalk-bridge: flush config space writes
  MIPS: PCI: xtalk-bridge: reassign slots whose devio window maps
    elsewhere
  MIPS: Xtalk: guard the widget identification table from assembly
  MIPS: SGI-IP27: dump the NMI save areas the CPU scan recorded
  MIPS: SGI-IP27: add REMOTE_HUB_PI_S()/REMOTE_HUB_PI_L()
  MIPS: SGI-IP27: detect Bedrock hubs at boot
  MIPS: SGI-IP27: widen Kconfig for the Bedrock-based machines
  MIPS: SGI-IP27: fold the dead SN1 arm out of klconfig.h
  MIPS: SGI-IP27: choose the node address layout at runtime
  MIPS: SGI-IP27: add the Bedrock hub register windows
  MIPS: SGI-IP27: decode a Bedrock hub's node id and system size
  MIPS: SGI-IP27: put a Bedrock hub's boot CPU in slot 0
  MIPS: SGI-IP27: lay out node memory in 1GB banks on Bedrock hubs
  MIPS: SGI-IP27: reserve the bottom 64MB of node 0 on Bedrock hubs
  MIPS: SGI-IP27: route interrupt masks and slices through both PIs
  MIPS: SGI-IP27: address a CPU's own PI for NMI, IPI and RT counter
  MIPS: SGI-IP27: take a CPU's node from the CPU table in per_cpu_init()
  MIPS: SGI-IP27: resolve the mapped-kernel node shift at runtime
  MIPS: SGI-IP27: load the kernel at node offset 0x40000
  MIPS: SGI-IP27: xbow_probe(): recognize KLTYPE_PBRICK_XBOW
  MIPS: ip27_defconfig: enable the IOC3 MFD, its cell drivers and tg3
  net: ethernet: sgi: ioc3-eth: apply the DMA attributes only to 64-bit
    addresses
  MIPS: SGI-IP27: pick the XBridge and PIC DMA address form by mask
  MIPS: SGI-IP27: recognize the PXBow crossbar
  MIPS: PCI: xtalk-bridge: recognize the PIC widget's 64-bit-only
    registers
  MIPS: PCI: xtalk-bridge: match PIC's register-level differences
  rtc: m48t35: support the SGI IP35 timekeeper's 1968 year base
  mfd: ioc3: Add support for IOC4
  MIPS: SGI-IP27: dispatch the early console between IOC3 and IOC4
  MIPS: SGI-IP27: add L1 system controller support
  MIPS: SGI-IP27: wire the L1 into reset and the Ethernet address
  MIPS: PCI: xtalk-bridge: take the board part number from the L1
  mfd: ioc3: Add IP34 system-board entry to ioc3_infos[]
  mfd: ioc3: Cross the serial IRQs on the Origin 300 IO8
  net: ethernet: sgi: ioc3-eth: fall back to the platform MAC address
  MIPS: SGI-IP27: don't register a w1 master on an XBridge or PIC
  MIPS: SGI-IP27: report a Bedrock machine as SGI IP35
  MIPS: SGI-IP27: identify the machine by the L1 brick type
  MIPS: SGI-IP27: register the Odyssey graphics widget
  MIPS: SGI-IP27: take the console from the KLCONFIG header on IP35
  MIPS: SGI-IP27: give each CPU its own topology package id
  ata: add pata_sgiioc4 driver for the SGI IOC4 ATA/ATAPI controller
  mfd: ioc3: Add IOC4 ATA/ATAPI cell
  MAINTAINERS: add an entry for the SGI IOC4 ATA driver
  MIPS: ip27_defconfig: update for the onboard hardware
  MIPS: ip27_defconfig: enable pata_sgiioc4 and the DVD-ROM path
  MIPS: SGI-IP27: add L1 front-panel LED and display requests
  leds: Add driver for the SGI Fuel and Tezro front-panel LEDs
  MIPS: SGI-IP27: show the OS state on the Fuel and Tezro front panels
  MIPS: ip27_defconfig: enable the Fuel and Tezro front-panel LEDs

 MAINTAINERS                                   |   7 +
 arch/mips/Kconfig                             |  13 +-
 arch/mips/configs/ip27_defconfig              | 192 +---
 .../include/asm/mach-ip27/kernel-entry-init.h |  33 +-
 arch/mips/include/asm/pci/bridge.h            |  88 +-
 arch/mips/include/asm/sn/addrs.h              |  39 +-
 arch/mips/include/asm/sn/agent.h              |   5 +-
 arch/mips/include/asm/sn/arch.h               |   8 +
 arch/mips/include/asm/sn/intr.h               |  14 +-
 arch/mips/include/asm/sn/ioc4.h               | 143 +++
 arch/mips/include/asm/sn/klconfig.h           |  19 +-
 arch/mips/include/asm/sn/kldir.h              |   1 +
 arch/mips/include/asm/sn/l1.h                 |  38 +
 arch/mips/include/asm/sn/mapped_kernel.h      |   6 +-
 arch/mips/include/asm/sn/sn0/addrs.h          |   8 +-
 arch/mips/include/asm/sn/sn0/hub.h            |  37 +-
 arch/mips/include/asm/sn/sn0/hubni.h          |   3 +
 arch/mips/include/asm/sn/sn1/addrs.h          |  22 +
 arch/mips/include/asm/sn/sn1/hub.h            |  40 +
 arch/mips/include/asm/sn/sn1/kldir.h          |  14 +
 arch/mips/include/asm/xtalk/xwidget.h         |  11 +-
 arch/mips/pci/pci-xtalk-bridge.c              | 467 ++++++++-
 arch/mips/sgi-ip27/Makefile                   |   4 +-
 arch/mips/sgi-ip27/Platform                   |  11 +-
 arch/mips/sgi-ip27/ip27-berr.c                |   4 +-
 arch/mips/sgi-ip27/ip27-console.c             |  47 +-
 arch/mips/sgi-ip27/ip27-init.c                | 178 +++-
 arch/mips/sgi-ip27/ip27-irq.c                 |  17 +-
 arch/mips/sgi-ip27/ip27-l1.c                  | 884 ++++++++++++++++++
 arch/mips/sgi-ip27/ip27-memory.c              |  55 +-
 arch/mips/sgi-ip27/ip27-nmi.c                 |  54 +-
 arch/mips/sgi-ip27/ip27-reset.c               |  47 +-
 arch/mips/sgi-ip27/ip27-smp.c                 |  41 +-
 arch/mips/sgi-ip27/ip27-timer.c               |  12 +-
 arch/mips/sgi-ip27/ip27-xtalk.c               | 138 ++-
 drivers/ata/Kconfig                           |  10 +
 drivers/ata/Makefile                          |   1 +
 drivers/ata/pata_sgiioc4.c                    | 311 ++++++
 drivers/leds/Kconfig                          |  12 +
 drivers/leds/Makefile                         |   1 +
 drivers/leds/leds-ip35.c                      | 144 +++
 drivers/mfd/ioc3.c                            | 455 ++++++++-
 drivers/net/ethernet/sgi/ioc3-eth.c           |  44 +-
 drivers/rtc/rtc-m48t35.c                      |  33 +-
 drivers/tty/serial/8250/8250_ioc3.c           |   5 +-
 include/linux/pci_ids.h                       |   1 +
 include/linux/platform_data/sgi-ioc3-serial.h |  13 +
 include/linux/platform_data/xtalk-bridge.h    |   2 +
 48 files changed, 3334 insertions(+), 398 deletions(-)
 create mode 100644 arch/mips/include/asm/sn/ioc4.h
 create mode 100644 arch/mips/include/asm/sn/l1.h
 create mode 100644 arch/mips/include/asm/sn/sn1/addrs.h
 create mode 100644 arch/mips/include/asm/sn/sn1/hub.h
 create mode 100644 arch/mips/include/asm/sn/sn1/kldir.h
 create mode 100644 arch/mips/sgi-ip27/ip27-l1.c
 create mode 100644 drivers/ata/pata_sgiioc4.c
 create mode 100644 drivers/leds/leds-ip35.c
 create mode 100644 include/linux/platform_data/sgi-ioc3-serial.h


base-commit: 24a19b953e2a3d0ea5a8c4951a0ab8f32720c907
prerequisite-patch-id: 642054c4c189f29a3f589a119d2311c20e395a23
-- 
2.47.3

[PATCH v2 45/53] ata: add pata_sgiioc4 driver for the SGI IOC4 ATA/ATAPI controller

[Imre Kaloz]

The IOC4 on Origin 350-class I-brick boards drives the DVD-ROM from an
ATA/ATAPI controller at BAR0+0x100. drivers/ide/sgiioc4.c went away in
v5.4.

Add a libata driver bound to an IOC4 MFD cell, with PIO4 and multiword
DMA mode 2. Each taskfile register sits at the lowest address of its
own 32-bit slot; the IDE driver's "+3" byte-lane correction reads
zeros there.

Signed-off-by: Imre Kaloz <kaloz@kernel.org>
---
 drivers/ata/Kconfig        |  10 ++
 drivers/ata/Makefile       |   1 +
 drivers/ata/pata_sgiioc4.c | 311 +++++++++++++++++++++++++++++++++++++
 3 files changed, 322 insertions(+)
 create mode 100644 drivers/ata/pata_sgiioc4.c

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 28ca856ecc75..704414501f35 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -940,6 +940,16 @@ config PATA_SERVERWORKS
 
 	  If unsure, say N.
 
+config PATA_SGIIOC4
+	tristate "SGI IOC4 ATA/ATAPI support"
+	depends on SGI_MFD_IOC3
+	help
+	  This option enables support for the ATA/ATAPI controller
+	  integrated into SGI's IOC4 I/O ASIC, found on Tezro/Origin
+	  350-class I-brick system boards.
+
+	  If unsure, say N.
+
 config PATA_SIL680
 	tristate "CMD / Silicon Image 680 PATA support"
 	depends on PCI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index b96025abd45e..f2947a2b86be 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -89,6 +89,7 @@ obj-$(CONFIG_PATA_RDC)		+= pata_rdc.o
 obj-$(CONFIG_PATA_SC1200)	+= pata_sc1200.o
 obj-$(CONFIG_PATA_SCH)		+= pata_sch.o
 obj-$(CONFIG_PATA_SERVERWORKS)	+= pata_serverworks.o
+obj-$(CONFIG_PATA_SGIIOC4)	+= pata_sgiioc4.o
 obj-$(CONFIG_PATA_SIL680)	+= pata_sil680.o
 obj-$(CONFIG_PATA_SIS)		+= pata_sis.o
 obj-$(CONFIG_PATA_TOSHIBA)	+= pata_piccolo.o
diff --git a/drivers/ata/pata_sgiioc4.c b/drivers/ata/pata_sgiioc4.c
new file mode 100644
index 000000000000..454c43c6b6c7
--- /dev/null
+++ b/drivers/ata/pata_sgiioc4.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * libata driver for the ATA/ATAPI controller in SGI's IOC4 I/O ASIC.
+ *
+ * Copyright (C) 1999-2004 Silicon Graphics, Inc.
+ * Copyright (C) 2026 Imre Kaloz <kaloz@kernel.org>
+ */
+#include <linux/ata.h>
+#include <linux/dma-mapping.h>
+#include <linux/iopoll.h>
+#include <linux/libata.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/sizes.h>
+#include <linux/string.h>
+
+#include <asm/sn/ioc4.h>
+
+#define DRV_NAME	"pata_sgiioc4"
+
+#define IOC4_ATA_CTRL_OFFSET	offsetof(struct ioc4_ata_regs, ctrl)
+
+/* The ATA controller needs IOC4 firmware revision 46 or later. */
+#define IOC4_ATA_MIN_REV	46
+
+/* DMA engine registers, as offsets into the ATA block */
+#define IOC4_DMA_REG(n)		offsetof(struct ioc4_ata_regs, dma[n])
+#define IOC4_DMA_PTR_L		IOC4_DMA_REG(1)	/* descriptor list */
+#define IOC4_DMA_PTR_H		IOC4_DMA_REG(2)
+#define IOC4_DMA_ADDR_L		IOC4_DMA_REG(3)	/* current memory address */
+#define IOC4_DMA_ADDR_H		IOC4_DMA_REG(4)
+#define IOC4_DMA_BC_DEV		IOC4_DMA_REG(5)
+#define IOC4_DMA_BC_MEM		IOC4_DMA_REG(6)
+#define IOC4_DMA_CTRL		IOC4_DMA_REG(7)
+#define IOC4_DMA_END		IOC4_DMA_REG(8)	/* completion area */
+
+#define IOC4_DMA_START		BIT(0)
+#define IOC4_DMA_STOP		BIT(1)	/* reads 1 until the engine stops */
+#define IOC4_DMA_TO_MEM		BIT(2)
+#define IOC4_DMA_ACTIVE		BIT(3)
+#define IOC4_DMA_MEMERR		BIT(4)
+
+#define IOC4_DMA_STOP_TIMEOUT_US	200
+
+/* Descriptors are big-endian; the last one has bit 31 set in its count. */
+struct ioc4_ata_prd {
+	__be64	addr;
+	__be64	count;
+};
+
+#define IOC4_PRD_EOL		0x80000000
+#define IOC4_PRD_ENTRIES	ATA_MAX_PRD
+#define IOC4_PRD_SIZE		(IOC4_PRD_ENTRIES * sizeof(struct ioc4_ata_prd))
+
+/*
+ * The count field holds at most 0xfffe bytes, so a whole 64 KiB segment
+ * does not fit one descriptor. Splitting at 32 KiB boundaries keeps
+ * libata's segments within two descriptors each.
+ */
+#define IOC4_PRD_CHUNK		SZ_32K
+
+/*
+ * After the last data of a transfer the engine writes nonzero bytes into
+ * a 128-byte, 128-byte aligned area. Register reads are not ordered
+ * against its data writes, so the data is valid only once this area
+ * changes.
+ */
+#define IOC4_DMAEND_SIZE	128
+#define IOC4_DMAEND_TIMEOUT_US	1000
+
+struct ioc4_ata_port {
+	struct ioc4_ata_prd	*prd;
+	void			*dmaend;
+	dma_addr_t		prd_dma;
+	dma_addr_t		dmaend_dma;
+	u32			dir;
+};
+
+static void ioc4_ata_dma_halt(struct ata_port *ap)
+{
+	void __iomem *base = ap->ioaddr.cmd_addr;
+	u32 val;
+
+	writel(IOC4_DMA_STOP, base + IOC4_DMA_CTRL);
+	if (readl_poll_timeout_atomic(base + IOC4_DMA_CTRL, val,
+				      !(val & IOC4_DMA_STOP), 1,
+				      IOC4_DMA_STOP_TIMEOUT_US))
+		ata_port_warn(ap, "DMA engine did not stop\n");
+}
+
+static enum ata_completion_errors ioc4_ata_qc_prep(struct ata_queued_cmd *qc)
+{
+	struct ioc4_ata_port *pp = qc->ap->private_data;
+	struct scatterlist *sg;
+	unsigned int si, pi = 0;
+
+	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
+		return AC_ERR_OK;
+
+	for_each_sg(qc->sg, sg, qc->n_elem, si) {
+		dma_addr_t addr = sg_dma_address(sg);
+		u32 sg_len = sg_dma_len(sg);
+
+		while (sg_len) {
+			u32 len = min_t(u32, sg_len, IOC4_PRD_CHUNK -
+					(addr & (IOC4_PRD_CHUNK - 1)));
+
+			pp->prd[pi].addr = cpu_to_be64(addr);
+			pp->prd[pi].count = cpu_to_be64(len);
+			pi++;
+			addr += len;
+			sg_len -= len;
+		}
+	}
+	pp->prd[pi - 1].count |= cpu_to_be64(IOC4_PRD_EOL);
+
+	return AC_ERR_OK;
+}
+
+static void ioc4_ata_bmdma_setup(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+	struct ioc4_ata_port *pp = ap->private_data;
+	void __iomem *base = ap->ioaddr.cmd_addr;
+
+	/* A failed transfer can leave the engine running or an error latched. */
+	if (readl(base + IOC4_DMA_CTRL) & (IOC4_DMA_ACTIVE | IOC4_DMA_MEMERR))
+		ioc4_ata_dma_halt(ap);
+
+	writel(lower_32_bits(pp->prd_dma), base + IOC4_DMA_PTR_L);
+	writel(upper_32_bits(pp->prd_dma), base + IOC4_DMA_PTR_H);
+
+	memset(pp->dmaend, 0, IOC4_DMAEND_SIZE);
+	writel(lower_32_bits(pp->dmaend_dma), base + IOC4_DMA_END);
+
+	pp->dir = qc->tf.flags & ATA_TFLAG_WRITE ? 0 : IOC4_DMA_TO_MEM;
+
+	ap->ops->sff_exec_command(ap, &qc->tf);
+}
+
+static void ioc4_ata_bmdma_start(struct ata_queued_cmd *qc)
+{
+	struct ata_port *ap = qc->ap;
+	struct ioc4_ata_port *pp = ap->private_data;
+
+	writel(pp->dir | IOC4_DMA_START, ap->ioaddr.cmd_addr + IOC4_DMA_CTRL);
+}
+
+static void ioc4_ata_bmdma_stop(struct ata_queued_cmd *qc)
+{
+	ioc4_ata_dma_halt(qc->ap);
+}
+
+/*
+ * The engine raises no completion interrupt; the port interrupt is
+ * the drive's. Once the drive has finished without error, wait for the
+ * completion area before the data is handed back.
+ */
+static u8 ioc4_ata_bmdma_status(struct ata_port *ap)
+{
+	struct ioc4_ata_port *pp = ap->private_data;
+	u32 ctrl = readl(ap->ioaddr.cmd_addr + IOC4_DMA_CTRL);
+	u8 status = ATA_DMA_INTR;
+	void *seen;
+
+	if (ctrl & IOC4_DMA_ACTIVE)
+		status |= ATA_DMA_ACTIVE;
+
+	if (ctrl & IOC4_DMA_MEMERR)
+		return status | ATA_DMA_ERR;
+
+	if (ioread8(ap->ioaddr.altstatus_addr) & (ATA_BUSY | ATA_DRQ | ATA_ERR))
+		return status;
+
+	if (read_poll_timeout_atomic(memchr_inv, seen, seen, 1,
+				     IOC4_DMAEND_TIMEOUT_US, false,
+				     pp->dmaend, 0, IOC4_DMAEND_SIZE))
+		return status | ATA_DMA_ERR;
+	dma_rmb();
+
+	return status;
+}
+
+static int ioc4_ata_port_start(struct ata_port *ap)
+{
+	struct device *dev = ap->host->dev;
+	struct ioc4_ata_port *pp;
+
+	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
+	if (!pp)
+		return -ENOMEM;
+
+	/* The page-aligned list leaves the completion area 128-byte aligned. */
+	pp->prd = dmam_alloc_coherent(dev, IOC4_PRD_SIZE + IOC4_DMAEND_SIZE,
+				      &pp->prd_dma, GFP_KERNEL);
+	if (!pp->prd)
+		return -ENOMEM;
+
+	pp->dmaend = (void *)pp->prd + IOC4_PRD_SIZE;
+	pp->dmaend_dma = pp->prd_dma + IOC4_PRD_SIZE;
+	ap->private_data = pp;
+
+	return 0;
+}
+
+static struct ata_port_operations ioc4_ata_port_ops = {
+	.inherits		= &ata_bmdma_port_ops,
+
+	.cable_detect		= ata_cable_40wire,
+
+	/* No .set_piomode: what the ATA timing register does is unknown. */
+
+	.qc_prep		= ioc4_ata_qc_prep,
+	.bmdma_setup		= ioc4_ata_bmdma_setup,
+	.bmdma_start		= ioc4_ata_bmdma_start,
+	.bmdma_stop		= ioc4_ata_bmdma_stop,
+	.bmdma_status		= ioc4_ata_bmdma_status,
+	.port_start		= ioc4_ata_port_start,
+};
+
+static const struct scsi_host_template ioc4_ata_sht = {
+	ATA_BMDMA_SHT(DRV_NAME),
+};
+
+static int ioc4_ata_probe(struct platform_device *pdev)
+{
+	struct ata_port_info pinfo = {
+		.flags		= ATA_FLAG_SLAVE_POSS,
+		.pio_mask	= ATA_PIO4,
+		.mwdma_mask	= ATA_MWDMA2_ONLY,
+		.port_ops	= &ioc4_ata_port_ops,
+	};
+	const struct ata_port_info *ppi[] = { &pinfo, NULL };
+	struct pci_dev *pci_parent;
+	struct ata_host *host;
+	struct ata_port *ap;
+	struct resource *res;
+	void __iomem *base;
+	int irq, ret;
+
+	if (!dev_is_pci(pdev->dev.parent))
+		return -EINVAL;
+	pci_parent = to_pci_dev(pdev->dev.parent);
+
+	if (pci_parent->revision < IOC4_ATA_MIN_REV) {
+		dev_err(&pdev->dev,
+			"IOC4 firmware revision %u is not supported, %u or later is required\n",
+			pci_parent->revision, IOC4_ATA_MIN_REV);
+		return -ENODEV;
+	}
+
+	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+
+	/*
+	 * The cell inherits its parent's 64-bit DMA mask, but the engine
+	 * takes 32-bit bus addresses only.
+	 */
+	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+	if (ret)
+		return ret;
+
+	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
+	if (!host)
+		return -ENOMEM;
+
+	ap = host->ports[0];
+
+	/*
+	 * Each taskfile register has a 32-bit slot of its own and sits at the
+	 * slot's lowest address, with no byte-lane correction.
+	 */
+	ap->ioaddr.cmd_addr	 = base;
+	ap->ioaddr.data_addr	 = base + (ATA_REG_DATA << 2);
+	ap->ioaddr.error_addr	 = base + (ATA_REG_ERR << 2);
+	ap->ioaddr.feature_addr	 = ap->ioaddr.error_addr;
+	ap->ioaddr.nsect_addr	 = base + (ATA_REG_NSECT << 2);
+	ap->ioaddr.lbal_addr	 = base + (ATA_REG_LBAL << 2);
+	ap->ioaddr.lbam_addr	 = base + (ATA_REG_LBAM << 2);
+	ap->ioaddr.lbah_addr	 = base + (ATA_REG_LBAH << 2);
+	ap->ioaddr.device_addr	 = base + (ATA_REG_DEVICE << 2);
+	ap->ioaddr.status_addr	 = base + (ATA_REG_STATUS << 2);
+	ap->ioaddr.command_addr	 = ap->ioaddr.status_addr;
+	ap->ioaddr.altstatus_addr = base + IOC4_ATA_CTRL_OFFSET;
+	ap->ioaddr.ctl_addr	 = ap->ioaddr.altstatus_addr;
+
+	ata_port_desc(ap, "cmd 0x%llx", (unsigned long long)res->start);
+
+	return ata_host_activate(host, irq, ata_bmdma_interrupt, IRQF_SHARED,
+				  &ioc4_ata_sht);
+}
+
+static struct platform_driver ioc4_ata_driver = {
+	.probe	= ioc4_ata_probe,
+	.remove	= ata_platform_remove_one,
+	.driver	= {
+		.name	= DRV_NAME,
+	},
+};
+module_platform_driver(ioc4_ata_driver);
+
+MODULE_AUTHOR("Imre Kaloz <kaloz@kernel.org>");
+MODULE_DESCRIPTION("SGI IOC4 ATA/ATAPI libata driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);
-- 
2.47.3

[PATCH v2 47/53] MAINTAINERS: add an entry for the SGI IOC4 ATA driver

[Imre Kaloz]

Add an entry for drivers/ata/pata_sgiioc4.c, the libata driver for the
IOC4 ATA/ATAPI controller.

Signed-off-by: Imre Kaloz <kaloz@kernel.org>
---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a30c09a55c72..826f0ffb71fd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24925,6 +24925,12 @@ F:	include/linux/phylink.h
 F:	include/linux/sfp.h
 K:	phylink\.h|struct\s+phylink|\.phylink|>phylink_|phylink_(autoneg|clear|connect|create|destroy|disconnect|ethtool|helper|mac|mii|of|set|start|stop|test|validate)
 
+SGI IOC4 ATA DRIVER
+M:	Imre Kaloz <kaloz@kernel.org>
+L:	linux-ide@vger.kernel.org
+S:	Maintained
+F:	drivers/ata/pata_sgiioc4.c
+
 SHARED MEMORY COMMUNICATIONS (SMC) SOCKETS
 M:	D. Wythe <alibuda@linux.alibaba.com>
 M:	Dust Li <dust.li@linux.alibaba.com>
-- 
2.47.3

Re: [PATCH v2 47/53] MAINTAINERS: add an entry for the SGI IOC4 ATA driver

[Damien Le Moal]

On 2026/10/13 15:17, Imre Kaloz wrote:
> Add an entry for drivers/ata/pata_sgiioc4.c, the libata driver for the
> IOC4 ATA/ATAPI controller.
> 
> Signed-off-by: Imre Kaloz <kaloz@kernel.org>
> ---
>  MAINTAINERS | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a30c09a55c72..826f0ffb71fd 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -24925,6 +24925,12 @@ F:	include/linux/phylink.h
>  F:	include/linux/sfp.h
>  K:	phylink\.h|struct\s+phylink|\.phylink|>phylink_|phylink_(autoneg|clear|connect|create|destroy|disconnect|ethtool|helper|mac|mii|of|set|start|stop|test|validate)
>  
> +SGI IOC4 ATA DRIVER
> +M:	Imre Kaloz <kaloz@kernel.org>
> +L:	linux-ide@vger.kernel.org
> +S:	Maintained
> +F:	drivers/ata/pata_sgiioc4.c
> +
>  SHARED MEMORY COMMUNICATIONS (SMC) SOCKETS
>  M:	D. Wythe <alibuda@linux.alibaba.com>
>  M:	Dust Li <dust.li@linux.alibaba.com>

Please squash this into patch 45.

Also, the cover letter mentions that patch 45-47 are for libata but I did not
receive patch 46. I only received the cover letter, and patches 45 and 47.

Are you planning to get all of this merged through the mips tree?

-- 
Damien Le Moal
Western Digital Research

Re: [PATCH v2 00/53] MIPS: SGI-IP27: add support for the IP35 (Bedrock hub) machines

[Niklas Cassel]

Hello Imre,

This series is rather large.

I would recommend you to submit a minimal patch series
to get the basic support for your new board, such that
it can boot with a ramdisk and serial console.

Then in the next cycle, send separate series for ata,
net, leds, mfc, rtc, etc.


Kind regards,
Niklas

Re: [PATCH v2 47/53] MAINTAINERS: add an entry for the SGI IOC4 ATA driver

[Imre Kaloz]

[-- Attachment #1: Type: text/plain, Size: 1841 bytes --]

Hi Damien,

On Tue, 13 Oct 2026, Damien Le Moal wrote:

> On 2026/10/13 15:17, Imre Kaloz wrote:
>> Add an entry for drivers/ata/pata_sgiioc4.c, the libata driver for the
>> IOC4 ATA/ATAPI controller.
>>
>> Signed-off-by: Imre Kaloz <kaloz@kernel.org>
>> ---
>>  MAINTAINERS | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index a30c09a55c72..826f0ffb71fd 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -24925,6 +24925,12 @@ F:	include/linux/phylink.h
>>  F:	include/linux/sfp.h
>>  K:	phylink\.h|struct\s+phylink|\.phylink|>phylink_|phylink_(autoneg|clear|connect|create|destroy|disconnect|ethtool|helper|mac|mii|of|set|start|stop|test|validate)
>>
>> +SGI IOC4 ATA DRIVER
>> +M:	Imre Kaloz <kaloz@kernel.org>
>> +L:	linux-ide@vger.kernel.org
>> +S:	Maintained
>> +F:	drivers/ata/pata_sgiioc4.c
>> +
>>  SHARED MEMORY COMMUNICATIONS (SMC) SOCKETS
>>  M:	D. Wythe <alibuda@linux.alibaba.com>
>>  M:	Dust Li <dust.li@linux.alibaba.com>
>
> Please squash this into patch 45.
>
> Also, the cover letter mentions that patch 45-47 are for libata but I did not
> receive patch 46. I only received the cover letter, and patches 45 and 47.
>
> Are you planning to get all of this merged through the mips tree?

Will squash 47 into 45 in v3.

Sorry about 46: it only touches drivers/mfd/ioc3.c and 
arch/mips/include/asm/sn/ioc4.h, so get_maintainer left linux-ide off it. 
It adds the IOC4 ATA/ATAPI MFD cell that pata_sgiioc4 binds to:
https://lore.kernel.org/all/754bae380c938b63eeaa87e3dccf9755314675ed.1791890466.git.kaloz@kernel.org/
v3 will copy you and linux-ide on it.

As for merging: pata_sgiioc4 depends on the IOC4 support added earlier in 
the series (asm/sn/ioc4.h and the MFD cell), so I’d like it to go through 
the MIPS tree with your ack, if that works for you.


Best,
Imre

Re: [PATCH v2 00/53] MIPS: SGI-IP27: add support for the IP35 (Bedrock hub) machines

[Imre Kaloz]

[-- Attachment #1: Type: text/plain, Size: 1013 bytes --]

Hello Niklas,

On Tue, 13 Oct 2026, Niklas Cassel wrote:

> Hello Imre,
>
> This series is rather large.
>
> I would recommend you to submit a minimal patch series
> to get the basic support for your new board, such that
> it can boot with a ramdisk and serial console.
>
> Then in the next cycle, send separate series for ata,
> net, leds, mfc, rtc, etc.

Hi Niklas,

Thanks for having a look. I checked what the minimum is: 31 of the 53 
patches (1, 6-24, 26-29, 31-36 and 39) boot a Tezro to a ramdisk with a 
serial console. Two mfd/ioc3 patches have to be part of that, as they 
provide the console UARTs (31 for IOC4 on the Tezro, 36 for the IOC3 on 
the Fuel). The rest separates cleanly into follow-ups: the remaining 
Bridge fixes (2-5), ioc3-eth (25, 38), rtc (30), the IO8 serial IRQs (37), 
machine identification and the Odyssey widget (40-44), ata (45-47, 49), 
the defconfig refresh (48) and the LEDs (50-53).

I’ll wait for Thomas to say whether he prefers it split that way for v3.


Thanks,
Imre

Re: [PATCH v2 47/53] MAINTAINERS: add an entry for the SGI IOC4 ATA driver

[Damien Le Moal]

On 2026/10/13 15:38, Imre Kaloz wrote:
> As for merging: pata_sgiioc4 depends on the IOC4 support added earlier in 
> the series (asm/sn/ioc4.h and the MFD cell), so I’d like it to go through 
> the MIPS tree with your ack, if that works for you.

OK for me to have this go through the mips tree.


-- 
Damien Le Moal
Western Digital Research