* [PATCH v3 2/2] dt-bindings: ata: add DT bindings for MediaTek SATA controller
From: Ryder Lee @ 2017-08-12 1:31 UTC (permalink / raw)
To: Hans de Goede, Tejun Heo, Rob Herring
Cc: devicetree, linux-mediatek, linux-kernel, linux-ide, Long Cheng,
Ryder Lee
In-Reply-To: <cover.1502501342.git.ryder.lee@mediatek.com>
Add DT bindings for the onboard SATA controller present on the MediaTek
SoCs.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
Documentation/devicetree/bindings/ata/ahci-mtk.txt | 51 ++++++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
diff --git a/Documentation/devicetree/bindings/ata/ahci-mtk.txt b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
new file mode 100644
index 0000000..96c8d22
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
@@ -0,0 +1,51 @@
+MediaTek Serial ATA controller
+
+Required properties:
+ - compatible : Must be "mediatek,soc-model-ahci", "mediatek,mtk-ahci".
+ When using "mediatek,mtk-ahci" compatible strings, you
+ need SoC specific ones in addition, one of:
+ - "mediatek,mt7622-ahci"
+ - reg : Physical base addresses and length of register sets.
+ - interrupts : Interrupt associated with the SATA device.
+ - interrupt-names : Associated name must be: "hostc".
+ - clocks : A list of phandle and clock specifier pairs, one for each
+ entry in clock-names.
+ - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
+ - phys : A phandle and PHY specifier pair for the PHY port.
+ - phy-names : Associated name must be: "sata-phy".
+ - ports-implemented : See ./ahci-platform.txt for details.
+
+Optional properties:
+ - power-domains : A phandle and power domain specifier pair to the power
+ domain which is responsible for collapsing and restoring
+ power to the peripheral.
+ - resets : Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names : Associated names must be: "axi", "sw", "reg".
+ - mediatek,phy-mode : A phandle to the system controller, used to enable
+ SATA function.
+
+Example:
+
+ sata: sata@1a200000 {
+ compatible = "mediatek,mt7622-ahci",
+ "mediatek,mtk-ahci";
+ reg = <0 0x1a200000 0 0x1100>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ clocks = <&pciesys CLK_SATA_AHB_EN>,
+ <&pciesys CLK_SATA_AXI_EN>,
+ <&pciesys CLK_SATA_ASIC_EN>,
+ <&pciesys CLK_SATA_RBC_EN>,
+ <&pciesys CLK_SATA_PM_EN>;
+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
+ phys = <&u3port1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi", "sw", "reg";
+ mediatek,phy-mode = <&pciesys>;
+ };
--
1.9.1
^ permalink raw reply related
* [PATCH v3 1/2] ata: mediatek: add support for MediaTek SATA controller
From: Ryder Lee @ 2017-08-12 1:31 UTC (permalink / raw)
To: Hans de Goede, Tejun Heo, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-ide-u79uwXL29TY76Z2rM5mHXA, Long Cheng, Ryder Lee
In-Reply-To: <cover.1502501342.git.ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
This adds support the AHCI-compliant Serial ATA controller present
on MediaTek SoCs.
Signed-off-by: Ryder Lee <ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/ata/Kconfig | 10 +++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 207 insertions(+)
create mode 100644 drivers/ata/ahci_mtk.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 363fc53..488c937 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -153,6 +153,16 @@ config AHCI_CEVA
If unsure, say N.
+config AHCI_MTK
+ tristate "MediaTek AHCI SATA support"
+ depends on ARCH_MEDIATEK
+ select MFD_SYSCON
+ help
+ This option enables support for the MediaTek SoC's
+ onboard AHCI SATA controller.
+
+ If unsure, say N.
+
config AHCI_MVEBU
tristate "Marvell EBU AHCI SATA support"
depends on ARCH_MVEBU
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index a26ef5a..ff9cd2e 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DM816) += ahci_dm816.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_MTK) += ahci_mtk.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_OCTEON) += ahci_octeon.o
obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c
new file mode 100644
index 0000000..80854f7
--- /dev/null
+++ b/drivers/ata/ahci_mtk.c
@@ -0,0 +1,196 @@
+/*
+ * MeidaTek AHCI SATA driver
+ *
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/ahci_platform.h>
+#include <linux/kernel.h>
+#include <linux/libata.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include "ahci.h"
+
+#define DRV_NAME "ahci"
+
+#define SYS_CFG 0x14
+#define SYS_CFG_SATA_MSK GENMASK(31, 30)
+#define SYS_CFG_SATA_EN BIT(31)
+
+struct mtk_ahci_plat {
+ struct regmap *mode;
+ struct reset_control *axi_rst;
+ struct reset_control *sw_rst;
+ struct reset_control *reg_rst;
+};
+
+static const struct ata_port_info ahci_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &ahci_platform_ops,
+};
+
+static struct scsi_host_template ahci_platform_sht = {
+ AHCI_SHT(DRV_NAME),
+};
+
+static int mtk_ahci_platform_resets(struct ahci_host_priv *hpriv,
+ struct device *dev)
+{
+ struct mtk_ahci_plat *plat = hpriv->plat_data;
+ int err;
+
+ /* reset AXI bus and PHY part */
+ plat->axi_rst = devm_reset_control_get_optional_exclusive(dev, "axi");
+ if (PTR_ERR(plat->axi_rst) == -EPROBE_DEFER)
+ return PTR_ERR(plat->axi_rst);
+
+ plat->sw_rst = devm_reset_control_get_optional_exclusive(dev, "sw");
+ if (PTR_ERR(plat->sw_rst) == -EPROBE_DEFER)
+ return PTR_ERR(plat->sw_rst);
+
+ plat->reg_rst = devm_reset_control_get_optional_exclusive(dev, "reg");
+ if (PTR_ERR(plat->reg_rst) == -EPROBE_DEFER)
+ return PTR_ERR(plat->reg_rst);
+
+ err = reset_control_assert(plat->axi_rst);
+ if (err) {
+ dev_err(dev, "failed to assert AXI bus\n");
+ return err;
+ }
+
+ err = reset_control_assert(plat->sw_rst);
+ if (err) {
+ dev_err(dev, "failed to assert PHY digital part\n");
+ return err;
+ }
+
+ err = reset_control_assert(plat->reg_rst);
+ if (err) {
+ dev_err(dev, "failed to assert PHY register part\n");
+ return err;
+ }
+
+ err = reset_control_deassert(plat->reg_rst);
+ if (err) {
+ dev_err(dev, "failed to deassert PHY register part\n");
+ return err;
+ }
+
+ err = reset_control_deassert(plat->sw_rst);
+ if (err) {
+ dev_err(dev, "failed to deassert PHY digital part\n");
+ return err;
+ }
+
+ err = reset_control_deassert(plat->axi_rst);
+ if (err) {
+ dev_err(dev, "failed to deassert AXI bus\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv,
+ struct device *dev)
+{
+ struct mtk_ahci_plat *plat = hpriv->plat_data;
+ struct device_node *np = dev->of_node;
+
+ /* enable SATA function if needed */
+ if (of_find_property(np, "mediatek,phy-mode", NULL)) {
+ plat->mode = syscon_regmap_lookup_by_phandle(
+ np, "mediatek,phy-mode");
+ if (IS_ERR(plat->mode)) {
+ dev_err(dev, "missing phy-mode phandle\n");
+ return PTR_ERR(plat->mode);
+ }
+
+ regmap_update_bits(plat->mode, SYS_CFG, SYS_CFG_SATA_MSK,
+ SYS_CFG_SATA_EN);
+ }
+
+ of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map);
+
+ return 0;
+}
+
+static int mtk_ahci_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ahci_plat *plat;
+ struct ahci_host_priv *hpriv;
+ int err;
+
+ plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);
+ if (!plat)
+ return -ENOMEM;
+
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ hpriv->plat_data = plat;
+
+ err = mtk_ahci_parse_property(hpriv, dev);
+ if (err)
+ return err;
+
+ err = mtk_ahci_platform_resets(hpriv, dev);
+ if (err)
+ return err;
+
+ err = ahci_platform_enable_resources(hpriv);
+ if (err)
+ return err;
+
+ err = ahci_platform_init_host(pdev, hpriv, &ahci_port_info,
+ &ahci_platform_sht);
+ if (err)
+ goto disable_resources;
+
+ return 0;
+
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+ return err;
+}
+
+static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
+ ahci_platform_resume);
+
+static const struct of_device_id ahci_of_match[] = {
+ { .compatible = "mediatek,mtk-ahci", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ahci_of_match);
+
+static struct platform_driver mtk_ahci_driver = {
+ .probe = mtk_ahci_probe,
+ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = ahci_of_match,
+ .pm = &ahci_pm_ops,
+ },
+};
+module_platform_driver(mtk_ahci_driver);
+
+MODULE_DESCRIPTION("MeidaTek SATA AHCI Driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v3 0/2] Add support for MediaTek AHCI SATA
From: Ryder Lee @ 2017-08-12 1:31 UTC (permalink / raw)
To: Hans de Goede, Tejun Heo, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-ide-u79uwXL29TY76Z2rM5mHXA, Long Cheng, Ryder Lee
Hi,
This patch series add support for AHCI compatible SATA controller, and it is
compliant with the ahci 1.3 and sata 3.0 specification. This driver is slightly
different than ahci_platform.c (e.g., reset control, subsystem setting).
changes since v3:
- update binding text: fix a typo and modify compatible strings.
changes since v2:
- according to Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines").
replace devm_reset_control_get_optional() by devm_reset_control_get_optional_exclusive().
changes since v1:
- update binding text: add missing "specifier pairs" descriptions.
- fix kbuild test warning: fix the error handling.
Ryder Lee (2):
ata: mediatek: add support for MediaTek SATA controller
dt-bindings: ata: add DT bindings for MediaTek SATA controller
Documentation/devicetree/bindings/ata/ahci-mtk.txt | 51 ++++++
drivers/ata/Kconfig | 10 ++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++
4 files changed, 258 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
create mode 100644 drivers/ata/ahci_mtk.c
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2] cs5536: add support for IDE controller variant
From: Tejun Heo @ 2017-08-11 17:35 UTC (permalink / raw)
To: Andrey Korolyov; +Cc: linux-ide, hch
In-Reply-To: <20170810102114.22332-1-andrey@xdel.ru>
On Thu, Aug 10, 2017 at 01:21:14PM +0300, Andrey Korolyov wrote:
> Several legacy devices such as Geode-based Cisco ASA appliances
> and DB800 development board do possess CS5536 IDE controller
> with different PCI id than existing one. Using pata_generic is
> not always feasible as at least DB800 requires MSR quirk from
> pata_cs5536 to be used with vendor firmware.
>
> Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
> CC: stable@vger.kernel.org
Applied to libata/for-4.14.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 1/2] ata: sata_gemini: Retire custom pin control
From: Tejun Heo @ 2017-08-11 17:32 UTC (permalink / raw)
To: Linus Walleij
Cc: Bartlomiej Zolnierkiewicz, linux-ide, Janos Laube,
Paulius Zaleckas, linux-arm-kernel, Hans Ulli Kroll,
Florian Fainelli
In-Reply-To: <20170808190704.11574-1-linus.walleij@linaro.org>
On Tue, Aug 08, 2017 at 09:07:04PM +0200, Linus Walleij wrote:
> I added a proper pin control driver for the Gemini SoC, so retire
> this custom code and rely on the pin controller to set up the pads.
>
> The "IOMUX" which is routing signals between the ATA and SATA
> bridge inside of the chip is not about pin control and remains in
> place.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Applied to libata/for-4.14.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 2/2] ata: sata_gemini: Introduce explicit IDE pin control
From: Tejun Heo @ 2017-08-11 17:32 UTC (permalink / raw)
To: Linus Walleij
Cc: Bartlomiej Zolnierkiewicz, linux-ide, Janos Laube,
Paulius Zaleckas, linux-arm-kernel, Hans Ulli Kroll,
Florian Fainelli
In-Reply-To: <20170808190714.11623-1-linus.walleij@linaro.org>
On Tue, Aug 08, 2017 at 09:07:14PM +0200, Linus Walleij wrote:
> The IDE pins are managed by the pin controller, if we want to
> use these, we need to ask the pin controller to explicitly enable
> them as by default, these pins are used for other business and
> most users just rely on the SATA bridge.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Applied to libata/for-4.14.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 1/9] devicetree: bindings: Add sata port phy config parameters in ahci-ceva
From: Michal Simek @ 2017-08-11 12:36 UTC (permalink / raw)
To: Rob Herring, Michal Simek, Anurag Kumar Vulisha
Cc: linux-kernel, monstr, Alexander Graf, Tejun Heo, devicetree,
linux-ide, Mark Rutland
In-Reply-To: <20170810190720.yqeu4qzztylu5slb@rob-hp-laptop>
On 10.8.2017 21:07, Rob Herring wrote:
> On Fri, Aug 04, 2017 at 03:18:10PM +0200, Michal Simek wrote:
>> From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
>>
>> This patch adds device tree bindings for sata port phy parameters
>> in the ahci-ceva.txt file.
>>
>> Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>> .../devicetree/bindings/ata/ahci-ceva.txt | 39 ++++++++++++++++++++++
>> 1 file changed, 39 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
>> index 7ca8b976c13a..f97546f61444 100644
>> --- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt
>> +++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
>> @@ -5,6 +5,36 @@ Required properties:
>> - compatible: Compatibility string. Must be 'ceva,ahci-1v84'.
>> - clocks: Input clock specifier. Refer to common clock bindings.
>> - interrupts: Interrupt specifier. Refer to interrupt binding.
>> + - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
>> + - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
>> + The fields for the above parameter must be as shown below:
>> + ceva,phy-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
>
> phy? Should be pN?
pN will be in v2.
Thanks,
Michal
^ permalink raw reply
* Re: [PATCH v2 2/2] dt-bindings: ata: add DT bindings for MediaTek SATA controller
From: Ryder Lee @ 2017-08-11 3:57 UTC (permalink / raw)
To: Rob Herring
Cc: Hans de Goede, Tejun Heo, devicetree, linux-mediatek,
linux-kernel, linux-ide, Long Cheng
In-Reply-To: <1502418356.18608.10.camel@mtkswgap22>
Hi Rob,
Sorry for the noise letter.
On Fri, 2017-08-11 at 10:25 +0800, Ryder Lee wrote:
> > > +Required properties:
> > > + - compatible : Must be "mediatek,ahci".
> >
> > SoC specific compatible strings please.
>
> Okay.
I took a look at ./ahci-platform.txt. Could we just add a generic
compatible string as below:
compatible: Must be "mediatek,soc-model-ahci", "mediatek,mtk-ahci"
In doing so, we can avoid having an endless list of compatibles for
those MTK SoCs with the same IP block.
> > > +
> > > +Optional properties:
> > > + - power-domains : A phandle and power domain specifier pair to the power
> > > + domain which is responsible for collapsing and restoring
> > > + power to the peripheral.
> > > + - resets : Must contain an entry for each entry in reset-names.
> > > + See ../reset/reset.txt for details.
> > > + - reset-names : Associated names must be: "axi", "sw", "reg".
> > > + - mediatek,phy-mode : A phandle to the system controller, used to enable
> > > + SATA function.
> > > +
> > > +Example:
> > > +
> > > + sata: sata@1a200000 {
> > > + compatible = "mediatek,ahci";
MT7622 should be:
compatible = "mediatek,mt7622-ahci",
"mediatek,mtk-ahci";
Ryder
^ permalink raw reply
* Re: [PATCH v2 2/2] dt-bindings: ata: add DT bindings for MediaTek SATA controller
From: Ryder Lee @ 2017-08-11 2:25 UTC (permalink / raw)
To: Rob Herring
Cc: Hans de Goede, Tejun Heo, devicetree, linux-mediatek,
linux-kernel, linux-ide, Long Cheng
In-Reply-To: <20170810205149.lkphpv7krhdaa23y@rob-hp-laptop>
On Thu, 2017-08-10 at 15:51 -0500, Rob Herring wrote:
> On Mon, Aug 07, 2017 at 05:52:21PM +0800, Ryder Lee wrote:
> > Add DT bindings for the onboard SATA controller present on the MediaTek
> > SoCs.
> >
> > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/ata/ahci-mtk.txt | 50 ++++++++++++++++++++++
> > 1 file changed, 50 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
> >
> > diff --git a/Documentation/devicetree/bindings/ata/ahci-mtk.txt b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
> > new file mode 100644
> > index 0000000..ed04dfc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
> > @@ -0,0 +1,50 @@
> > +MediaTek Seria ATA controller
>
> s/Seria/Serial/
Okay.
> > +
> > +Required properties:
> > + - compatible : Must be "mediatek,ahci".
>
> SoC specific compatible strings please.
Okay.
> > + - reg : Physical base addresses and length of register sets.
> > + - interrupts : Interrupt associated with the SATA device.
> > + - interrupt-names : Associated name must be: "hostc".
> > + - clocks : A list of phandle and clock specifier pairs, one for each
> > + entry in clock-names.
> > + - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
> > + - phys : A phandle and PHY specifier pair for the PHY port.
> > + - phy-names : Associated name must be: "sata-phy".
> > + - ports-implemented : Mask that indicates which ports that the HBA supports
> > + are available for software to use. Useful if PORTS_IMPL
> > + is not programmed by the BIOS, which is true with some
> > + embedded SOC's.
>
> Do you have a variable number of ports and need this in DT? Because it
> looks like you only define having a single phy.
We use this property to set PORTS_IMPL register value to 0x1, or there
is no available port for use.
> But this is a standard prop, so you can just say "see
> ./ahci-platform.txt"
Okay.
> > +
> > +Optional properties:
> > + - power-domains : A phandle and power domain specifier pair to the power
> > + domain which is responsible for collapsing and restoring
> > + power to the peripheral.
> > + - resets : Must contain an entry for each entry in reset-names.
> > + See ../reset/reset.txt for details.
> > + - reset-names : Associated names must be: "axi", "sw", "reg".
> > + - mediatek,phy-mode : A phandle to the system controller, used to enable
> > + SATA function.
> > +
> > +Example:
> > +
> > + sata: sata@1a200000 {
> > + compatible = "mediatek,ahci";
> > + reg = <0 0x1a200000 0 0x1100>;
> > + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "hostc";
> > + clocks = <&pciesys CLK_SATA_AHB_EN>,
> > + <&pciesys CLK_SATA_AXI_EN>,
> > + <&pciesys CLK_SATA_ASIC_EN>,
> > + <&pciesys CLK_SATA_RBC_EN>,
> > + <&pciesys CLK_SATA_PM_EN>;
> > + clock-names = "ahb", "axi", "asic", "rbc", "pm";
> > + phys = <&u3port1 PHY_TYPE_SATA>;
> > + phy-names = "sata-phy";
> > + ports-implemented = <0x1>;
> > + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
> > + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
> > + <&pciesys MT7622_SATA_PHY_SW_RST>,
> > + <&pciesys MT7622_SATA_PHY_REG_RST>;
> > + reset-names = "axi", "sw", "reg";
> > + mediatek,phy-mode = <&pciesys>;
> > + };
> > --
> > 1.9.1
> >
^ permalink raw reply
* (unknown),
From: mitch_128 @ 2017-08-10 21:08 UTC (permalink / raw)
To: linux-ide
[-- Attachment #1: 6807682246.zip --]
[-- Type: application/zip, Size: 2832 bytes --]
^ permalink raw reply
* Re: [PATCH v2 2/2] dt-bindings: ata: add DT bindings for MediaTek SATA controller
From: Rob Herring @ 2017-08-10 20:51 UTC (permalink / raw)
To: Ryder Lee
Cc: Hans de Goede, Tejun Heo, devicetree, linux-mediatek,
linux-kernel, linux-ide, Long Cheng
In-Reply-To: <a7ceb4ed8cc3542169ae8d2d995bdd4707f504e1.1502098458.git.ryder.lee@mediatek.com>
On Mon, Aug 07, 2017 at 05:52:21PM +0800, Ryder Lee wrote:
> Add DT bindings for the onboard SATA controller present on the MediaTek
> SoCs.
>
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> ---
> Documentation/devicetree/bindings/ata/ahci-mtk.txt | 50 ++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
>
> diff --git a/Documentation/devicetree/bindings/ata/ahci-mtk.txt b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
> new file mode 100644
> index 0000000..ed04dfc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
> @@ -0,0 +1,50 @@
> +MediaTek Seria ATA controller
s/Seria/Serial/
> +
> +Required properties:
> + - compatible : Must be "mediatek,ahci".
SoC specific compatible strings please.
> + - reg : Physical base addresses and length of register sets.
> + - interrupts : Interrupt associated with the SATA device.
> + - interrupt-names : Associated name must be: "hostc".
> + - clocks : A list of phandle and clock specifier pairs, one for each
> + entry in clock-names.
> + - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
> + - phys : A phandle and PHY specifier pair for the PHY port.
> + - phy-names : Associated name must be: "sata-phy".
> + - ports-implemented : Mask that indicates which ports that the HBA supports
> + are available for software to use. Useful if PORTS_IMPL
> + is not programmed by the BIOS, which is true with some
> + embedded SOC's.
Do you have a variable number of ports and need this in DT? Because it
looks like you only define having a single phy.
But this is a standard prop, so you can just say "see
./ahci-platform.txt"
> +
> +Optional properties:
> + - power-domains : A phandle and power domain specifier pair to the power
> + domain which is responsible for collapsing and restoring
> + power to the peripheral.
> + - resets : Must contain an entry for each entry in reset-names.
> + See ../reset/reset.txt for details.
> + - reset-names : Associated names must be: "axi", "sw", "reg".
> + - mediatek,phy-mode : A phandle to the system controller, used to enable
> + SATA function.
> +
> +Example:
> +
> + sata: sata@1a200000 {
> + compatible = "mediatek,ahci";
> + reg = <0 0x1a200000 0 0x1100>;
> + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
> + clocks = <&pciesys CLK_SATA_AHB_EN>,
> + <&pciesys CLK_SATA_AXI_EN>,
> + <&pciesys CLK_SATA_ASIC_EN>,
> + <&pciesys CLK_SATA_RBC_EN>,
> + <&pciesys CLK_SATA_PM_EN>;
> + clock-names = "ahb", "axi", "asic", "rbc", "pm";
> + phys = <&u3port1 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
> + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
> + <&pciesys MT7622_SATA_PHY_SW_RST>,
> + <&pciesys MT7622_SATA_PHY_REG_RST>;
> + reset-names = "axi", "sw", "reg";
> + mediatek,phy-mode = <&pciesys>;
> + };
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH 1/9] devicetree: bindings: Add sata port phy config parameters in ahci-ceva
From: Rob Herring @ 2017-08-10 19:07 UTC (permalink / raw)
To: Michal Simek
Cc: linux-kernel, monstr, Alexander Graf, Anurag Kumar Vulisha,
Tejun Heo, devicetree, linux-ide, Mark Rutland
In-Reply-To: <b7692739885fe200a4ea5a4e3828349a406e2247.1501852693.git.michal.simek@xilinx.com>
On Fri, Aug 04, 2017 at 03:18:10PM +0200, Michal Simek wrote:
> From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
>
> This patch adds device tree bindings for sata port phy parameters
> in the ahci-ceva.txt file.
>
> Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> .../devicetree/bindings/ata/ahci-ceva.txt | 39 ++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
> index 7ca8b976c13a..f97546f61444 100644
> --- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt
> +++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
> @@ -5,6 +5,36 @@ Required properties:
> - compatible: Compatibility string. Must be 'ceva,ahci-1v84'.
> - clocks: Input clock specifier. Refer to common clock bindings.
> - interrupts: Interrupt specifier. Refer to interrupt binding.
> + - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
> + - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
> + The fields for the above parameter must be as shown below:
> + ceva,phy-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
phy? Should be pN?
> + CINMP : COMINIT Negate Minimum Period.
> + CIBGN : COMINIT Burst Gap Nominal.
> + CIBGMX: COMINIT Burst Gap Maximum.
> + CIBGMN: COMINIT Burst Gap Minimum.
> + - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
> + - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
> + The fields for the above parameter must be as shown below:
> + ceva,phy-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
> + CWBGMN: COMWAKE Burst Gap Minimum.
> + CWBGMX: COMWAKE Burst Gap Maximum.
> + CWBGN: COMWAKE Burst Gap Nominal.
> + CWNMP: COMWAKE Negate Minimum Period.
> + - ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
> + - ceva,p1-burst-params: Burst timing value for COM parameter for port 1.
> + The fields for the above parameter must be as shown below:
> + ceva,phy-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
> + BMX: COM Burst Maximum.
> + BNM: COM Burst Nominal.
> + SFD: Signal Failure Detection value.
> + PTST: Partial to Slumber timer value.
> + - ceva,p0-retry-params: Retry interval timing value for port 0.
> + - ceva,p1-retry-params: Retry interval timing value for port 1.
> + The fields for the above parameter must be as shown below:
> + ceva,phy-retry-params = /bits/ 16 <RIT RCT>;
> + RIT: Retry Interval Timer.
> + RCT: Rate Change Timer.
>
> Optional properties:
> - ceva,broken-gen2: limit to gen1 speed instead of gen2.
> @@ -16,5 +46,14 @@ Examples:
> interrupt-parent = <&gic>;
> interrupts = <0 133 4>;
> clocks = <&clkc SATA_CLK_ID>;
> + ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
> + ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
> + ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
> + ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
> +
> + ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
> + ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
> + ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
> + ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
> ceva,broken-gen2;
> };
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH v2] cs5536: add support for IDE controller variant
From: Andrey Korolyov @ 2017-08-10 10:21 UTC (permalink / raw)
To: linux-ide; +Cc: andrey, hch
Several legacy devices such as Geode-based Cisco ASA appliances
and DB800 development board do possess CS5536 IDE controller
with different PCI id than existing one. Using pata_generic is
not always feasible as at least DB800 requires MSR quirk from
pata_cs5536 to be used with vendor firmware.
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
CC: stable@vger.kernel.org
---
drivers/ata/pata_amd.c | 1 +
drivers/ata/pata_cs5536.c | 1 +
include/linux/pci_ids.h | 1 +
3 files changed, 3 insertions(+)
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
index 8d4d959..8706533 100644
--- a/drivers/ata/pata_amd.c
+++ b/drivers/ata/pata_amd.c
@@ -616,6 +616,7 @@ static const struct pci_device_id amd[] = {
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_DEV_IDE), 9 },
{ },
};
diff --git a/drivers/ata/pata_cs5536.c b/drivers/ata/pata_cs5536.c
index 6c15a55..dc12552 100644
--- a/drivers/ata/pata_cs5536.c
+++ b/drivers/ata/pata_cs5536.c
@@ -289,6 +289,7 @@ static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
static const struct pci_device_id cs5536[] = {
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_DEV_IDE), },
{ },
};
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index c71e532..4adf616 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -576,6 +576,7 @@
#define PCI_DEVICE_ID_AMD_CS5536_EHC 0x2095
#define PCI_DEVICE_ID_AMD_CS5536_UDC 0x2096
#define PCI_DEVICE_ID_AMD_CS5536_UOC 0x2097
+#define PCI_DEVICE_ID_AMD_CS5536_DEV_IDE 0x2092
#define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A
#define PCI_DEVICE_ID_AMD_LX_VIDEO 0x2081
#define PCI_DEVICE_ID_AMD_LX_AES 0x2082
--
2.10.2
^ permalink raw reply related
* Re: [PATCH] cs5536: add support for IDE controller variant
From: Christoph Hellwig @ 2017-08-10 9:41 UTC (permalink / raw)
To: Andrey Korolyov; +Cc: linux-ide
In-Reply-To: <20170809181926.20015-1-andrey@xdel.ru>
On Wed, Aug 09, 2017 at 09:19:26PM +0300, Andrey Korolyov wrote:
> Several legacy devices such as Geode-based Cisco ASA appliances
> and DB800 development board do possess CS5536 IDE controller
> with different PCI id than existing one. Using pata_generic is
> not always feasible as at least DB800 requires MSR quirk from
> pata_cs5536 to be used with vendor firmware.
Can we please avoid adding new PCI IDs to legacy drivers/ide?
Please resend without that hunk.
^ permalink raw reply
* [PATCH] cs5536: add support for IDE controller variant
From: Andrey Korolyov @ 2017-08-09 18:19 UTC (permalink / raw)
To: linux-ide; +Cc: andrey
Several legacy devices such as Geode-based Cisco ASA appliances
and DB800 development board do possess CS5536 IDE controller
with different PCI id than existing one. Using pata_generic is
not always feasible as at least DB800 requires MSR quirk from
pata_cs5536 to be used with vendor firmware.
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
CC: stable@vger.kernel.org
---
drivers/ata/pata_amd.c | 1 +
drivers/ata/pata_cs5536.c | 1 +
drivers/ide/cs5536.c | 1 +
include/linux/pci_ids.h | 1 +
4 files changed, 4 insertions(+)
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
index 8d4d959..8706533 100644
--- a/drivers/ata/pata_amd.c
+++ b/drivers/ata/pata_amd.c
@@ -616,6 +616,7 @@ static const struct pci_device_id amd[] = {
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_DEV_IDE), 9 },
{ },
};
diff --git a/drivers/ata/pata_cs5536.c b/drivers/ata/pata_cs5536.c
index 6c15a55..dc12552 100644
--- a/drivers/ata/pata_cs5536.c
+++ b/drivers/ata/pata_cs5536.c
@@ -289,6 +289,7 @@ static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
static const struct pci_device_id cs5536[] = {
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_DEV_IDE), },
{ },
};
diff --git a/drivers/ide/cs5536.c b/drivers/ide/cs5536.c
index de9185d..01c250f 100644
--- a/drivers/ide/cs5536.c
+++ b/drivers/ide/cs5536.c
@@ -283,6 +283,7 @@ static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
static const struct pci_device_id cs5536_pci_tbl[] = {
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_DEV_IDE), },
{ },
};
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index c71e532..4adf616 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -576,6 +576,7 @@
#define PCI_DEVICE_ID_AMD_CS5536_EHC 0x2095
#define PCI_DEVICE_ID_AMD_CS5536_UDC 0x2096
#define PCI_DEVICE_ID_AMD_CS5536_UOC 0x2097
+#define PCI_DEVICE_ID_AMD_CS5536_DEV_IDE 0x2092
#define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A
#define PCI_DEVICE_ID_AMD_LX_VIDEO 0x2081
#define PCI_DEVICE_ID_AMD_LX_AES 0x2082
--
2.10.2
^ permalink raw reply related
* [PATCH 2/2] ata: sata_gemini: Introduce explicit IDE pin control
From: Linus Walleij @ 2017-08-08 19:07 UTC (permalink / raw)
To: Tejun Heo, Bartlomiej Zolnierkiewicz, linux-ide
Cc: Janos Laube, Paulius Zaleckas, linux-arm-kernel, Hans Ulli Kroll,
Florian Fainelli, Linus Walleij
The IDE pins are managed by the pin controller, if we want to
use these, we need to ask the pin controller to explicitly enable
them as by default, these pins are used for other business and
most users just rely on the SATA bridge.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/ata/sata_gemini.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/ata/sata_gemini.c b/drivers/ata/sata_gemini.c
index 4990dd496598..0f0fc82bc6c8 100644
--- a/drivers/ata/sata_gemini.c
+++ b/drivers/ata/sata_gemini.c
@@ -15,6 +15,7 @@
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/pinctrl/consumer.h>
#include "sata_gemini.h"
#define DRV_NAME "gemini_sata_bridge"
@@ -287,6 +288,29 @@ static int gemini_sata_bridge_init(struct sata_gemini *sg)
return 0;
}
+static int gemini_setup_ide_pins(struct device *dev)
+{
+ struct pinctrl *p;
+ struct pinctrl_state *ide_state;
+ int ret;
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p))
+ return PTR_ERR(p);
+
+ ide_state = pinctrl_lookup_state(p, "ide");
+ if (IS_ERR(ide_state))
+ return PTR_ERR(ide_state);
+
+ ret = pinctrl_select_state(p, ide_state);
+ if (ret) {
+ dev_err(dev, "could not select IDE state\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int gemini_sata_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -355,6 +379,17 @@ static int gemini_sata_probe(struct platform_device *pdev)
goto out_unprep_clk;
}
+ /*
+ * Route out the IDE pins if desired.
+ * This is done by looking up a special pin control state called
+ * "ide" that will route out the IDE pins.
+ */
+ if (sg->ide_pins) {
+ ret = gemini_setup_ide_pins(dev);
+ if (ret)
+ return ret;
+ }
+
dev_info(dev, "set up the Gemini IDE/SATA nexus\n");
platform_set_drvdata(pdev, sg);
sg_singleton = sg;
--
2.9.4
^ permalink raw reply related
* [PATCH 1/2] ata: sata_gemini: Retire custom pin control
From: Linus Walleij @ 2017-08-08 19:07 UTC (permalink / raw)
To: Tejun Heo, Bartlomiej Zolnierkiewicz, linux-ide
Cc: Janos Laube, Paulius Zaleckas, linux-arm-kernel, Hans Ulli Kroll,
Florian Fainelli, Linus Walleij
I added a proper pin control driver for the Gemini SoC, so retire
this custom code and rely on the pin controller to set up the pads.
The "IOMUX" which is routing signals between the ATA and SATA
bridge inside of the chip is not about pin control and remains in
place.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/ata/sata_gemini.c | 34 ----------------------------------
1 file changed, 34 deletions(-)
diff --git a/drivers/ata/sata_gemini.c b/drivers/ata/sata_gemini.c
index 8c704523bae7..4990dd496598 100644
--- a/drivers/ata/sata_gemini.c
+++ b/drivers/ata/sata_gemini.c
@@ -43,17 +43,6 @@ struct sata_gemini {
struct clk *sata1_pclk;
};
-/* Global IDE PAD Skew Control Register */
-#define GEMINI_GLOBAL_IDE_SKEW_CTRL 0x18
-#define GEMINI_IDE1_HOST_STROBE_DELAY_SHIFT 28
-#define GEMINI_IDE1_DEVICE_STROBE_DELAY_SHIFT 24
-#define GEMINI_IDE1_OUTPUT_IO_SKEW_SHIFT 20
-#define GEMINI_IDE1_INPUT_IO_SKEW_SHIFT 16
-#define GEMINI_IDE0_HOST_STROBE_DELAY_SHIFT 12
-#define GEMINI_IDE0_DEVICE_STROBE_DELAY_SHIFT 8
-#define GEMINI_IDE0_OUTPUT_IO_SKEW_SHIFT 4
-#define GEMINI_IDE0_INPUT_IO_SKEW_SHIFT 0
-
/* Miscellaneous Control Register */
#define GEMINI_GLOBAL_MISC_CTRL 0x30
/*
@@ -91,8 +80,6 @@ struct sata_gemini {
#define GEMINI_IDE_IOMUX_MODE2 (2 << 24)
#define GEMINI_IDE_IOMUX_MODE3 (3 << 24)
#define GEMINI_IDE_IOMUX_SHIFT (24)
-#define GEMINI_IDE_PADS_ENABLE BIT(4)
-#define GEMINI_PFLASH_PADS_DISABLE BIT(1)
/*
* Registers directly controlling the PATA<->SATA adapters
@@ -310,7 +297,6 @@ static int gemini_sata_probe(struct platform_device *pdev)
enum gemini_muxmode muxmode;
u32 gmode;
u32 gmask;
- u32 val;
int ret;
sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL);
@@ -362,16 +348,6 @@ static int gemini_sata_probe(struct platform_device *pdev)
gmask = GEMINI_IDE_IOMUX_MASK;
gmode = (muxmode << GEMINI_IDE_IOMUX_SHIFT);
- /*
- * If we mux out the IDE, parallel flash must be disabled.
- * SATA0 and SATA1 have dedicated pins and may coexist with
- * parallel flash.
- */
- if (sg->ide_pins)
- gmode |= GEMINI_IDE_PADS_ENABLE | GEMINI_PFLASH_PADS_DISABLE;
- else
- gmask |= GEMINI_IDE_PADS_ENABLE;
-
ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, gmask, gmode);
if (ret) {
dev_err(dev, "unable to set up IDE muxing\n");
@@ -379,16 +355,6 @@ static int gemini_sata_probe(struct platform_device *pdev)
goto out_unprep_clk;
}
- /* FIXME: add more elaborate IDE skew control handling */
- if (sg->ide_pins) {
- ret = regmap_read(map, GEMINI_GLOBAL_IDE_SKEW_CTRL, &val);
- if (ret) {
- dev_err(dev, "cannot read IDE skew control register\n");
- return ret;
- }
- dev_info(dev, "IDE skew control: %08x\n", val);
- }
-
dev_info(dev, "set up the Gemini IDE/SATA nexus\n");
platform_set_drvdata(pdev, sg);
sg_singleton = sg;
--
2.9.4
^ permalink raw reply related
* Re: [PATCH] ata: make ata_port_operations const
From: Bhumika Goyal @ 2017-08-08 8:11 UTC (permalink / raw)
To: Joe Perches
Cc: Tejun Heo, Julia Lawall, b.zolnierkie, linux-ide, linux-kernel
In-Reply-To: <1502123652.2219.24.camel@perches.com>
On Mon, Aug 7, 2017 at 10:04 PM, Joe Perches <joe@perches.com> wrote:
> On Mon, 2017-08-07 at 09:29 -0700, Tejun Heo wrote:
>> Hello,
>>
>> On Mon, Aug 07, 2017 at 08:54:21PM +0530, Bhumika Goyal wrote:
>> > I compiled the .o files and checked the size before and after
>> > compilation. After making the structure const, bytes should move from
>> > data to text segment of the memory and this is what happened. So, this
>> > is how I tested it.
>>
>> Ah, I see, so the port_operations is never used directly. I'm not
>> sure whether it'd be a good idea to selectively pick these and makr
>> them const. Let's just leave them be.
>
> Why?
>
> Things that are never accessed as other than const should
> be const no?
>
I think it would be better to leave them as in most situations the
ata_port_operations structures cannot be const as they are only used
in the port_ops field of an ata_port_info structure and this field is
not const. Having two ata_port_operations const and others non-const
will cause code inconsistency.
Thanks,
Bhumika
> Why leave unnecessary exposure for muckery?
^ permalink raw reply
* (unknown),
From: mitch_128 @ 2017-08-07 18:38 UTC (permalink / raw)
To: linux-ide
[-- Attachment #1: MESSAGE_5386199_linux-ide.zip --]
[-- Type: application/zip, Size: 10047 bytes --]
^ permalink raw reply
* Re: [PATCH] ata: make ata_port_operations const
From: Joe Perches @ 2017-08-07 16:34 UTC (permalink / raw)
To: Tejun Heo, Bhumika Goyal
Cc: Julia Lawall, b.zolnierkie, linux-ide, linux-kernel
In-Reply-To: <20170807162920.GA537256@devbig577.frc2.facebook.com>
On Mon, 2017-08-07 at 09:29 -0700, Tejun Heo wrote:
> Hello,
>
> On Mon, Aug 07, 2017 at 08:54:21PM +0530, Bhumika Goyal wrote:
> > I compiled the .o files and checked the size before and after
> > compilation. After making the structure const, bytes should move from
> > data to text segment of the memory and this is what happened. So, this
> > is how I tested it.
>
> Ah, I see, so the port_operations is never used directly. I'm not
> sure whether it'd be a good idea to selectively pick these and makr
> them const. Let's just leave them be.
Why?
Things that are never accessed as other than const should
be const no?
Why leave unnecessary exposure for muckery?
^ permalink raw reply
* Re: [PATCH] ata: make ata_port_operations const
From: Tejun Heo @ 2017-08-07 16:29 UTC (permalink / raw)
To: Bhumika Goyal; +Cc: Julia Lawall, b.zolnierkie, linux-ide, linux-kernel
In-Reply-To: <CAOH+1jEQy3PrExruDLWetVd=iWYX3sf13Ku5G5CUUbJGADsNvw@mail.gmail.com>
Hello,
On Mon, Aug 07, 2017 at 08:54:21PM +0530, Bhumika Goyal wrote:
> I compiled the .o files and checked the size before and after
> compilation. After making the structure const, bytes should move from
> data to text segment of the memory and this is what happened. So, this
> is how I tested it.
Ah, I see, so the port_operations is never used directly. I'm not
sure whether it'd be a good idea to selectively pick these and makr
them const. Let's just leave them be.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH] ata: make ata_port_operations const
From: Bhumika Goyal @ 2017-08-07 15:24 UTC (permalink / raw)
To: Tejun Heo; +Cc: Julia Lawall, b.zolnierkie, linux-ide, linux-kernel
In-Reply-To: <20170807150727.GD4050379@devbig577.frc2.facebook.com>
On Mon, Aug 7, 2017 at 8:37 PM, Tejun Heo <tj@kernel.org> wrote:
> Hello,
>
> On Mon, Aug 07, 2017 at 04:02:02PM +0530, Bhumika Goyal wrote:
>> Make ata_port_operations structures const as it is only stored in the
>> inherits field of an ata_port_operations structure. Therefore make it
>> const.
>>
>> Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
>
> How did you test the patch?
>
I compiled the .o files and checked the size before and after
compilation. After making the structure const, bytes should move from
data to text segment of the memory and this is what happened. So, this
is how I tested it.
Thanks,
Bhumika
> Thanks.
>
> --
> tejun
^ permalink raw reply
* Re: [PATCH] ata: make ata_port_operations const
From: Tejun Heo @ 2017-08-07 15:07 UTC (permalink / raw)
To: Bhumika Goyal; +Cc: julia.lawall, b.zolnierkie, linux-ide, linux-kernel
In-Reply-To: <1502101922-13313-1-git-send-email-bhumirks@gmail.com>
Hello,
On Mon, Aug 07, 2017 at 04:02:02PM +0530, Bhumika Goyal wrote:
> Make ata_port_operations structures const as it is only stored in the
> inherits field of an ata_port_operations structure. Therefore make it
> const.
>
> Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
How did you test the patch?
Thanks.
--
tejun
^ permalink raw reply
* [PATCH] ata: make ata_port_operations const
From: Bhumika Goyal @ 2017-08-07 10:32 UTC (permalink / raw)
To: julia.lawall, b.zolnierkie, tj, linux-ide, linux-kernel; +Cc: Bhumika Goyal
Make ata_port_operations structures const as it is only stored in the
inherits field of an ata_port_operations structure. Therefore make it
const.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
---
drivers/ata/pata_sis.c | 2 +-
drivers/ata/sata_via.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/pata_sis.c b/drivers/ata/pata_sis.c
index 626f989..24614d2 100644
--- a/drivers/ata/pata_sis.c
+++ b/drivers/ata/pata_sis.c
@@ -549,7 +549,7 @@ static unsigned long sis_133_mode_filter(struct ata_device *adev, unsigned long
.cable_detect = sis_133_cable_detect,
};
-static struct ata_port_operations sis_base_ops = {
+static const struct ata_port_operations sis_base_ops = {
.inherits = &ata_bmdma_port_ops,
.prereset = sis_pre_reset,
};
diff --git a/drivers/ata/sata_via.c b/drivers/ata/sata_via.c
index 93b8d78..83ba848 100644
--- a/drivers/ata/sata_via.c
+++ b/drivers/ata/sata_via.c
@@ -129,7 +129,7 @@ struct svia_priv {
ATA_BMDMA_SHT(DRV_NAME),
};
-static struct ata_port_operations svia_base_ops = {
+static const struct ata_port_operations svia_base_ops = {
.inherits = &ata_bmdma_port_ops,
.sff_tf_load = svia_tf_load,
};
--
1.9.1
^ permalink raw reply related
* [PATCH v2 0/2] Add support for MediaTek AHCI SATA
From: Ryder Lee @ 2017-08-07 9:52 UTC (permalink / raw)
To: Hans de Goede, Tejun Heo
Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide,
Long Cheng, Ryder Lee
Hi,
This patch series add support for AHCI compatible SATA controller, and it is
compliant with the ahci 1.3 and sata 3.0 specification. This driver is slightly
different than ahci_platform.c (e.g., reset control, subsystem setting).
changes since v2:
- according to Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines").
replace devm_reset_control_get_optional() by devm_reset_control_get_optional_exclusive().
changes since v1:
- update binding text: add missing "specifier pairs" descriptions.
- fix kbuild test warning: fix the error handling.
Ryder Lee (2):
ata: mediatek: add support for MediaTek SATA controller
dt-bindings: ata: add DT bindings for MediaTek SATA controller
Documentation/devicetree/bindings/ata/ahci-mtk.txt | 50 ++++++
drivers/ata/Kconfig | 10 ++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++
4 files changed, 257 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
create mode 100644 drivers/ata/ahci_mtk.c
--
1.9.1
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox