* [PATCH v2] staging: iio: frequency: ad9832: Fix alignment for DMA safety
@ 2022-08-13 16:06 Jonathan Cameron
2022-08-14 19:09 ` Andy Shevchenko
0 siblings, 1 reply; 2+ messages in thread
From: Jonathan Cameron @ 2022-08-13 16:06 UTC (permalink / raw)
To: linux-iio; +Cc: Andy Shevchenko, Nuno Sá, Jonathan Cameron
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition. Whilst here, move the marking to cover
the whole union. That has not functional affect, but makes it slightly
easier to see what is going on.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v2: Move the alignment marking to the union rather than an element in the
union. (Andy Shevchenko)
drivers/staging/iio/frequency/ad9832.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/frequency/ad9832.c
index f43464db618a..6f9eebd6c7ee 100644
--- a/drivers/staging/iio/frequency/ad9832.c
+++ b/drivers/staging/iio/frequency/ad9832.c
@@ -112,10 +112,10 @@ struct ad9832_state {
* transfer buffers to live in their own cache lines.
*/
union {
- __be16 freq_data[4]____cacheline_aligned;
+ __be16 freq_data[4];
__be16 phase_data[2];
__be16 data;
- };
+ } __aligned(IIO_DMA_MINALIGN);
};
static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
--
2.37.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH v2] staging: iio: frequency: ad9832: Fix alignment for DMA safety
2022-08-13 16:06 [PATCH v2] staging: iio: frequency: ad9832: Fix alignment for DMA safety Jonathan Cameron
@ 2022-08-14 19:09 ` Andy Shevchenko
0 siblings, 0 replies; 2+ messages in thread
From: Andy Shevchenko @ 2022-08-14 19:09 UTC (permalink / raw)
To: Jonathan Cameron; +Cc: linux-iio, Nuno Sá, Jonathan Cameron
On Sat, Aug 13, 2022 at 6:55 PM Jonathan Cameron <jic23@kernel.org> wrote:
>
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1. Switch to the updated
> IIO_DMA_MINALIGN definition. Whilst here, move the marking to cover
> the whole union. That has not functional affect, but makes it slightly
not --> no ?
> easier to see what is going on.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ---
> v2: Move the alignment marking to the union rather than an element in the
> union. (Andy Shevchenko)
> drivers/staging/iio/frequency/ad9832.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/frequency/ad9832.c
> index f43464db618a..6f9eebd6c7ee 100644
> --- a/drivers/staging/iio/frequency/ad9832.c
> +++ b/drivers/staging/iio/frequency/ad9832.c
> @@ -112,10 +112,10 @@ struct ad9832_state {
> * transfer buffers to live in their own cache lines.
> */
> union {
> - __be16 freq_data[4]____cacheline_aligned;
> + __be16 freq_data[4];
> __be16 phase_data[2];
> __be16 data;
> - };
> + } __aligned(IIO_DMA_MINALIGN);
> };
>
> static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
> --
> 2.37.1
>
--
With Best Regards,
Andy Shevchenko
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