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From: Jonathan Cameron <jic23@kernel.org>
To: carlos.song@nxp.com
Cc: lars@metafoo.de, rjones@gateworks.com,
	Jonathan.Cameron@huawei.com, haibo.chen@nxp.com,
	linux-imx@nxp.com, linux-iio@vger.kernel.org
Subject: Re: [PATCH v2 6/7] iio: imu: fxos8700: fix ODR register readback and initialization
Date: Sun, 11 Dec 2022 14:01:34 +0000	[thread overview]
Message-ID: <20221211140134.7745473c@jic23-huawei> (raw)
In-Reply-To: <20221208071911.2405922-7-carlos.song@nxp.com>

On Thu,  8 Dec 2022 15:19:10 +0800
carlos.song@nxp.com wrote:

> From: Carlos Song <carlos.song@nxp.com>
> 
> Use the hexadecimal number to read and write the incorrect bits of
> the ODR register. It fails to set MAX ODR mode in chip initialization
> and it will return an incorrect ODR mode to userspace.
> 
> Use of regmap_write() instead of regmap_update_bits() to update bits
> is good for readability. FIELD_GET()/FIELD_PREP() can help clear register
> bit definition and avoid separately to define an offset. Unified use of
> regmap_write(), FIELD_GET()/FIELD_PREP() to read and write correct ODR
> register bits.
> 
> Fixes: 84e5ddd5c46e ("iio: imu: Add support for the FXOS8700 IMU")
> Signed-off-by: Carlos Song <carlos.song@nxp.com>
This should probably be split into the minimal fix and then the
cleanup (which can follow later, keeping the code to backport more minimal.)

Comments inline.

> ---
> Changes for V2:
> - Modify FXOS8700_CTRL_ODR_MSK MASK instead of hexadecimal
> - Use of regmap_write() instead of regmap_update_bits()
> - Use FIELD_GET()/FIELD_PREP() to avoid to separately define an offset
> - Rework commit log
> 
> diff --git a/drivers/iio/imu/fxos8700_core.c b/drivers/iio/imu/fxos8700_core.c
> index 773f62203bf0..b4baef82f6d5 100644
> --- a/drivers/iio/imu/fxos8700_core.c
> +++ b/drivers/iio/imu/fxos8700_core.c
> @@ -10,6 +10,7 @@
>  #include <linux/regmap.h>
>  #include <linux/acpi.h>
>  #include <linux/bitops.h>
> +#include <linux/bitfield.h>
>  
>  #include <linux/iio/iio.h>
>  #include <linux/iio/sysfs.h>
> @@ -144,9 +145,9 @@
>  #define FXOS8700_NVM_DATA_BNK0      0xa7
>  
>  /* Bit definitions for FXOS8700_CTRL_REG1 */
> -#define FXOS8700_CTRL_ODR_MSK       0x38
>  #define FXOS8700_CTRL_ODR_MAX       0x00
>  #define FXOS8700_CTRL_ODR_MIN       GENMASK(4, 3)

Unrelated but this is a very odd thing to see.  A mask for something called _MIN.
It's not used but value is probably wrong.  Best thing is probably just to remove it.

> +#define FXOS8700_CTRL_ODR_MSK       GENMASK(5, 3)
>  
>  /* Bit definitions for FXOS8700_M_CTRL_REG1 */
>  #define FXOS8700_HMS_MASK           GENMASK(1, 0)
> @@ -481,6 +482,7 @@ static int fxos8700_set_odr(struct fxos8700_data *data, enum fxos8700_sensor t,
>  			    int odr, int uodr)
>  {
>  	int i, ret, val;
> +	int odr_mode;
>  	bool active_mode;
>  	static const int odr_num = ARRAY_SIZE(fxos8700_odr);
>  
> @@ -508,10 +510,10 @@ static int fxos8700_set_odr(struct fxos8700_data *data, enum fxos8700_sensor t,
>  	if (i >= odr_num)
>  		return -EINVAL;
>  
> -	return regmap_update_bits(data->regmap,
> -				  FXOS8700_CTRL_REG1,
> -				  FXOS8700_CTRL_ODR_MSK + FXOS8700_ACTIVE,
> -				  fxos8700_odr[i].bits << 3 | active_mode);
> +	odr_mode &= ~FXOS8700_CTRL_ODR_MSK;

This doesn't look right.   You are masking bits out of an uninitialized variable.
I'm guessing intent was to use the value read from the register which is in
val.


> +	odr_mode |= FIELD_PREP(FXOS8700_CTRL_ODR_MSK, fxos8700_odr[i].bits);

> +	return regmap_write(data->regmap, FXOS8700_CTRL_REG1,
> +			   odr_mode | active_mode);
>  }
>  
>  static int fxos8700_get_odr(struct fxos8700_data *data, enum fxos8700_sensor t,
> @@ -524,7 +526,7 @@ static int fxos8700_get_odr(struct fxos8700_data *data, enum fxos8700_sensor t,
>  	if (ret)
>  		return ret;
>  
> -	val &= FXOS8700_CTRL_ODR_MSK;
> +	val = FIELD_GET(FXOS8700_CTRL_ODR_MSK, val);
>  
>  	for (i = 0; i < odr_num; i++)
>  		if (val == fxos8700_odr[i].bits)
> @@ -612,6 +614,7 @@ static const struct iio_info fxos8700_info = {
>  static int fxos8700_chip_init(struct fxos8700_data *data, bool use_spi)
>  {
>  	int ret;
> +	int odr_mode;
>  	unsigned int val;
>  	struct device *dev = regmap_get_device(data->regmap);
>  
> @@ -664,8 +667,10 @@ static int fxos8700_chip_init(struct fxos8700_data *data, bool use_spi)
>  		return ret;
>  
>  	/* Max ODR (800Hz individual or 400Hz hybrid), active mode */
> +	odr_mode &= ~FXOS8700_CTRL_ODR_MSK;
odr_mode not set to anything so you shouldn't be masking bits out of it.

> +	odr_mode |= FIELD_PREP(FXOS8700_CTRL_ODR_MSK, FXOS8700_CTRL_ODR_MAX);
>  	return regmap_write(data->regmap, FXOS8700_CTRL_REG1,
> -			   FXOS8700_CTRL_ODR_MAX | FXOS8700_ACTIVE);
> +			   odr_mode | FXOS8700_ACTIVE);
>  }
>  
>  static void fxos8700_chip_uninit(void *data)


  reply	other threads:[~2022-12-11 13:48 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-08  7:19 [PATCH v2 0/7] iio: imu: fxos8700: fix few bugs in data readback and mode set carlos.song
2022-12-08  7:19 ` [PATCH v2 1/7] iio: imu: fxos8700: fix map lable of channel type to MAGN sensor carlos.song
2022-12-11 13:42   ` Jonathan Cameron
2022-12-08  7:19 ` [PATCH v2 2/7] iio: imu: fxos8700: fix swapped ACCEL and MAGN channels readback carlos.song
2022-12-11 13:43   ` Jonathan Cameron
2022-12-08  7:19 ` [PATCH v2 3/7] iio: imu: fxos8700: fix incompete " carlos.song
2022-12-11 13:45   ` Jonathan Cameron
2022-12-08  7:19 ` [PATCH v2 4/7] iio: imu: fxos8700: fix IMU data bits returned to user space carlos.song
2022-12-11 13:49   ` Jonathan Cameron
2022-12-08  7:19 ` [PATCH v2 5/7] iio: imu: fxos8700: fix ACCEL measurement range selection carlos.song
2022-12-11 13:51   ` Jonathan Cameron
2022-12-08  7:19 ` [PATCH v2 6/7] iio: imu: fxos8700: fix ODR register readback and initialization carlos.song
2022-12-11 14:01   ` Jonathan Cameron [this message]
2022-12-08  7:19 ` [PATCH v2 7/7] iio: imu: fxos8700: fix MAGN sensor scale and unit carlos.song
2022-12-11 14:05   ` Jonathan Cameron

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