From: Jonathan Cameron <jic23@kernel.org>
To: Andy Shevchenko <andriy.shevchenko@intel.com>
Cc: "Gary Chu(楚光庆)" <chuguangqing@inspur.com>, lars <lars@metafoo.de>,
"Michael.Hennerich" <Michael.Hennerich@analog.com>,
dlechner <dlechner@baylibre.com>, "nuno.sa" <nuno.sa@analog.com>,
andy <andy@kernel.org>,
"subhajit.ghosh" <subhajit.ghosh@tweaklogic.com>,
"javier.carrasco.cruz" <javier.carrasco.cruz@gmail.com>,
linux-iio <linux-iio@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 4/4] iio: light: apds9960: convert to use maple tree register cache
Date: Mon, 27 Oct 2025 13:38:06 +0000 [thread overview]
Message-ID: <20251027133806.5e4368bc@jic23-huawei> (raw)
In-Reply-To: <aP8tvj_IPbv65m0T@smile.fi.intel.com>
On Mon, 27 Oct 2025 10:30:54 +0200
Andy Shevchenko <andriy.shevchenko@intel.com> wrote:
> On Sat, Oct 25, 2025 at 11:36:45AM +0800, Gary Chu(楚光庆) wrote:
> > >On Fri, Oct 24, 2025 at 03:38:23PM +0800, Chu Guangqing wrote:
> > >> The maple tree register cache is based on a much more modern data structure
> > >> than the rbtree cache and makes optimisation choices which are probably
> > >> more appropriate for modern systems than those made by the rbtree cache.
>
> ...
>
> > >> .reg_defaults = apds9960_reg_defaults,
> > >> .num_reg_defaults = ARRAY_SIZE(apds9960_reg_defaults),
> > >
> > >^^^^ Be careful with such cases, the cache implementations may behave
> > >differently. Have you tested this on the actual HW?
> > >
> > We have conducted tests on some hardware, and performance improvements were observed,
> > though tests have not been carried out on all hardware models.
> > Neither rbtree nor maple tree directly depends on hardware types (such as CPU or peripheral
> > models). Instead, they rely on the address distribution characteristics (discrete/continuous)
> > of hardware registers. The optimal cache type is determined by the hardware layout.
> > Red-black trees excel at individual operations on discrete addresses, while Maple Trees are
> > proficient in range operations on contiguous addresses.
>
> It's not about the low-level cache implementation, it's about regmap
> abstraction implementation that might differ from cache to cache
> implementations. This all in regard how the cold cache is getting filled up.
> There is a separate discussion (unrelated to the topic of your series) where
> this was brought up.
I appreciate these things can be hard to track down with lots of threads in flight
but any chance of a reference for that? I'd be a little surprised if these uses
are complicated enough to hit corner cases but would like to know more.
I've taken a few similar changes in the past thinking there would be no
practical difference.
Jonathan
> That's why I asked how this was tested.
>
> In any case, up to Jonathan, but I had to rise a potential misbehave, so in my
> opinion this kind of corner cases needs to be tested on real HW.
>
> > >> .max_register = APDS9960_REG_GFIFO_DIR(RIGHT),
> > >> - .cache_type = REGCACHE_RBTREE,
> > >> + .cache_type = REGCACHE_MAPLE,
> > >> };
>
next prev parent reply other threads:[~2025-10-27 13:38 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-24 7:38 [PATCH 0/4] iio: convert to use maple tree register cache Chu Guangqing
2025-10-24 7:38 ` [PATCH 1/4] iio: adc: ade9000: " Chu Guangqing
2025-10-24 7:38 ` [PATCH 2/4] iio: light: veml3235: " Chu Guangqing
2025-10-24 7:38 ` [PATCH 3/4] iio: light: apds9306: " Chu Guangqing
2025-10-27 13:06 ` Subhajit Ghosh
2025-10-24 7:38 ` [PATCH 4/4] iio: light: apds9960: " Chu Guangqing
2025-10-24 8:47 ` Andy Shevchenko
[not found] ` <68fc4591.1.gk94qBPVZajhk94q@inspur.com>
2025-10-27 8:30 ` Andy Shevchenko
2025-10-27 13:38 ` Jonathan Cameron [this message]
2025-10-28 8:10 ` Andy Shevchenko
2025-11-02 12:11 ` Jonathan Cameron
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